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to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? 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h8s/2643 group, h8s/2643f-ztat tm hardware manual 16 users manual rev.3.00 2005.01 renesas 16-bit single-chip microcomputer
rev. 3.00 jan 11, 2005 page ii of liv 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third- party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. keep safety first in your circuit designs! notes regarding these materials
rev. 3.00 jan 11, 2005 page iii of liv general precautions on the handling of products 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the product?s state is undefined. the states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power s upply has been turned on. 4. prohibition of access to undefined or reserved address note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these address. do not access these registers: the system?s operation is not guaranteed if they are accessed.
rev. 3.00 jan 11, 2005 page iv of liv configuration of this manual this manual comprises the following items: 1. precautions in relation to this product 2. configuration of this manual 3. overview 4. table of contents 5. summary 6. description of functional modules cpu and system-control modules on-chip peripheral modules the configuration of the functional description of each module differs according to the module. however, the generic style includes the following items: i) features ii) i/o pins iii) description of registers iv) description of operation v) usage: points for caution when designing an application system that includes this lsi, take the points for caution into account. each section includes points for caution in relation to the descriptions given, and points for caution in usage are given, as required, as the final part of each section. 7. list of registers 8. electrical characteristics 9. appendix product-type codes and external dimensions major revisions or addenda in this version of the manual (only for revised versions) the history of revisions is a summary of sections that have been revised and sections that have been added to earlier versions. this does not include all of the revised contents. for details, confirm by referring to the main description of this manual. 10. appendix/appendices
rev. 3.00 jan 11, 2005 page v of liv preface the h8s/2643 group is a group of high-performance microcontrollers with a 32-bit h8s/2600 cpu core, and a set of on-chip supporting functions required for system configuration. the h8s/2600 cpu can execute basic instructions in one state, and is provided with sixteen 16-bit general registers with a 32-bit internal configuration, and a concise and opt imized instruction set. the cpu can handle a 16 mbyte linear address space (architecturally 4 gbytes). programs based on the high-level language c can also be run efficiently. the address space is divided into eight areas. the data bus width and access states can be selected for each of these areas, and various kinds of memory can be connected fast and easily. single-power-supply flash memory (f-ztat?*) and masked rom versions are available, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently changing specifications. on-chip supporting functions include a 16-bit timer pulse unit (tpu), programmable pulse generator (ppg), 8-bit timer, 14-bit pwm timer (pwm), watchdog timer (wdt), serial communication interface (sci, irda), a/d converter, d/a converter, and i/o ports. it is also possible to incorporate an on-chip pc bus interface (iic) as an option. in addition, dma controller (dmac) and data transfer controller (dtc) are provided, enabling high-speed data transfer without cpu intervention. use of the h8s/2643 group enables easy implementation of compact, high-performance systems capable of processing large volumes of data. this manual describes the hardware of the h8s/2643 group. refer to the h8s/2600 series and h8s/2000 series progra mming manual for a detailed description of the instruction set. note: * f-ztat (flexible-ztat) is a trademark of renesas technology, corp.
rev. 3.00 jan 11, 2005 page vi of liv
rev. 3.00 jan 11, 2005 page vii of liv main revisions for this edition item page revisions (see manual for details) 1.1 overview table 1.1 overview 4 specification amended memory ? flash memory or mask ed rom ? high-speed static ram 5 package ? 144-pin plastic qfp (fp-144 j) ? 144-pin plastic tqfp (tfp-144) specification amended and note deleted product lineup model name masked rom version f-ztat version rom/ram (bytes) packages HD6432643 hd64f2643 256 k/16 k fp-144j tfp-144 hd6432642 ? 192 k/12 k fp-144j tfp-144 hd6432641 ? 128 k/8 k fp-144j tfp-144 1.2 internal block diagram figure 1.1 internal block diagram 6 figure 1.1 amended p77/txd3 p76/rxd3 p75 / tmo3/sck3 p74 / tmo2/ mres p73 / tmo1/ cs7 p72 / tmo0/ cs6 p71 / tmri23/tmci23/ cs5 p70 / tmri01/tmci01/ cs4 port 7
rev. 3.00 jan 11, 2005 page v iii of liv item page revisions (see manual for details) 1.3.1 pin arrangement figure 1.2 pin arrangement (fp- 144 j, tfp-144: top view) 7 figure 1.2 amended a0/pc0 a1/pc1 a2/pc2 a3/pc3 vss a4/pc4 vcc a5/pc5 pwm0/a6/pc6 pwm1/a7/pc7 tioca3/po0/p20 tiocb3/po1/p21 tiocc3/po2/p22 vss a8/pb0 pvcc a9/pb1 a10/pb2 a11/pb3 a12/pb4 a13/pb5 a14/pb6 a15/pb7 tiocd3/po3/p23 tioca4/po4/p24 tiocb4/po5/p25 a16/pa0 a17/pa1 a18/pa2 a19/pa3 vss tioca0/po8/p10 tiocb0/po9/p11 tclka/tiocc0/po10/p12 tclkb/tiocd0/po11/p13 irq0 /tioca1/po12/p14 da3/an15/p97 avss test1 a20/pa4 a21/pa5 a22/pa6 a23/pa7 cs4 /tmci01/tmri01/p70 cs5 /tmci23/tmri23/p71 cs6 /tmo0/p72 cs7 /tmo1/p73 mres /tmo2/p74 sck3/tmo3/p75 rxd3/p76 txd3/p77 md0 md1 md2 nc 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 pd2/d10 pd1/d9 pvcc pd0/d8 vss pe7/d7 pe6/d6 pe5/d5 pe4/d4 p50/txd2 p27/po7/tiocb5 p26/po6/tioca5 pe3/d3 pe2/d2 pe1/d1 pe0/d0 p17/po15/tiocb2/tclkd/pwm3 p16/po14/tioca2/pwm2/ irq1 p15/po13/tiocb1/tclkc 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 top view (fp-144j) (tfp-144) note: * fwe is used only in the flash memory version. 8 table 1.2 amended pin name pin no. mode 4 mode 5 15 pb0/a8 pb0/a8 16 pvcc pvcc 1.3.2 pin functions in each operating mode table 1.2 pin functions in each operating mode 17 pb1/a9 pb1/a9 18 pb2/a10 pb2/a10 19 pb3/a11 pb3/a11 20 pb4/a12 pb4/a12 21 pb5/a13 pb5/a13 22 pb6/a14 pb6/a14 23 pb7/a15 pb7/a15 27 pa0/a16 pa0/a16
rev. 3.00 jan 11, 2005 page ix of liv item page revisions (see manual for details) 9 pin name pin no. mode 4 mode 5 28 pa1/a17 pa1/a17 29 pa2/a18 pa2/a18 30 pa3/a19 pa3/a19 1.3.2 pin functions in each operating mode table 1.2 pin functions in each operating mode 40 pe0/d0 pe0/d0 41 pe1/d1 pe1/d1 42 pe2/d2 pe2/d2 43 pe3/d3 pe3/d3 47 pe4/d4 pe4/d4 48 pe5/d5 pe5/d5 49 pe6/d6 pe6/d6 50 pe7/d7 pe7/d7 11 pin name pin no. mode 4 mode 5 mode 6 mode 7 89 few * 2 fwe * 2 fwe * 2 fwe * 2 102 as / lcas as / lcas as / lcas pf6 103 rd rd rd pf5 104 hwr hwr hwr pf4 105 lwr / adtrg / irq3 pf3/lwr/ adtrg / irq3 pf3/lwr/ adtrg / irq3 pf3/ adtrg / irq3 12 pin name pin no. mode 4 mode 5 mode 6 mode 7 129 pa4/a20 pa4/a20 pa4/a20 pa4 130 pa5/a21 pa5/a21 pa5/a21 pa5 131 pa6/a22 pa6/a22 pa6/a22 pa6 132 pa7/a23 pa7/a23 pa7/a23 pa7 135 p72/tmo0/ cs6 p72/tmo0/ cs6 p72/tmo0/ cs6 p72/tmo0 144 nc * 1 nc * 1 nc * 1 nc * 1
rev. 3.00 jan 11, 2005 page x of liv item page revisions (see manual for details) 1.3.3 pin functions table 1.3 pin functions 13 name and function amended xtal, extal crystal: connects to a crystal oscillator. ? txd4, txd3, txd2, txd1, txd0 transmit data (channel 0 to 4) rxd4, rxd3, rxd2, rxd1, rxd0 receive data (channel 0 to 4) 17 sck4, sck3, sck2, sck1, sck0 serial clock (channel 0 to 4): clock i/o pins. avcc analog power supply: a/d converter and d/a converter power supply pins. ? 18 avss analog ground: analog circuit ground and reference voltage. ? vref analog reference power supply: a/d converter and d/a converter reference voltage input pins. ? pa 7 to pa0 port a: 8-bit i/o port. ? 38 table 2.1 amended function instructions data transfer mov pop * 1 , push * 1 ldm * 5 , stm * 5 2.6.1 overview table 2.1 instruction classification movfpe * 3 , movtpe * 3 note added note: 5. only register er0 to er6 should be used when using the stm/ldm instruction.
rev. 3.00 jan 11, 2005 page xi of liv item page revisions (see manual for details) 2.6.2 instructions and addressing modes table 2.2 combinations of instructions and addressing modes 39 table 2.2 amended function data transfer instruction mov pop, push ldm * 3 , stm * 3 movepe * 1 , movtpe * 1 40 note added note: 3. only register er0 to er6 should be used when using the stm/ldm instruction. 42 table 2.3 amended type instruction size * 1 data transfer ldm * 3 l 2.6.3 table of instructions classified by function table 2.3 instructions classified by function stm * 3 l 47 table 2.3 amended type instruction size * 1 function block data transfer instruction eepmov.b eepmov.w ? ? if r4l 0 then repeat @er5+ @er6+ r4l?1 r4l until r4l = 0 else next; if r4 0 then repeat @er5+ @er6+ r4?1 r4 until r4 = 0 48 note added note: 3. only register er0 to er6 should be used when using the stm/ldm instruction. 2.10.2 stm/ldm instruction 67 2.10.2 added 2.10.3 bit manipulation instructions 2.10.3 added 3.3.1 mode 4 3.3.2 mode 5 3.3.3 mode 6 76 description amended ? port a, b, and c, function as ?
rev. 3.00 jan 11, 2005 page xii of liv item page revisions (see manual for details) 3.4 pin functions in each operating mode 75 description amended the pin functions of ports a to g vary depending on the operating mode. ? table 3.3 amended port mode 4 mode 5 mode 6 mode 7 port a pa7 to pa5 p * /a p * /a p * /a p table 3.3 pin functions in each mode 77 pa 4 to pa0 p/a * p/a * p * /a p 3.5 address map in each operating mode description amended the address space is 16 mbytes in modes 4 to 7 (advanced mode). 5.5.5 irq interrupt 119 5.5.5 added 5.5.6 nmi interrupt usage notes 5.5.6 added 10.1 overview table 10.1 port functions 341 table 10.1 amended port description pins mode 4 mode 5 mode 6 mode 7 port 7 8-bit i/o port p77/txd3 p76/rxd3 p75/tmo3/sck3 p74/tmo2/ mres p73/tmo1/ cs7 p72/tmo0/ cs6 p71/tmri23/tmci23/ cs5 p70/tmri01/tmci01/ cs4 8-bit i/o port also functioning as 8-bit timer i/o pins (tmri01, tmci01, tmri23, tmci23, tmo0, tmo1, tmo2, tmo3), bus control output pins ( cs4 to cs7 ), sci i/o pins (sck3, rxd3, txd3), and the manual reset input pin ( mres ) 8-bit i/o port also function- ing as 8-bit timer i/o pins (tmri01, tmci01, tmri23, tmci23, tmo0, tmo1, tmo2, tmo3), sci i/o pins (sck3, rxd3, txd3), and the manual reset input pin ( mres ) 10.2.1 overview 345 description amended ... port 1 functions are the same in all operation mode s. ... 10.2.2 register configuration 346 (1) port 1 data direction register (p1ddr) description amended ? because ppg and tpu are initialized at a manual reset, ?
rev. 3.00 jan 11, 2005 page x iii of liv item page revisions (see manual for details) 10.2.3 pin functions 348 description amended ? topca2, and tiocb2), external interrupt input pins (irq0 and irq1), and 14-bit pwm output pins (pwm2 and pwm3). ? table 10.3 port 1 pin functions 352 table 10.3 amended pin selection method and pin functions p13/po11/ tiocd0/tclkb the pin function is switched as shown below according to the combination of the tpu channel 0 setting (by bits md3 to md0 in tmdr0, bits iod3 to iod0 in tior0l, and bits cclr2 to cclr0 in tcr0), bits tpsc2 to tpsc0 in tcr0 to tcr2, bit nder11 in nderh, and bit p13ddr. tpu channel 0 setting table below (1) table below (2) p13ddr ? 011 nder11 ?? 01 pin function tiocd0 output p13 input p13 output po11 output tiocd0 input * 1 tclkb input * 2 353 pin selection method and pin functions p12/po10/ tiocc0/tclka the pin function is switched as shown below according to the combination of the tpu channel 0 setting (by bits md3 to md0 in tmdr0, bits ioc3 to ioc0 in tior0l, and bits cclr2 to cclr0 in tcr0), bits tpsc2 to tpsc0 in tcr0 to tcr5, bit nder10 in nderh, and bit p12ddr. tpu channel 0 setting table below (1) table below (2) p12ddr ? 011 nder10 ?? 01 pin function tiocc0 output p12 input p12 output po10 output tiocc0 input * 1 tclka input * 2 354 pin selection method and pin functions p11/po9/tiocb0 the pin function is switched as shown below according to the combination of the tpu channel 0 setting (by bits md3 to md0 in tmdr0, and bits iob3 to iob0 in tior0h), bit nder9 in nderh, and bit p11ddr. tpu channel 0 setting table below (1) table below (2) p11ddr ? 011 nder9 ?? 01 pin function tiocb0 output p11 input p11 output po9 output tiocb0 input * 355 pin selection method and pin functions p10/po8/tioca0 the pin function is switched as shown below according to the combination of the tpu channel 0 setting (by bits md3 to md0 in tmdr0, bits ioa3 to ioa0 in tior0h, and bits cclr2 to cclr0 in tcr0), bit nder8 in nderh, and bit p10ddr. tpu channel 0 setting table below (1) table below (2) p10ddr ? 011 nder8 ?? 01 pin function tioca0 output p10 input p10 output po8 output tioca0 input * 1
rev. 3.00 jan 11, 2005 page xiv of liv item page revisions (see manual for details) 10.3.2 register configuration 357 (1) port 2 data direction register (p2ddr) description amended ... and in software standby mode. ppg and tpu are initialized by a manual reset, so the pin states are determined by the specification of p2ddr and p2dr. 10.4.2 register configuration 368 (1) port 3 data direction register (p3ddr) description amended sci and iic are initialized by a manual reset, so the pin state s are determined by the specification of p3ddr and p3dr. 10.4.3 pin functions 370 description amended the port 3 pins double as sci i/o input pins (txd0, rxd0, sck0, irtxd , irrxd , txd1, rxd1, sck1, txd4, rxd4, sck4) , external interrupt input pins ( irq4 , irq5 ) and iic i/o pins (scl0, sda0, scl1, sda1). 10.6.2 register configuration 376 (1) port 5 data direction register (p5ddr) description amended ? p5ddr is initialized to h'0 (bits 2 to 0) by a power-on reset and in hardware standby mode. ... and in software standby mode. as the sci is initialized by a manual reset, the pin states are determined by the p5ddr and p5dr specifications. (2) port 5 data register (p5dr) description amended ? p5dr is initialized to h'0 (bits 2 to 0) by a power-on reset and in hardware standby mode. ?
rev. 3.00 jan 11, 2005 page xv of liv item page revisions (see manual for details) 10.7.1 overview 379 description amended ? bus control output pins ( cs4 to cs7 ), sci i/o pins (sck3, rxd3, txd3) and manual reset input pin ( mres ). ? figure 10.6 port 7 pin functions figure 10.6 amended p77 / p76 / p75 / p74 / p73 / p72 / p71 / p70 / p77 (i/o) / p76 (i/o) / p75 (i/o) / p74 (i/o) / p73 (i/o) / p72 (i/o) / p71 (i/o) / p70 (i/o) / txd3 rxd3 tmo3 sck3 tmo2 / mres tmo1 / cs7 tmo0 / cs6 tmri23 / tmci23 / cs5 tmri01 / tmci01 / cs4 port 7 pins pins functions for modes 4 to 6 modes 7 pin functions port 7 txd3 (output) rxd3 (input) tmo3 (output) / sck3 (i/o) tmo2 (output) / mres (input) tmo1 (output) / cs7 (output) tmo0 (output) / cs6 (output) tmri23 (input) / tmci23 (input) / cs5 (output) tmri01 (input) / tmci01 (input) / cs4 (output) p77 (i/o) / p76 (i/o) / p75 (i/o) / p74 (i/o) / p73 (i/o) / p72 (i/o) / p71 (i/o) / p70 (i/o) / txd3 (output) rxd3 (input) tmo3 (output) / sck3 (i/o) tmo2 (output) / mres (input) tmo1 (output) tmo0 (output) tmri23 (input) / tmci23 (input) tmri01 (input) / tmci01 (input) 10.7.2 register configuration 380 (1) port 7 data direction register (p7ddr) description amended ... and in software standby mode. the 8-bit timer and sci are initialized by a manual reset so the pin state s are determined by the specification of p7ddr and p7dr. 10.7.3 pin functions 382 description amended ? bus control output pins ( cs4 to cs7 ), sci i/o pins (sck3, rxd3, txd3) and manual reset input pin ( mres ). ? table 10.12 port 7 pin function 383 table 10.12 amended pin selection method and pin functions p72/tmo0/ cs6 switches as follows according to combinations of operating mode and os3 to os0 bits of 8-bit timer tcsr0, and the p72ddr bit. operating mode modes 4 to 6 mode 7 os3 to os0 all 0 any is 1 all 0 any is 1 p72ddr 0 1 ? 01 ? pin function p72 input pin cs6 output pin tmo0 output p72 input pin p72 output pin tmo0 output
rev. 3.00 jan 11, 2005 page xvi of liv item page revisions (see manual for details) 10.8.2 register configuration 386 (1) port 8 data direction register (p8ddr) description amended ... and in software standby mode. dmac is initialized by a manual reset, so the pin states are determined by the specification of p8ddr and p8dr. 10.10.2 register configuration 393 (1) port a data direction register (paddr) description amended ? paddr is initialized to h'00 by a power-on reset, and in hardware standby mode. ? when a transition is made to software standby mode. see section 24.2.1, standby control register (sbycr), for details. ? modes 4 to 6 ? irrespective of the value of paddr. when pins are not used as address outputs, ? 394 (2) port a data register (padr) description amended ? padr is initialized to h'00 by a power-on reset, and in hardware standby mode. ? 395 (4) port a mos pill-up control register (papcr) description amended ? in modes 4 to 6, if a pin is in the input state in accordance with the settings in pfcr, and in ddr, setting the corresponding papcr bit to 1 turns on the mos input pill-up for than pin. in mode 7, if a pin is in the input state in accordance with the settings in ddr, setting the corresponding papcr bit to 1 turns on the mos input pill-up for than pin. papcr is initialized by a manual reset or to h'00 by a power-on reset, and in hardware standby mode. ? (5) port a open drain control register (paodr) description amended ? paodr is initialized to h'00 by a power-on reset, and in hardware standby mode. ? 10.11.1 overview 398 description amended port b is n 8-bit i/o port. port b pins also function as address bus outputs; ...
rev. 3.00 jan 11, 2005 page xvii of liv item page revisions (see manual for details) 10.12.1 overview figure 10.15 port c pin functions 404 figure 10.15 amended pc7/a7/pwm1 pc6/a6/pwm0 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 port c port c pins pin functions in mode 7 a7 a6 a5 a4 a3 a2 a1 a0 (output) (output) (output) (output) (output) (output) (output) (output) pin functions in modes 4 and 5 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (i/o) / pwm1 (output) (i/o) / pwm0 (output) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) pin functions in mode 6 a7 a6 a5 a4 a3 a2 a1 a0 when pcddr = 1 (output) (output) (output) (output) (output) (output) (output) (output) pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 when pcddr = 0 (input) / pwm1 (output) (input) / pwm0 (output) (input) (input) (input) (input) (input) (input) 10.15.1 overview figure 10.25 port f pin functions 423 figure 10.25 amended pf7 / pf6 / as / lcas pf5 / rd pf4 / hwr pf3 / lwr / adtrg / irq3 pf2 / lcas / wait / breqo pf1 / back /buzz pf0 / breq / irq2 port f port f pins 10.16.2 register configuration 429 (1) port g data direction register (pgddr) description amended ? in modes 4 and 5, the pgddr are initialized to h'10 (bit s 4 to 0) ?
rev. 3.00 jan 11, 2005 page xv iii of liv item page revisions (see manual for details) 11.2.9 timer synchro register (tsyr) 472 description amended tsyr is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 5 tcnt counters. 15.1.2 block diagram figure 15.1 (a) block diagram of wdt0 598 figure 15.1 (a) amended overflow interrupt control wovi 0 (interrupt request signal) wdtovf internal reset signal * 1 reset control rstcsr tcnt tscr /2 * 2 /64 * 2 /128 * 2 /512 * 2 /2048 * 2 /8192 * 2 /32768 * 2 /131072 * 2 clock clock select internal clock sources bus interface module bus legend: tcsr: tcnt: rstcsr: notes: timer control/status register timer counter reset control/status register internal bus wdt 1. the type of internal reset signal depends on a register setting. there are two alternative types of reset, namely power-on reset and manual reset. 2. the in the subactive and subsleep modes is sub. 15.2.2 timer control/status register (tcsr) 605 wdt1 input clock select note * 2 added notes: 1. an overflow period is the time interval between the start of counting up from h ? 00 on the tcnt and the occurrence of a tcnt overview. 2. the in the subactive and subsleep modes is sub. 17.2.4 serial control register (scr) 708 bits 1 and 0 ? clock enable 1 and 0 (cke1, cke0): table amended (before) c/ a, gm (after) c/ a , gm 17.3.5 clock 715 description amended ... where: n = value set in brr (0 n 255) ... 716 ... n is an integer, 0 n 255, and the smaller error is specified.
rev. 3.00 jan 11, 2005 page xix of liv item page revisions (see manual for details) 17.3.6 data transfer operations 718 (2) serial data transmission description amended for details, see (6), interrupt operation (except block transfer mode), and (7), data transfer operation by dmac or dtc. 722 (3) serial data reception (except block transfer mode) description amended for details, see (6), interrupt operation (except block transfer mode), and (7), data transfer operation by dmac or dtc. 18.2.2 slave address register (sar) 739 bit 0 ? format select (fs): description amended bit 0 ? format select (fs): used together with the fsx bit in sarx to select the communication format. 740 bit table amended sar bit 0 sarx bit 0 0 0i 2 c bus format ? sar and sarx slave addresses recognized 1i 2 c bus format (initial value ) ? sar slave address recognized ? sarx slave address ignored 1 0i 2 c bus format ? sar slave address ignored ? sarx slave address recognized 1 synchronous serial format ? sar and sarx slave addresses ignored 18.2.3 second slave address register (sarx) bit 0 ? format select x (fsx): description amended used together with the fs bit in sar to select the communication format.
rev. 3.00 jan 11, 2005 page xx of liv item page revisions (see manual for details) 18.2.4 i 2 c bus mode register (icmr) 743 bits 5 to 3 ? serial clock select (cks2 to cks0): note * added to bit table scrx bit 5 or 6 bit 5 bit 4 bit 3 transfer rate iicx cks2 cks1 cks0 clock = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz = 25 mhz 0000 /28 179 khz 286 khz 357 khz 571 khz * 714 khz * 893 khz * 1 /40 125 khz 200 khz 250 khz 400 khz 500 khz * 625 khz * 10 /48 104 khz 167 khz 208 khz 333 khz 417 khz * 521 khz * 1 /64 78.1 khz 125 khz 156 khz 250 khz 313 khz 391 khz note: * outside the allowable range for the i 2 c bus interface standard (normal mode: max. 100 khz, high-speed mode: max. 400 khz). 18.2.5 i 2 c bus control register (iccr) 746 bit 4 ? transmit/receive select (trs) no.4 description deleted from clearing conditions 18.2.6 i 2 c bus status register (icsr) 757 bit 0 ? acknowledge bit (ackb) description added ... the value set by internal software is read. in addition, writing to this bit overwrites the setting for acknowledge data sent when receiving data, regardless of the trs value. in this case the value loaded from the receive device is maintained unchanged, so caution is necessary when using instructions that manipulate the bits in this register. 18.3.5 slave transmit operation figure 18.11 example of slave transmit mode operation timing (mls = 0) 771 figure 18.11 amended sda (slave output) scl (slave output) 9 8 scl (master output) slave receive mode a
rev. 3.00 jan 11, 2005 page xxi of liv item page revisions (see manual for details) table 18.7 amended time indication iicx t cyc indication i 2 c bus specifi- cation (max.) = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz = 25 mhz = 28 mhz 0 7.5 t cyc standard mode 1000 ns 1000 ns 937 ns 750 ns 468 ns 375 ns ? high-speed mode 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns ? ? ? 1 17.5 t cyc standard mode 1000 ns 1000 ns 1000 ns 1000 ns 1000 ns 875 ns 700 ns 624 ns high-speed mode 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns 18.4 usage notes table 18.7 permissible scl rise time (t sr ) values 782 note added note:when 7.5 t cyc is selected as the transfer rate, the actual transfer rate may be extended if exceeds 20 mhz. 788 to 792 (10) notes on iric flag clearance when using wait function (11) notes on icdr reads and iccr access in slave transmit mode (12) notes on trs bit setting in slave mode (13) notes on icdr reads in transmit mode and icdr writes in receive mode (14) notes on acke bit and trs bit in slave mode (15) notes on arbitration lost in master mode description added 19.2.2 a/d control/status register (adcsr) 798 bit 7 ? a/d end flag (adf): description amended [clearing conditions] ? when 0 is written to the adf flag after reading adf = 1 ? when the dmac or dtc is activated by an adi interrupt and addr is read 19.4.3 input sampling and a/d conversion time 808 description amended ... at least 10 s when av cc 4.5v, and at least 16 s when av cc < 4.5v. 19.6 usage notes 811 (1) setting range of analog power supply and other pins: (a) analog input voltage range description amended the voltage applied to analog input pin ann during a/d conversion should be in the range avss ann vref. table 19.7 analog pin specifications 812 table 19.7 amended unit of permissible signal source impedance unit (before) k (after) k ?
rev. 3.00 jan 11, 2005 page xxii of liv item page revisions (see manual for details) 20.1.4 register configuration table 20.2 d/a converter registers 819 table 20.2 amended channel name abbreviation r/w initial value address * all module stop control register a mstpcra r/w h'3f h'fde8 module stop control register c mstpcrc r/w h'ff h'fdea 22.11.1 socket adapter and memory map 874 22.11.1 replaced 891 table 22.27 amended abbreviation address flmcr1 h'ff a8 flmcr2 h'ff a9 ebr1 h'ff aa ebr2 h'ff ab 22.14 note on switching from f- ztat version to masked rom version table 22.27 registers present in f-ztat version but absent in mask ed rom version ramer h'fedb 23.2.2 low-power control register (lpwrcr) 896 bits 1 and 0 ? frequency multiplication factor (stc1, stc0): note description added note: in section 25, electrical characteristics. current consumption and noise can be reduced by using this function ? s pll 4 setting and lowering the external clock frequency. 23.3.2 external clock input table 23.4 external clock input conditions 900 (2) external clock clock low pulse width level and clock high pulse width level test conditions amended (before) 5mhz (after) 5 mhz 24.12 clock output disabling function 931 description added ... in each processing state. using the on-chip pll circuit to lower the oscillator frequency or prohibiting external clock output also have the effect of reducing unwanted electromagnetic interference * . therefore, consideration should be given to these options when deciding on system board settings. note: * electromagnetic interference: emi (electro magnetic interference)
rev. 3.00 jan 11, 2005 page xx iii of liv item page revisions (see manual for details) table 25.2 (1) amended conditions: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to avcc, v ss = av ss = pllv ss = 0 v, t a = ? 20 c to +75 c (regular specifications), t a = ? 40 c to +85 c (wide- range specifications) * 1 25.2 dc characteristics table 25.2 dc characteristics (1) 934 item symbol min. typ. max. unit test conditions input leakage res , fwe * 5 | i in ? 1.0 a v in = current stby , nmi, md2 to md0 ?? 1.0 a 0.5 to pv cc ? 0.5 v ports 4, 9 ?? 1.0 a v in = 0.5 to av cc ? 0.5 v three-state leakage current (off state) ports 1, 2, 3, 5, 7, 8, a to g i tsi ?? 1.0 a v in = 0.5 to pv cc ? 0.5 v current dissipation * 2 standby mode ? 1.0 5.0 a t a 50 c ?? 20 50?c < t a | 936 item symbol min. typ. max. unit test conditions ram standby voltage * 3 v ram 2.0 v notes amended notes: 1. ... set v ref ? ? * 7 , v ref = 3.6 v to av cc * 8 , v ss = av ss = pllv ss = 0 v, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) * 1 item symbol min. typ. max. unit test conditions input leakage res , fwe * 6 | i in 1.0 a v in = current stby , nmi, md2 to md0 1.0 a pv 0.5 to cc 0.5 v ports 4, 9 1.0 a v in = 0.5 to av cc 0.5 v | 938 item symbol min. typ. max. unit test conditions three-state leakage current (off state) ports 1, 2, 3, 5, 7, 8, a to g 1.0 a v in = pv cc 0.5 v 0.5 to current dissipation * 3 standby mode 1.0 5.0 a t a ? c 20 50 ? c < t a | |
rev. 3.00 jan 11, 2005 page xxiv of liv item page revisions (see manual for details) 25.2 dc characteristics table 25.2 dc characteristics (2) 939 table 25.2 (2) amended item symbol min typ max unit test conditions port power supply operating pi cc 10 pv cc = 5.0 v 16 ma current * 3 subclock operation 50 a standby 0.5 5.0 t a 20 50 * 4 v ram 2.0 v notes amended notes: 1. * 1 , v ref = 3.6 v to av cc * 2 , v ss = av ss = pllv ss = 0 v, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) * 1 notes added notes:1. av cc = 3.3 v to 5.5 v if the a/d and d/a converters are not used (used as i/o ports). 2. v ref = 3.3 v to av cc if the a/d and d/a converters are not used (used as i/o ports). table 25.4 bus drive characteristics 941 table 25.4 conditions amended (before) v ss = av ss = 0 v
rev. 3.00 jan 11, 2005 page xxv of liv item page revisions (see manual for details) 25.3.1 clock timing table 25.5 clock timing to 25.3.4 dmac timing table 25.8 dmac timing 943 to 957 table 25.5 to 25.8 conditions amended condition a: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 3.0 v to 5.5 v, av cc = 3.6 v to 5.5 v * 1 , v ref = 3.6 v to av cc * 2 , v ss = av ss = pllv ss = 0 v, 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) condition b: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = av ss = pllv ss = 0 v, 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) notes added notes: 1. av cc = 3.3 v to 5.5 v if the a/d and d/a converters are not used (used as i/o ports). 2. v ref = 3.3 v to av cc if the a/d and d/a converters are not used (used as i/o ports). 25.3.5 timing of on- chip supporting modules table 25.9 timing of on-chip supporting modules 961, 962 table 25.9 conditions amended condition a: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 3.0 v to 5.5 v, av cc = 3.6 v to 5.5 v * 2 , v ref = 3.6 v to av cc * 3 , v ss = av ss = pllv ss = 0 v, * 1 , 2 to 16 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) condition b: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = av ss = pllv ss = 0 v, * 1 , 2 to 25 mhz, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) notes 2 and 3 added note s: 1. only available i/o port, tmr, wdt0, and wdt1. 2. av cc = 3.3 v to 5.5 v if the a/d and d/a converters are not used (used as i/o ports). 3. v ref = 3.3 v to av cc if the a/d and d/a converters are not used (used as i/o ports).
rev. 3.00 jan 11, 2005 page xxvi of liv item page revisions (see manual for details) 25.3.5 timing of on- chip supporting modules table 25.10 i 2 c bus timing 967 table 25.10 conditions replaced notes 2 and 3 added note s: 1. 17.5 t cyc can be set * 1 , v ref = 3.6 v to av cc * 2 , v ss = av ss = pllv ss = 0 v, 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) condition b: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = av ss = pllv ss = 0 v, 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) notes added notes: 1. av cc = 3.3 v to 5.5 v if the a/d and d/a converters are not used (used as i/o ports). 2. v ref = 3.3 v to av cc if the a/d and d/a converters are not used (used as i/o ports). 25.6 flash memory characteristics table 25.13 flash memory characteristics 971 table 25.13 conditions amended conditions: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = pllv ss = 0 v, t a = 20 c to +75 c (regular specifications), t a = 40 c to +85 c (wide-range specifications) 1005 table a.2 amended and note * 3 added ldm * 3 1006 mov.l #xx:32, erd 1010 stm * 3 a.2 instruction codes table a.2 instruction codes 1011 notes:
rev. 3.00 jan 11, 2005 page xxvii of liv item page revisions (see manual for details) a.4 number of states required for instruction execution table a.5 number of cycles in instruction execution 1024 note * 5 added to table a.5 ldm * 5 1028 stm * 5 1029 notes: * 9 added to table a.6 ldm.l @sp+, (ern-ern+1) * 9 ldm.l @sp+, (ern-ern+2) * 9 ldm.l @sp+, (ern-ern+3) * 9 1042 stm.l (ern-ern+1) @-sp * 9 stm.l (ern-ern+2) @-sp * 9 stm.l (ern-ern+3) @-sp * 9 1043 notes: address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width (bits) h'ffb9 porta pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 port 8 b.2 functions 1062 scrx serial control register x h'fdb4 iic figure amended 7 0 r/w 6 iicx1 0 r/w 5 iicx0 0 r/w 4 iice 0 r/w 3 flshe 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w i 2 c transfer rate select 1, 0 i 2 c master enable 0 disables cpu access of i 2 c bus interface data register and control register 1 enables cpu access of i 2 c bus interface data register and control register bit initial value r/w : : : the master mode transfer rate is selected in combination with cks2 to cks0 in icmr. for details, see the section on the i 2 c bus mode register. 0 flash control registers deselected in area h'ffffa8 to h'ffffac 1 flash control registers selected in area h'ffffa8 to h'ffffac flash memory control register enable
rev. 3.00 jan 11, 2005 page xxv iii of liv item page revisions (see manual for details) b.2 functions 1075 ssr0 ? ? ? ? ? * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r transmit data register empty (tdre) 0 [clearing conditions] ? ? ? ? ? ? ? * 1 ? ? * 2 framing error (fer) 0 [clearing condition] * 1 ? ? * 1 ? ? * 2 transmit end (tend) 0 [clearing conditions] ? ? ? ? * ? multiprocessor bit = 0 is received 1 [setting condition] ? multiprocessor bit = 1 is received note: * the existing status is continued when, in multi- processor format, the scr re bit is cleared to 0. multiprocessor bit transfer (mpbt) 0 transfer data multiprocessor bit = 0 1 transfer data multiprocessor bit = 1 notes: 1. the per flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the per flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. bit initial value r/w : : : note: * only 0 can be written to these bits (to clear these flags).
rev. 3.00 jan 11, 2005 page xxix of liv item page revisions (see manual for details) b.2 functions 1078 syscr ? 0 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 mrese 0 r/w 1 0 0 mac saturation manual reset disabled pins p74/tmo2/ mres can be used as p74/tmo2 i/o pins manual reset enabled pins p74/tmo2/ mres can be used as mres input pins 1 non-saturating calculation for mac instruction saturating calculation for mac instruction 0 1 interrupt control mode 1, 0 internal ram disabled internal ram enabled 0 1 nmi edge select ram enable manual reset select bit 0 0 0 interrupt controlled by bit i intm0 description intm1 interrupt control mode 1 do not set 0 1 2 interrupt controlled by bits i2 to i0 and ipr 1 do not set bit initial value r/w : : : pin 0 1 1 1 res mres reset type power-on reset manual reset operation state 0 1 interrupt request issued on falling edge of nmi input interrupt request issued on rising edge of nmi input 0 1 1080 figure amended mdcr mode control register h'fde7 system 7 1 r/w 6 0 5 0 4 0 3 0 0 mds0 * r 2 mds2 * r 1 mds1 * r mode select 2 to 0 * input level determined b y mode pins. bit initial value r/w note: * determined b y pins md2 to md0. : : :
rev. 3.00 jan 11, 2005 page xxx of liv item page revisions (see manual for details) b.2 functions 1080 mstpcra module stop control register ah'fde8 system 7 mstpa7 0 r/w 6 mstpa6 0 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w 0 mstpa0 1 r/w module stop 0 module stop mode is cleared 1 module stop mode is set bit initial value r/w : : : mstpcrb module stop control register bh'fde9 system 7 mstpb7 1 r/w 6 mstpb6 1 r/w 5 mstpb5 1 r/w 4 mstpb4 1 r/w 3 mstpb3 1 r/w 2 mstpb2 1 r/w 1 mstpb1 1 r/w 0 mstpb0 1 r/w module stop 0 module stop mode canceled 1 module stop mode enabled bit initial value r/w : : : 1081 mstpcrc module stop control register c h'fdea system figure amended 7 mstpc7 1 r/w 6 mstpc6 1 r/w 5 mstpc5 1 r/w 4 mstpc4 1 r/w 3 mstpc3 1 r/w 2 mstpc2 1 r/w 1 mstpc1 1 r/w 0 mstpc0 1 r/w module stop module stop mode canceled module stop mode enabled 0 1 bit initial value r/w : : : 1083 lpwrcr low-power control register h'fdec system figure amended 0 stc0 0 r/w 1 stc1 0 r/w frequency multiplier stc1 stc0 0 0
rev. 3.00 jan 11, 2005 page xxxi of liv item page revisions (see manual for details) b.2 functions 1094 ndrh next data register h h'fe2c, h'fe2e ppg figure amended 7 ndr15 0 r/w 6 ndr14 0 r/w 5 ndr13 0 r/w 4 ndr12 0 r/w 3 ndr11 0 r/w 0 ndr8 0 r/w 2 ndr10 0 r/w 1 ndr9 0 r/w bit initial value r/w address: h'fe2c address: h'fe2e address: h'fe2e address: h'fe2c same trigger for pulse output groups: : : : 7 1 6 1 5 1 4 1 3 1 0 1 2 1 1 1 bit initial value r/w : : : 7 ndr15 0 r/w 6 ndr14 0 r/w 5 ndr13 0 r/w 4 ndr12 0 r/w 3 1 0 1 2 1 1 1 bit initial value r/w different triggers for pulse output groups: : : : 7 1 6 1 5 1 4 1 3 ndr11 0 r/w 0 ndr8 0 r/w 2 ndr10 0 r/w 1 ndr9 0 r/w bit initial value r/w : : :
rev. 3.00 jan 11, 2005 page xxxii of liv item page revisions (see manual for details) b.2 functions 1095 ndrl next data register l h'fe2d, h'fe2f ppg figure amended 7 1 6 1 5 1 4 1 3 1 0 1 2 1 1 1 bit initial value r/w : : : 7 ndr7 0 r/w 6 ndr6 0 r/w 5 ndr5 0 r/w 4 ndr4 0 r/w 3 ndr3 0 r/w 0 ndr0 0 r/w 2 ndr2 0 r/w 1 ndr1 0 r/w bit initial value r/w : : : 7 1 6 1 5 1 4 1 3 ndr3 0 r/w 0 ndr0 0 r/w 2 ndr2 0 r/w 1 ndr1 0 r/w bit initial value r/w : : : 7 ndr7 0 r/w 6 ndr6 0 r/w 5 ndr5 0 r/w 4 ndr4 0 r/w 3 1 0 1 2 1 1 1 bit initial value r/w different triggers for pulse output groups: same trigger for pulse output groups: : : : address: h'fe2d address: h'fe2d address: h'fe2f address: h'fe2f 1114 subtitle amended tcnt0 timer counter 0 (up-counter) tcnt0 timer counter 1 (up/down-counter * ) tcnt0 timer counter 2 (up/down-counter * ) tcnt0 timer counter 3 (up-counter) tcnt0 timer counter 4 (up/down-counter * ) tcnt0 timer counter 5 (up/down-counter * )
rev. 3.00 jan 11, 2005 page xxxiii of liv item page revisions (see manual for details) b.2 functions 1155 tcsr1 timer control/status register 1 h'ffa2 (w), h'ffa2 (r) wdt1 4 pss 0 r/w prescaler select 0 tcnt counts the divided clock output by the * priority order: (mode 7) 8-bit timer output > dr output (modes 4 to 6) chip select output > 8-bit timer output > dr output figure c.6 (c) port 7 block diagram (pin p73) 1184 note amended note: * priority order: (mode 7) 8-bit timer output > dr output (modes 4 to 6) chip select output > 8-bit timer output > dr output c.9 port a block diagrams figure c.9 port a block diagram (pin s pa0 to pa7) 1194 figure c.9 amended pan ? port a block diagram (pin pa1) to port a block diagram (pins pa4 to pa7) deleted
rev. 3.00 jan 11, 2005 page xxxiv of liv item page revisions (see manual for details) 1217 table f.1 amended product type product code mark code package (package code) h8s/2643 f-ztat hd64f2643 hd64f2643fc 144-pin qfp (fp-144 j) hd64f2643tf 144-pin tqfp (tfp-144) masked rom HD6432643 HD6432643fc 144-pin qfp (fp-144 j) HD6432643tf 144-pin tqfp (tfp-144) h8s/2642 hd6432642 hd6432642fc 144-pin qfp (fp-144 j) hd6432642tf 144-pin tqfp (tfp-144) h8s/2641 hd6432641 hd6432641fc 144-pin qfp (fp-144 j) f. product code lineup table f.1 h8s/2643 group product code lineup hd6432641tf 144-pin tqfp (tfp-144) g. package dimensions ?
rev. 3.00 jan 11, 2005 page xxxv of liv contents section 1 overview ............................................................................................................. 1 1.1 overview.................................................................................................................... ....... 1 1.2 internal block diagram..................................................................................................... 6 1.3 pin description ............................................................................................................. .... 7 1.3.1 pin arrangement.................................................................................................. 7 1.3.2 pin functions in each operating mode ............................................................... 8 1.3.3 pin functions ....................................................................................................... 13 section 2 cpu ...................................................................................................................... 21 2.1 overview.................................................................................................................... ....... 21 2.1.1 features................................................................................................................ 21 2.1.2 differences between h8s/2600 cpu and h8s/2000 cpu .................................. 22 2.1.3 differences from h8/300 cpu ............................................................................ 23 2.1.4 differences from h8/300h cpu ......................................................................... 23 2.2 cpu operating modes...................................................................................................... 24 2.3 address space............................................................................................................... .... 29 2.4 register configuration...................................................................................................... 30 2.4.1 overview.............................................................................................................. 30 2.4.2 general registers................................................................................................. 31 2.4.3 control registers ................................................................................................. 32 2.4.4 initial register values ......................................................................................... 34 2.5 data formats................................................................................................................ ..... 35 2.5.1 general register data formats............................................................................ 35 2.5.2 memory data formats ......................................................................................... 37 2.6 instruction set............................................................................................................. ...... 38 2.6.1 overview.............................................................................................................. 38 2.6.2 instructions and addressing modes..................................................................... 39 2.6.3 table of instructions classified by function ....................................................... 41 2.6.4 basic instruction formats .................................................................................... 48 2.7 addressing modes and effective address calculation..................................................... 50 2.7.1 addressing mode................................................................................................. 50 2.7.2 effective address calculation ............................................................................. 53 2.8 processing states........................................................................................................... .... 57 2.8.1 overview.............................................................................................................. 57 2.8.2 reset state ........................................................................................................... 58 2.8.3 exception-handling state .................................................................................... 59 2.8.4 program execution state ..................................................................................... 62
rev. 3.00 jan 11, 2005 page xxxvi of liv 2.8.5 bus-released state............................................................................................... 62 2.8.6 power-down state ............................................................................................... 62 2.9 basic timing ..................................................................................................................... 63 2.9.1 overview.............................................................................................................. 63 2.9.2 on-chip memory (rom, ram) ......................................................................... 63 2.9.3 on-chip supporting module access t iming ....................................................... 65 2.9.4 external address space access t iming ............................................................... 66 2.10 usage note................................................................................................................. ....... 66 2.10.1 tas instruction.................................................................................................... 66 2.10.2 stm/ldm instruction ......................................................................................... 67 2.10.3 bit manipulation instructions............................................................................... 67 section 3 mcu operating modes ................................................................................... 69 3.1 overview.................................................................................................................... ....... 69 3.1.1 operating mode selection.................................................................................... 69 3.1.2 register configuration ......................................................................................... 70 3.2 register descriptions ....................................................................................................... .70 3.2.1 mode control register (mdcr).......................................................................... 70 3.2.2 system control register (syscr) ...................................................................... 71 3.2.3 pin function control register (pfcr) ................................................................ 73 3.3 operating mode descriptions ........................................................................................... 76 3.3.1 mode 4 ................................................................................................................. 76 3.3.2 mode 5 ................................................................................................................. 76 3.3.3 mode 6 ................................................................................................................. 76 3.3.4 mode 7 ................................................................................................................. 76 3.4 pin functions in each operating mode ............................................................................ 77 3.5 address map in each operating mode ............................................................................. 77 section 4 exception handling .......................................................................................... 81 4.1 overview.................................................................................................................... ....... 81 4.1.1 exception handling types and priority ............................................................... 81 4.1.2 exception handling operation............................................................................. 82 4.1.3 exception vector table........................................................................................ 82 4.2 reset ....................................................................................................................... .......... 84 4.2.1 overview.............................................................................................................. 84 4.2.2 types of reset...................................................................................................... 84 4.2.3 reset sequence .................................................................................................... 85 4.2.4 interrupts after reset ............................................................................................ 87 4.2.5 state of on-chip supporting modules after reset release ................................. 87 4.3 traces ...................................................................................................................... .......... 88 4.4 interrupts .................................................................................................................. ......... 89
rev. 3.00 jan 11, 2005 page xxxvii of liv 4.5 trap instruction............................................................................................................ ..... 90 4.6 stack status after exception handling.............................................................................. 91 4.7 notes on use of the stack................................................................................................. 92 section 5 interrupt controller .......................................................................................... 93 5.1 overview.................................................................................................................... ....... 93 5.1.1 features................................................................................................................ 93 5.1.2 block diagram..................................................................................................... 94 5.1.3 pin configuration................................................................................................. 95 5.1.4 register configuration......................................................................................... 95 5.2 register descriptions....................................................................................................... .96 5.2.1 system control register (syscr) ...................................................................... 96 5.2.2 interrupt priority registers a to l, o (ipra to iprl, ipro)............................. 97 5.2.3 irq enable register (ier) .................................................................................. 98 5.2.4 irq sense control registers h and l (iscrh, iscrl)..................................... 99 5.2.5 irq status register (isr).................................................................................... 100 5.3 interrupt sources........................................................................................................... .... 101 5.3.1 external interrupts ............................................................................................... 101 5.3.2 internal interrupts ................................................................................................ 102 5.3.3 interrupt exception handling vector table......................................................... 103 5.4 interrupt operation ......................................................................................................... .. 108 5.4.1 interrupt control modes and interrupt operation................................................ 108 5.4.2 interrupt control mode 0..................................................................................... 111 5.4.3 interrupt control mode 2..................................................................................... 113 5.4.4 interrupt exception handling sequence .............................................................. 115 5.4.5 interrupt response times .................................................................................... 116 5.5 usage notes ................................................................................................................. ..... 117 5.5.1 contention between interrupt generation and disabling..................................... 117 5.5.2 instructions that disable interrupts...................................................................... 118 5.5.3 times when interrupts are disabled .................................................................... 118 5.5.4 interrupts during execution of eepmov instruction ......................................... 119 5.5.5 irq interrupt ....................................................................................................... 119 5.5.6 nmi interrupt usage notes ................................................................................. 119 5.6 dtc and dmac activation by interrupt ......................................................................... 120 5.6.1 overview.............................................................................................................. 120 5.6.2 block diagram..................................................................................................... 120 5.6.3 operation ............................................................................................................. 121 section 6 pc break controller (pbc) ........................................................................... 123 6.1 overview.................................................................................................................... ....... 123 6.1.1 features................................................................................................................ 12 3
rev. 3.00 jan 11, 2005 page xxxv iii of liv 6.1.2 block diagram ..................................................................................................... 124 6.1.3 register configuration ......................................................................................... 125 6.2 register descriptions ....................................................................................................... . 125 6.2.1 break address register a (bara) ..................................................................... 125 6.2.2 break address register b (barb)...................................................................... 126 6.2.3 break control register a (bcra) ...................................................................... 126 6.2.4 break control register b (bcrb)....................................................................... 128 6.2.5 module stop control register c (mstpcrc).................................................... 128 6.3 operation................................................................................................................... ........ 128 6.3.1 pc break interrupt due to instruction fetch........................................................ 128 6.3.2 pc break interrupt due to data access............................................................... 129 6.3.3 notes on pc break interrupt handling ................................................................ 130 6.3.4 operation in transitions to power-down modes................................................. 130 6.3.5 pc break operation in continuous data transfer ............................................... 131 6.3.6 when instruction execution is delayed by one state ......................................... 131 6.3.7 additional notes .................................................................................................. 132 section 7 bus controller .................................................................................................... 133 7.1 overview.................................................................................................................... ....... 133 7.1.1 features ................................................................................................................ 13 3 7.1.2 block diagram ..................................................................................................... 135 7.1.3 pin configuration................................................................................................. 136 7.1.4 register configuration ......................................................................................... 137 7.2 register descriptions ....................................................................................................... . 138 7.2.1 bus width control register (abwcr) ............................................................... 138 7.2.2 access state control register (astcr).............................................................. 139 7.2.3 wait control registers h and l (wcrh, wcrl) .............................................. 140 7.2.4 bus control register h (bcrh).......................................................................... 144 7.2.5 bus control register l (bcrl)........................................................................... 146 7.2.6 pin function control register (pfcr) ................................................................ 148 7.2.7 memory control register (mcr) ........................................................................ 151 7.2.8 dram control register (dramcr) ................................................................. 153 7.2.9 refresh timer counter (rtcnt) ........................................................................ 155 7.2.10 refresh time constant register (rtcor).......................................................... 156 7.3 overview of bus control .................................................................................................. 157 7.3.1 area partitioning .................................................................................................. 157 7.3.2 bus specifications................................................................................................ 158 7.3.3 memory interfaces ............................................................................................... 159 7.3.4 interface specifications for each area................................................................. 160 7.3.5 chip select signals .............................................................................................. 161 7.4 basic bus interface ......................................................................................................... .. 162
rev. 3.00 jan 11, 2005 page xxxix of liv 7.4.1 overview.............................................................................................................. 162 7.4.2 data size and data alignment............................................................................. 162 7.4.3 valid strobes ....................................................................................................... 164 7.4.4 basic t iming ........................................................................................................ 165 7.4.5 wait control ........................................................................................................ 173 7.5 dram interface .............................................................................................................. . 175 7.5.1 overview.............................................................................................................. 175 7.5.2 setting up dram space..................................................................................... 175 7.5.3 address multiplexing .......................................................................................... 176 7.5.4 data bus .............................................................................................................. 176 7.5.5 dram interface pins .......................................................................................... 177 7.5.6 basic t iming ........................................................................................................ 177 7.5.7 precharge state control ....................................................................................... 179 7.5.8 wait control ........................................................................................................ 180 7.5.9 byte access control ............................................................................................ 184 7.5.10 burst operation.................................................................................................... 186 7.5.11 refresh control.................................................................................................... 190 7.6 dmac single address mode and dram interface ........................................................ 194 7.6.1 dds = 1 ............................................................................................................... 194 7.6.2 dds = 0 ............................................................................................................... 196 7.7 burst rom interface ........................................................................................................ 1 98 7.7.1 overview.............................................................................................................. 198 7.7.2 basic t iming ........................................................................................................ 198 7.7.3 wait control ........................................................................................................ 200 7.8 idle cycle.................................................................................................................. ........ 201 7.8.1 operation ............................................................................................................. 201 7.8.2 pin states in idle cycle........................................................................................ 205 7.9 write data buffer function .............................................................................................. 206 7.10 bus release................................................................................................................ ....... 207 7.10.1 overview.............................................................................................................. 207 7.10.2 operation ............................................................................................................. 207 7.10.3 pin states in external bus released state ........................................................... 208 7.10.4 transition t iming ................................................................................................ 209 7.10.5 notes.................................................................................................................... 210 7.11 bus arbitration ............................................................................................................ ..... 211 7.11.1 overview.............................................................................................................. 211 7.11.2 operation ............................................................................................................. 211 7.11.3 bus transfer t iming ............................................................................................ 212 7.12 resets and the bus controller........................................................................................... 213
rev. 3.00 jan 11, 2005 page xl of liv section 8 dma controller ................................................................................................ 215 8.1 overview.................................................................................................................... ....... 215 8.1.1 features ................................................................................................................ 21 5 8.1.2 block diagram ..................................................................................................... 216 8.1.3 overview of functions......................................................................................... 217 8.1.4 pin configuration................................................................................................. 219 8.1.5 register configuration ......................................................................................... 220 8.2 register descriptions (1) (short address mode) .............................................................. 221 8.2.1 memory address register (mar) ....................................................................... 222 8.2.2 i/o address register (ioar)............................................................................... 223 8.2.3 execute transfer count register (etcr)............................................................ 223 8.2.4 dma control register (dmacr)....................................................................... 224 8.2.5 dma band control register (dmabcr)........................................................... 229 8.3 register descriptions (2) (full address mode) ................................................................ 234 8.3.1 memory address register (mar) ....................................................................... 234 8.3.2 i/o address register (ioar)............................................................................... 235 8.3.3 execute transfer count register (etcr)............................................................ 235 8.3.4 dma control register (dmacr)....................................................................... 237 8.3.5 dma band control register (dmabcr)........................................................... 241 8.4 register descriptions (3)................................................................................................... 246 8.4.1 dma write enable register (dmawer) .......................................................... 246 8.4.2 dma terminal control register (dmatcr)..................................................... 249 8.4.3 module stop control register (mstpcr) .......................................................... 250 8.5 operation................................................................................................................... ........ 251 8.5.1 transfer modes .................................................................................................... 251 8.5.2 sequential mode .................................................................................................. 253 8.5.3 idle mode ............................................................................................................. 257 8.5.4 repeat mode ........................................................................................................ 260 8.5.5 single address mode ........................................................................................... 264 8.5.6 normal mode ....................................................................................................... 267 8.5.7 block transfer mode ........................................................................................... 270 8.5.8 dmac activation sources .................................................................................. 276 8.5.9 basic dmac bus cycles..................................................................................... 279 8.5.10 dmac bus cycles (dual address mode) ........................................................... 280 8.5.11 dmac bus cycles (single address mode)......................................................... 288 8.5.12 write data buffer function.................................................................................. 294 8.5.13 dmac multi-channel operation ........................................................................ 295 8.5.14 relation between external bus requests, refresh cycles, the dtc, and the dmac ..................................................................................................... 297 8.5.15 nmi interrupts and dmac.................................................................................. 298 8.5.16 forced termination of dmac operation............................................................ 299
rev. 3.00 jan 11, 2005 page xli of liv 8.5.17 clearing full address mode................................................................................ 300 8.6 interrupts.................................................................................................................. ......... 301 8.7 usage notes ................................................................................................................. ..... 302 section 9 data transfer controller (dtc) ................................................................... 307 9.1 overview.................................................................................................................... ....... 307 9.1.1 features................................................................................................................ 30 7 9.1.2 block diagram..................................................................................................... 308 9.1.3 register configuration......................................................................................... 309 9.2 register descriptions....................................................................................................... . 310 9.2.1 dtc mode register a (mra) ............................................................................ 310 9.2.2 dtc mode register b (mrb)............................................................................. 312 9.2.3 dtc source address register (sar).................................................................. 313 9.2.4 dtc destination address register (dar).......................................................... 313 9.2.5 dtc transfer count register a (cra) .............................................................. 313 9.2.6 dtc transfer count register b (crb)............................................................... 314 9.2.7 dtc enable register (dtcer) .......................................................................... 314 9.2.8 dtc vector register (dtvecr)........................................................................ 315 9.2.9 module stop control register a (mstpcra) ................................................... 316 9.3 operation ................................................................................................................... ....... 318 9.3.1 overview.............................................................................................................. 318 9.3.2 activation sources............................................................................................... 320 9.3.3 dtc vector table ............................................................................................... 321 9.3.4 location of register information in address space ............................................ 326 9.3.5 normal mode....................................................................................................... 327 9.3.6 repeat mode........................................................................................................ 328 9.3.7 block transfer mode ........................................................................................... 329 9.3.8 chain transfer ..................................................................................................... 331 9.3.9 operation t iming ................................................................................................. 332 9.3.10 number of dtc execution states ....................................................................... 333 9.3.11 procedures for using dtc .................................................................................. 334 9.3.12 examples of use of the dtc ............................................................................... 335 9.4 interrupts.................................................................................................................. ......... 338 9.5 usage notes ................................................................................................................. ..... 338 section 10 i/o ports ............................................................................................................ 339 10.1 overview................................................................................................................... ........ 339 10.2 port 1..................................................................................................................... ............ 345 10.2.1 overview.............................................................................................................. 345 10.2.2 register configuration......................................................................................... 346 10.2.3 pin functions ....................................................................................................... 348
rev. 3.00 jan 11, 2005 page x lii of liv 10.3 port 2 ..................................................................................................................... ............ 356 10.3.1 overview.............................................................................................................. 356 10.3.2 register configuration ......................................................................................... 356 10.3.3 pin functions........................................................................................................ 359 10.4 port 3 ..................................................................................................................... ............ 367 10.4.1 overview.............................................................................................................. 367 10.4.2 register configuration ......................................................................................... 367 10.4.3 pin functions........................................................................................................ 370 10.5 port 4 ..................................................................................................................... ............ 373 10.5.1 overview.............................................................................................................. 373 10.5.2 register configuration ......................................................................................... 374 10.5.3 pin functions........................................................................................................ 374 10.6 port 5 ..................................................................................................................... ............ 375 10.6.1 overview.............................................................................................................. 375 10.6.2 register configuration ......................................................................................... 375 10.6.3 pin functions........................................................................................................ 378 10.7 port 7 ..................................................................................................................... ............ 379 10.7.1 overview.............................................................................................................. 379 10.7.2 register configuration ......................................................................................... 380 10.7.3 pin functions........................................................................................................ 382 10.8 port 8 ..................................................................................................................... ............ 385 10.8.1 overview.............................................................................................................. 385 10.8.2 register configuration ......................................................................................... 385 10.8.3 pin functions........................................................................................................ 388 10.9 port 9 ..................................................................................................................... ............ 390 10.9.1 overview.............................................................................................................. 390 10.9.2 register configuration ......................................................................................... 391 10.9.3 pin functions........................................................................................................ 391 10.10 port a .................................................................................................................... ............ 392 10.10.1 overview.............................................................................................................. 39 2 10.10.2 register configuration ......................................................................................... 393 10.10.3 pin functions........................................................................................................ 396 10.10.4 mos input pull-up function............................................................................... 397 10.11 port b .................................................................................................................... ............ 398 10.11.1 overview.............................................................................................................. 39 8 10.11.2 register configuration ......................................................................................... 399 10.11.3 pin functions........................................................................................................ 402 10.11.4 mos input pull-up function............................................................................... 403 10.12 port c .................................................................................................................... ............ 404 10.12.1 overview.............................................................................................................. 40 4 10.12.2 register configuration ......................................................................................... 405
rev. 3.00 jan 11, 2005 page x liii of liv 10.12.3 pin functions for each mode .............................................................................. 408 10.12.4 mos input pull-up function............................................................................... 410 10.13 port d.................................................................................................................... ............ 411 10.13.1 overview.............................................................................................................. 41 1 10.13.2 register configuration......................................................................................... 412 10.13.3 pin functions ....................................................................................................... 414 10.13.4 mos input pull-up function............................................................................... 415 10.14 port e .................................................................................................................... ............ 417 10.14.1 overview.............................................................................................................. 41 7 10.14.2 register configuration......................................................................................... 418 10.14.3 pin functions ....................................................................................................... 420 10.14.4 mos input pull-up function............................................................................... 422 10.15 port f .................................................................................................................... ............ 423 10.15.1 overview.............................................................................................................. 42 3 10.15.2 register configuration......................................................................................... 424 10.15.3 pin functions ....................................................................................................... 426 10.16 port g.................................................................................................................... ............ 428 10.16.1 overview.............................................................................................................. 42 8 10.16.2 register configuration......................................................................................... 429 10.16.3 pin functions ....................................................................................................... 431 section 11 16-bit timer pulse unit (tpu) .................................................................. 433 11.1 overview................................................................................................................... ........ 433 11.1.1 features................................................................................................................ 4 33 11.1.2 block diagram..................................................................................................... 437 11.1.3 pin configuration................................................................................................. 438 11.1.4 register configuration......................................................................................... 440 11.2 register descriptions...................................................................................................... .. 442 11.2.1 timer control register (tcr)............................................................................. 442 11.2.2 timer mode register (tmdr)............................................................................ 447 11.2.3 timer i/o control register (tior)..................................................................... 449 11.2.4 timer interrupt enable register (tier).............................................................. 462 11.2.5 timer status register (tsr)................................................................................ 465 11.2.6 timer counter (tcnt)........................................................................................ 469 11.2.7 timer general register (tgr) ............................................................................ 470 11.2.8 timer start register (tstr) ............................................................................... 471 11.2.9 timer synchro register (tsyr) ......................................................................... 472 11.2.10 module stop control register a (mstpcra) ................................................... 473 11.3 interface to bus master.................................................................................................... . 474 11.3.1 16-bit registers ................................................................................................... 474 11.3.2 8-bit registers ..................................................................................................... 474
rev. 3.00 jan 11, 2005 page xliv of liv 11.4 operation.................................................................................................................. ......... 476 11.4.1 overview.............................................................................................................. 476 11.4.2 basic functions .................................................................................................... 478 11.4.3 synchronous operation........................................................................................ 484 11.4.4 buffer operation .................................................................................................. 487 11.4.5 cascaded operation ............................................................................................. 491 11.4.6 pwm modes ........................................................................................................ 493 11.4.7 phase counting mode .......................................................................................... 499 11.5 interrupts ................................................................................................................. .......... 506 11.5.1 interrupt sources and priorities............................................................................ 506 11.5.2 dtc/dmac activation....................................................................................... 508 11.5.3 a/d converter activation .................................................................................... 508 11.6 operation t iming .............................................................................................................. 509 11.6.1 input/output t iming ............................................................................................ 509 11.6.2 interrupt signal t iming ........................................................................................ 514 11.7 usage notes ................................................................................................................ ...... 519 section 12 programmable pulse generator (ppg) ..................................................... 529 12.1 overview................................................................................................................... ........ 529 12.1.1 features ................................................................................................................ 5 29 12.1.2 block diagram ..................................................................................................... 530 12.1.3 pin configuration................................................................................................. 531 12.1.4 registers............................................................................................................... 5 32 12.2 register descriptions ...................................................................................................... .. 533 12.2.1 next data enable registers h and l (nderh, nderl) ................................... 533 12.2.2 output data registers h and l (podrh, podrl) ............................................ 534 12.2.3 next data registers h and l (ndrh, ndrl) .................................................... 535 12.2.4 notes on ndr access.......................................................................................... 535 12.2.5 ppg output control register (pcr).................................................................... 537 12.2.6 ppg output mode register (pmr)...................................................................... 539 12.2.7 port 1 data direction register (p1ddr) ............................................................. 542 12.2.8 port 2 data direction register (p1ddr) ............................................................. 542 12.2.9 module stop control register a (mstpcra).................................................... 543 12.3 operation.................................................................................................................. ......... 544 12.3.1 overview.............................................................................................................. 544 12.3.2 output t iming ...................................................................................................... 545 12.3.3 normal pulse output............................................................................................ 546 12.3.4 non-overlapping pulse output............................................................................ 548 12.3.5 inverted pulse output........................................................................................... 551 12.3.6 pulse output triggered by input capture ............................................................ 552 12.4 usage notes ................................................................................................................ ...... 553
rev. 3.00 jan 11, 2005 page xlv of liv section 13 8-bit timers (tmr) ...................................................................................... 555 13.1 overview................................................................................................................... ........ 555 13.1.1 features................................................................................................................ 5 55 13.1.2 block diagram..................................................................................................... 556 13.1.3 pin configuration................................................................................................. 557 13.1.4 register configuration......................................................................................... 558 13.2 register descriptions...................................................................................................... .. 559 13.2.1 timer counters 0 to 3 (tcnt0 to tcnt3)......................................................... 559 13.2.2 time constant registers a0 to a3 (tcora0 to tcora3)............................... 559 13.2.3 time constant registers b0 to b3 (tcorb0 to tcorb3) ............................... 560 13.2.4 timer control registers 0 to 3 (tcr0 to tcr3) ................................................ 560 13.2.5 timer control/status registers 0 to 3 (tcsr0 to tcsr3) ................................. 563 13.2.6 module stop control register a (mstpcra) ................................................... 566 13.3 operation .................................................................................................................. ........ 567 13.3.1 tcnt incrementation t iming ............................................................................. 567 13.3.2 compare match t iming ....................................................................................... 568 13.3.3 t iming of external reset on tcnt ................................................................. 570 13.3.4 t iming of overflow flag (ovf) setting ............................................................. 570 13.3.5 operation with cascaded connection.................................................................. 571 13.4 interrupts................................................................................................................. .......... 572 13.4.1 interrupt sources and dtc activation ................................................................ 572 13.4.2 a/d converter activation.................................................................................... 573 13.5 sample application......................................................................................................... .. 573 13.6 usage notes ................................................................................................................ ...... 574 13.6.1 contention between tcnt write and clear........................................................ 574 13.6.2 contention between tcnt write and increment ................................................ 575 13.6.3 contention between tcor write and compare match ...................................... 576 13.6.4 contention between compare matches a and b ................................................. 577 13.6.5 switching of internal clocks and tcnt operation ........................................... 577 13.6.6 interrupts and module stop mode ....................................................................... 579 section 14 14-bit pwm d/a ........................................................................................... 581 14.1 overview................................................................................................................... ........ 581 14.1.1 features................................................................................................................ 5 81 14.1.2 block diagram..................................................................................................... 582 14.1.3 pin configuration................................................................................................. 583 14.1.4 register configuration......................................................................................... 583 14.2 register descriptions...................................................................................................... .. 584 14.2.1 pwm d/a counter (dacnt)............................................................................. 584 14.2.2 pwm d/a data registers a and b (dadra and dadrb) .............................. 585 14.2.3 pwm d/a control register (dacr).................................................................. 586
rev. 3.00 jan 11, 2005 page xlvi of liv 14.2.4 module stop control register b (mstpcrb).................................................... 588 14.3 bus master interface ....................................................................................................... .. 589 14.4 operation.................................................................................................................. ......... 592 section 15 watchdog timer ............................................................................................. 597 15.1 overview................................................................................................................... ........ 597 15.1.1 features ................................................................................................................ 5 97 15.1.2 block diagram ..................................................................................................... 598 15.1.3 pin configuration................................................................................................. 600 15.1.4 register configuration ......................................................................................... 600 15.2 register descriptions ...................................................................................................... .. 601 15.2.1 timer counter (tcnt) ........................................................................................ 601 15.2.2 timer control/status register (tcsr) ................................................................ 601 15.2.3 reset control/status register (rstcsr) ............................................................ 606 15.2.4 pin function control register (pfcr) ................................................................ 607 15.2.5 notes on register access..................................................................................... 608 15.3 operation.................................................................................................................. ......... 610 15.3.1 watchdog timer operation.................................................................................. 610 15.3.2 interval timer operation...................................................................................... 613 15.3.3 t iming of setting overflow flag (ovf) .............................................................. 613 15.3.4 t iming of setting of watc hdog timer overflow flag (wovf).......................... 614 15.4 interrupts ................................................................................................................. .......... 615 15.5 usage notes ............................................................................................................... ....... 615 15.5.1 contention between timer counter (tcnt) write and increment ..................... 615 15.5.2 changing value of pss and cks2 to cks0........................................................ 616 15.5.3 switching between watchdog timer mode and interval timer mode ................ 616 15.5.4 system reset by wdtovf signal ...................................................................... 616 15.5.5 internal reset in watchdog timer mode ............................................................. 616 15.5.6 ovf flag clearing in interval timer mode ........................................................ 617 section 16 serial communication interface (sci, irda) ........................................ 619 16.1 overview................................................................................................................... ........ 619 16.1.1 features ................................................................................................................ 6 19 16.1.2 block diagram ..................................................................................................... 621 16.1.3 pin configuration................................................................................................. 622 16.1.4 register configuration ......................................................................................... 623 16.2 register descriptions ...................................................................................................... .. 625 16.2.1 receive shift register (rsr)............................................................................... 625 16.2.2 receive data register (rdr) .............................................................................. 625 16.2.3 transmit shift register (tsr) ............................................................................. 626 16.2.4 transmit data register (tdr)............................................................................. 626
rev. 3.00 jan 11, 2005 page xlvii of liv 16.2.5 serial mode register (smr) ............................................................................... 627 16.2.6 serial control register (scr) ............................................................................. 630 16.2.7 serial status register (ssr) ................................................................................ 634 16.2.8 bit rate register (brr) ...................................................................................... 638 16.2.9 smart card mode register (scmr).................................................................... 647 16.2.10 irda control register (ircr).............................................................................. 648 16.2.11 module stop control registers b and c (mstpcrb, mstpcrc) ................... 650 16.3 operation .................................................................................................................. ........ 652 16.3.1 overview.............................................................................................................. 652 16.3.2 operation in asynchronous mode ....................................................................... 654 16.3.3 multiprocessor communication function ........................................................... 665 16.3.4 operation in clocked synchronous mode ........................................................... 673 16.3.5 irda operation.................................................................................................... 682 16.4 sci interrupts............................................................................................................. ....... 685 16.5 usage notes ................................................................................................................ ...... 687 section 17 smart card interface ..................................................................................... 697 17.1 overview................................................................................................................... ........ 697 17.1.1 features................................................................................................................ 6 97 17.1.2 block diagram..................................................................................................... 698 17.1.3 pin configuration................................................................................................. 699 17.1.4 register configuration......................................................................................... 700 17.2 register descriptions...................................................................................................... .. 702 17.2.1 smart card mode register (scmr).................................................................... 702 17.2.2 serial status register (ssr) ................................................................................ 704 17.2.3 serial mode register (smr) ............................................................................... 706 17.2.4 serial control register (scr) ............................................................................. 708 17.3 operation .................................................................................................................. ........ 709 17.3.1 overview.............................................................................................................. 709 17.3.2 pin connections ................................................................................................... 709 17.3.3 data format ......................................................................................................... 711 17.3.4 register settings .................................................................................................. 713 17.3.5 clock.................................................................................................................... 715 17.3.6 data transfer operations..................................................................................... 717 17.3.7 operation in gsm mode ..................................................................................... 724 17.3.8 operation in block transfer mode ...................................................................... 725 17.4 usage notes ................................................................................................................ ...... 727 section 18 i 2 c bus interface [option] .......................................................................... 731 18.1 overview................................................................................................................... ........ 731 18.1.1 features................................................................................................................ 7 31
rev. 3.00 jan 11, 2005 page xlv iii of liv 18.1.2 block diagram ..................................................................................................... 732 18.1.3 input/output pins ................................................................................................. 734 18.1.4 register configuration ......................................................................................... 734 18.2 register descriptions ...................................................................................................... .. 736 18.2.1 i 2 c bus data register (icdr) ............................................................................. 736 18.2.2 slave address register (sar) ............................................................................. 739 18.2.3 second slave address register (sarx).............................................................. 740 18.2.4 i 2 c bus mode register (icmr)........................................................................... 741 18.2.5 i 2 c bus control register (iccr)......................................................................... 744 18.2.6 i 2 c bus status register (icsr)............................................................................ 752 18.2.7 serial control register x (scrx) ....................................................................... 757 18.2.8 ddc switch register (ddcswr) ...................................................................... 758 18.2.9 module stop control register b (mstpcrb).................................................... 760 18.3 operation.................................................................................................................. ......... 761 18.3.1 i 2 c bus data format ............................................................................................ 761 18.3.2 master transmit operation .................................................................................. 762 18.3.3 master receive operation.................................................................................... 765 18.3.4 slave receive operation ...................................................................................... 767 18.3.5 slave transmit operation .................................................................................... 769 18.3.6 iric setting t iming and scl control ................................................................. 772 18.3.7 operation using the dtc .................................................................................... 773 18.3.8 noise canceler ..................................................................................................... 774 18.3.9 sample flowcharts ............................................................................................... 774 18.3.10 initialization of internal state............................................................................... 778 18.4 usage notes ................................................................................................................ ...... 780 section 19 a/d converter ................................................................................................. 793 19.1 overview................................................................................................................... ........ 793 19.1.1 features ................................................................................................................ 7 93 19.1.2 block diagram ..................................................................................................... 794 19.1.3 pin configuration................................................................................................. 795 19.1.4 register configuration ......................................................................................... 796 19.2 register descriptions ...................................................................................................... .. 797 19.2.1 a/d data registers a to d (addra to addrd).............................................. 797 19.2.2 a/d control/status register (adcsr)................................................................ 798 19.2.3 a/d control register (adcr)............................................................................. 801 19.2.4 module stop control register a (mstpcra).................................................... 802 19.3 interface to bus master .................................................................................................... . 803 19.4 operation.................................................................................................................. ......... 804 19.4.1 single mode (scan = 0)..................................................................................... 804 19.4.2 scan mode (scan = 1) ....................................................................................... 806
rev. 3.00 jan 11, 2005 page xlix of liv 19.4.3 input sampling and a/d conversion time ......................................................... 808 19.4.4 external trigger input t iming ............................................................................. 810 19.5 interrupts................................................................................................................. .......... 810 19.6 usage notes ................................................................................................................ ...... 811 section 20 d/a converter ................................................................................................. 817 20.1 overview................................................................................................................... ........ 817 20.1.1 features................................................................................................................ 8 17 20.1.2 block diagram..................................................................................................... 817 20.1.3 input and output pins .......................................................................................... 819 20.1.4 register configuration......................................................................................... 819 20.2 register descriptions...................................................................................................... .. 820 20.2.1 d/a data registers 0 to 3 (dadr0 to dadr3)................................................. 820 20.2.2 d/a control registers 01 and 23 (dacr01 and dacr23) ............................... 820 20.2.3 module stop control registers a and c (mstpcra and mstpcrc) ............. 822 20.3 operation .................................................................................................................. ........ 823 section 21 ram .................................................................................................................. 825 21.1 overview................................................................................................................... ........ 825 21.1.1 block diagram..................................................................................................... 825 21.1.2 register configuration......................................................................................... 826 21.2 register descriptions...................................................................................................... .. 826 21.2.1 system control register (syscr) ...................................................................... 826 21.3 operation .................................................................................................................. ........ 827 21.4 usage notes ................................................................................................................ ...... 827 section 22 rom .................................................................................................................. 829 22.1 overview................................................................................................................... ........ 829 22.1.1 block diagram..................................................................................................... 829 22.1.2 register configuration......................................................................................... 829 22.2 register descriptions...................................................................................................... .. 830 22.2.1 mode control register (mdcr) ......................................................................... 830 22.3 operation .................................................................................................................. ........ 830 22.4 flash memory overview .................................................................................................. 833 22.4.1 features................................................................................................................ 8 33 22.4.2 overview.............................................................................................................. 834 22.4.3 flash memory operating modes ......................................................................... 835 22.4.4 on-board progra mming modes ........................................................................... 836 22.4.5 flash memory emulation in ram ...................................................................... 838 22.4.6 differences between boot mode and user program mode ................................. 839 22.4.7 block configuration ............................................................................................ 840
rev. 3.00 jan 11, 2005 page l of liv 22.4.8 pin configuration................................................................................................. 841 22.4.9 register configuration ......................................................................................... 842 22.5 register descriptions ...................................................................................................... .. 842 22.5.1 flash memory control register 1 (flmcr1)..................................................... 842 22.5.2 flash memory control register 2 (flmcr2)..................................................... 846 22.5.3 erase block register 1 (ebr1)............................................................................ 847 22.5.4 erase block register 2 (ebr2)............................................................................ 847 22.5.5 ram emulation register (ramer) ................................................................... 848 22.5.6 flash memory power control register (flpwcr) ............................................ 850 22.5.7 serial control register x (scrx) ....................................................................... 850 22.6 on-board progra mming modes ........................................................................................ 851 22.6.1 boot mode ........................................................................................................... 852 22.6.2 user program mode ............................................................................................. 856 22.7 progra mming/erasing flash memory ............................................................................... 858 22.7.1 program mode...................................................................................................... 859 22.7.2 program-verify mode.......................................................................................... 860 22.7.3 erase mode .......................................................................................................... 864 22.7.4 erase-verify mode............................................................................................... 864 22.8 protection ................................................................................................................. ......... 866 22.8.1 hardware protection............................................................................................. 866 22.8.2 software protection.............................................................................................. 867 22.8.3 error protection.................................................................................................... 868 22.9 flash memory emulation in ram.................................................................................... 870 22.10 interrupt handling when progra mming/erasing flash memory ....................................... 872 22.11 flash memory programmer mode .................................................................................... 872 22.11.1 socket adapter and memory map ....................................................................... 873 22.11.2 programmer mode operation............................................................................... 874 22.11.3 memory read mode ............................................................................................ 875 22.11.4 auto-program mode ............................................................................................ 878 22.11.5 auto-erase mode ................................................................................................. 880 22.11.6 status read mode ................................................................................................ 882 22.11.7 status po lling ....................................................................................................... 883 22.11.8 programmer mode transition time..................................................................... 883 22.11.9 notes on memory progra mming .......................................................................... 884 22.12 flash memory and power-down states ............................................................................ 885 22.12.1 note on power-down states ................................................................................ 885 22.13 flash memory progra mming and erasing precautions ..................................................... 886 22.14 note on switching from f-ztat version to masked rom version............................... 891 section 23 clock pulse generator .................................................................................. 893 23.1 overview................................................................................................................... ........ 893
rev. 3.00 jan 11, 2005 page li of liv 23.1.1 block diagram..................................................................................................... 893 23.1.2 register configuration......................................................................................... 894 23.2 register descriptions...................................................................................................... .. 894 23.2.1 system clock control register (sckcr) ........................................................... 894 23.2.2 low-power control register (lpwrcr) ........................................................... 895 23.3 osc illator ........................................................................................................................... 896 23.3.1 connecting a crystal resonator........................................................................... 896 23.3.2 external clock input............................................................................................ 899 23.4 pll circuit ................................................................................................................ ....... 901 23.5 medium-speed clock divider .......................................................................................... 902 23.6 bus master clock selection circuit.................................................................................. 902 23.7 subclock osc illator ........................................................................................................... 902 23.8 subclock waveform shaping circuit................................................................................ 903 23.9 note on crystal resonator ................................................................................................ 90 4 section 24 power-down modes ...................................................................................... 905 24.1 overview................................................................................................................... ........ 905 24.1.1 register configuration......................................................................................... 909 24.2 register descriptions...................................................................................................... .. 910 24.2.1 standby control register (sbycr) .................................................................... 910 24.2.2 system clock control register (sckcr) ........................................................... 912 24.2.3 low-power control register (lpwrcr) ........................................................... 913 24.2.4 timer control/status register (tcsr)................................................................ 916 24.2.5 module stop control register (mstpcr).......................................................... 917 24.3 medium-speed mode ....................................................................................................... 918 24.4 sleep mode ................................................................................................................. ...... 919 24.4.1 sleep mode .......................................................................................................... 919 24.4.2 exiting sleep mode ............................................................................................. 919 24.5 module stop mode ........................................................................................................... 920 24.5.1 module stop mode .............................................................................................. 920 24.5.2 usage notes ......................................................................................................... 922 24.6 software standby mode.................................................................................................... 92 2 24.6.1 software standby mode....................................................................................... 922 24.6.2 exiting software standby mode.......................................................................... 922 24.6.3 setting osc illation stabilization time after clearing software standby mode... 923 24.6.4 software standby mode application example.................................................... 924 24.6.5 usage notes ......................................................................................................... 926 24.7 hardware standby mode .................................................................................................. 926 24.7.1 hardware standby mode ..................................................................................... 926 24.7.2 hardware standby mode t iming ......................................................................... 927 24.8 watch mode................................................................................................................. ..... 927
rev. 3.00 jan 11, 2005 page lii of liv 24.8.1 watch mode......................................................................................................... 927 24.8.2 exiting watch mode ............................................................................................ 928 24.8.3 notes .................................................................................................................... 928 24.9 sub-sleep mode ............................................................................................................. ... 929 24.9.1 sub-sleep mode................................................................................................... 929 24.9.2 exiting sub-sleep mode ...................................................................................... 929 24.10 sub-active mode ........................................................................................................... ... 930 24.10.1 sub-active mode ................................................................................................. 930 24.10.2 exiting sub-active mode .................................................................................... 930 24.11 direct transitions........................................................................................................ ...... 931 24.11.1 overview of direct transitions............................................................................ 931 24.12 clock output disabling function................................................................................... 931 section 25 electrical characteristics .............................................................................. 933 25.1 absolute maximum ratings.............................................................................................. 933 25.2 dc characteristics ......................................................................................................... ... 934 25.3 ac characteristics ......................................................................................................... ... 942 25.3.1 clock t iming ....................................................................................................... 943 25.3.2 control signal t iming .......................................................................................... 945 25.3.3 bus t iming ........................................................................................................... 947 25.3.4 dmac t iming ..................................................................................................... 957 25.3.5 t iming of on-chip s upporting modules ............................................................. 961 25.4 a/d conversion characteristics........................................................................................ 969 25.5 d/a conversion characteristics........................................................................................ 970 25.6 flash memory characteristics........................................................................................... 971 25.7 usage note................................................................................................................. ....... 972 appendix a instruction set .............................................................................................. 973 a.1 instruction list ............................................................................................................ ...... 973 a.2 instruction codes ........................................................................................................... ... 997 a.3 operation code map ........................................................................................................10 12 a.4 number of states required for instruction execution .....................................................1016 a.5 bus states during instruction execution ..........................................................................1030 a.6 condition code modification...........................................................................................1044 appendix b internal i/o register ..................................................................................1050 b.1 addresses ................................................................................................................... ......1050 b.2 functions................................................................................................................... .......1061 appendix c i/o port block diagrams ..........................................................................1163 c.1 port 1 block diagrams .....................................................................................................11 63
rev. 3.00 jan 11, 2005 page liii of liv c.2 port 2 block diagram ...................................................................................................... 11 69 c.3 port 3 block diagrams..................................................................................................... 11 70 c.4 port 4 block diagrams..................................................................................................... 11 78 c.5 port 5 block diagrams..................................................................................................... 11 79 c.6 port 7 block diagrams..................................................................................................... 11 82 c.7 port 8 block diagrams..................................................................................................... 11 89 c.8 port 9 block diagrams..................................................................................................... 11 93 c.9 port a block diagrams.................................................................................................... 119 4 c.10 port b block diagram...................................................................................................... 1 195 c.11 port c block diagrams .................................................................................................... 11 96 c.12 port d block diagram ..................................................................................................... 11 98 c.13 port e block diagram...................................................................................................... 1 199 c.14 port f block diagrams..................................................................................................... 1 200 c.15 port g block diagrams.................................................................................................... 12 08 appendix d pin states ...................................................................................................... 1212 d.1 port states in each mode................................................................................................. 121 2 appendix e timing of transition to and recovery from hardware standby mode ............................................................... 1216 appendix f product code lineup ................................................................................. 1217 appendix g package dimensions ................................................................................. 1218
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section 1 overview rev. 3.00 jan 11, 2005 page 1 of 1220 rej09b0186-0300o section 1 overview 1.1 overview the h8s/2643 group is a group of microcomputers (mcus: microcomputer units), built around the h8s/2600 cpu, employing renesas' proprietary architecture, and equipped with peripheral functions on-chip. the h8s/2600 cpu has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-mbyte linear address space. the instruction set is upward-compatible with h8/300 and h8/300h cpu instructions at the object-code level, fac ilitating migration from the h8/ 300, h8/300l, or h8/300h series. on-chip peripheral functions required for system configuration include dma controller (dmac), data transfer controller (dtc) bus masters, rom and ram memory, a 16-bit timer-pulse unit (tpu), programmable pulse generator (ppg), 8-bit timer, 14-bit pwm timer (pwm) watchdog timer (wdt), serial communication interface (sci, irda), a/d converter, d/a converter, and i/o ports. it is also possible to incorporate an on-chip pc bus interface (iic) as an option. on-chip rom is available as 256-kbyte flash memory (f-ztat? version) * or as 256-, 128-, or 64-kbyte mask rom. rom is connected to the cpu via a 16-bit data bus, enabling both byte and word data to be accessed in one state. instruction fetching has been speeded up, and processing speed increased. four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or external expansion mode. the features of the h8s/2643 group are shown in table 1.1. note: * f-ztat is a trademark of renesas technology, corp.
section 1 overview rev. 3.00 jan 11, 2005 page 2 of 1220 rej09b0186-0300o table 1.1 overview item specification cpu ? general-register machine ? sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) ? high-speed operation suitable for realtime control ? maximum clock rate: 25 mhz ? high-speed arithmetic operations 8/16/32-bit register-register add/subtract : 40 ns 16 16-bit register-register multiply : 160 ns 16 16 + 42-bit multiply and accumulate : 160 ns 32 16-bit register-register divide : 800 ns ? instruction set suitable for high-speed operation ? sixty-nine basic instructions ? 8/16/32-bit move/arithmetic and logic instructions ? unsigned/signed multiply and divide instructions ? multiply-and accumulate instruction ? powerful bit-manipulation instructions ? two cpu operating modes ? normal mode: 64-kbyte address space (cannot be used in the h8s/2643 group) ? advanced mode: 16-mbyte address space bus controller ? address space divided into 8 areas, with bus specifications settable independently for each area ? choice of 8-bit or 16-bit access space for each area ? 2-state or 3-state access space can be designated for each area ? number of program wait states can be set for each area ? burst rom directly connectable ? possible to connect a maximum of 8 mb of dram (alternatively, it is also possible to use an interval timer) ? external bus release function pc break controller ? supports debugging functions by means of pc break interrupts ? two break channels
section 1 overview rev. 3.00 jan 11, 2005 page 3 of 1220 rej09b0186-0300o item specification dma controller (dmac) ? short address mode and full address mode selectable ? short address mode: 4 channels full address mode: 2 channels ? transfer possible in repeat mode/block transfer mode transfer possible in single address mode ? activation by internal interrupt possible data transfer controller (dtc) ? can be activated by internal interrupt or software ? multiple transfers or multiple types of transfer possible for one activation source ? transfer possible in repeat mode, block transfer mode, etc. ? request can be sent to cpu for interrupt that activated dtc 16-bit timer-pulse unit (tpu) ? 6-channel 16-bit timer on-chip ? pulse i/o processing capability for up to 16 pins' ? automatic 2-phase encoder count capability programmable pulse generator (ppg) ? maximum 16-bit pulse output possible with tpu as time base ? output trigger selectable in 4-bit groups ? non-overlap margin can be set ? direct output or inverse output setting possible 8-bit timer 4 channels ? 8-bit up counter (external event count possible) ? time constant register 2 ? 2 channel connection possible watchdog timer (wdt) 2 channels ? watchdog timer or interval timer selectable ? operation using sub-clock supported (wdt1 only) 14-bit pwm timer (pwm) ? maximum of 4 outputs ? resolution: 1/16384 ? maximum carrier frequency: 390.6 khz (operating at 25 mhz) serial communication interface (sci) 5 channels (sci0 to sci4) ? asynchronous mode or synchronous mode selectable ? multiprocessor communication function ? smart card interface function
section 1 overview rev. 3.00 jan 11, 2005 page 4 of 1220 rej09b0186-0300o item specification irda-equipped sci 1 channel (sci0) ? supports irda standard version 1.0 ? txd and rxd encoding/decoding in irda format ? start/stop synchronization mode or clock synchronization mode selectable ? multiprocessor communications function ? smart card interface function a/d converter ? resolution: 10 bits ? input: 16 channels ? high-speed conversion: 10.72 s minimum conversion time (at 25 mhz operation) ? single or scan mode selectable ? sample and hold circuit ? a/d conversion can be activated by external trigger or timer trigger d/a converter ? resolution: 8 bits ? output: 4 channels i/o ports ? 95 i/o pins, 16 input-only pins memory ? flash memory or masked rom ? high-speed static ram product name rom ram h8s/2643 256 kbytes 16 kbytes h8s/2642 192 kbytes 12 kbytes h8s/2641 128 kbytes 8 kbytes interrupt controller ? nine external interrupt pins (nmi, irq0 to irq7 ) ? 72 internal interrupt sources (including options) ? eight priority levels settable power-down state ? medium-speed mode ? sleep mode ? module stop mode ? software standby mode ? hardware standby mode ? sub-clock operation (sub-active mode, sub-sleep mode, watch mode)
section 1 overview rev. 3.00 jan 11, 2005 page 5 of 1220 rej09b0186-0300o item specification operating modes four mcu operating modes cpu external data bus mode operating mode description on-chip rom initial value maximu m value 4 advanced on-chip rom disabled expansion mode disabled 16 bits 16 bits 5 on-chip rom disabled expansion mode disabled 8 bits 16 bits 6 on-chip rom enabled expansion mode enabled 8 bits 16 bits 7 single-chip mode enabled ? ? clock pulse generator ? on-chip pll circuit ( 1, 2, 4) ? input clock frequency: 2 to 25 mhz package ? 144-pin plastic qfp (fp-144j) ? 144-pin plastic tqfp (tfp-144) i 2 c bus interface (iic) 2 channels (optional) ? conforms to i 2 c bus interface type advocated by philips ? single master mode/slave mode ? possible to determine arbitration lost conditions ? supports two slave addresses product lineup model name masked rom version f-ztat version rom/ram (bytes) packages HD6432643 hd64f2643 256 k/16 k fp-144j tfp-144 hd6432642 ? 192 k/12 k fp-144j tfp-144 hd6432641 ? 128 k/8 k fp-144j tfp-144
section 1 overview rev. 3.00 jan 11, 2005 page 6 of 1220 rej09b0186-0300o 1.2 internal block diagram figure 1.1 shows an internal block diagram. pe7/d7 pe6/d6 pe5 /d5 pe4 /d4 pe3 /d3 pe2 /d2 pe1 /d1 pe0 /d0 internal data bus peripheral data bus peripheral address bus pd7 / d15 pd6 / d14 pd5 / d13 pd4 / d12 pd3 / d11 pd2 / d10 pd1/d9 pd0/d8 port d pvcc pvcc pvcc pvcc vcc vcc vss vss vss vss vss vss vss pa7 / a23 pa6 / a22 pa5 / a21 pa4 / a20 pa3 / a19 pa2 / a18 pa1 / a17 pa0 / a16 pb7 / a15 pb6 / a14 pb5 / a13 pb4 / a12 pb3 / a11 pb2 / a10 pb1 / a9 pb0 / a8 pc7 / a7/ pwm1 pc6 / a6/ pwm0 pc5 / a5 pc4 / a4 pc3 / a3 pc2 / a2 pc1 / a1 pc0 / a0 p37 / txd4 p36 / rxd4 p35 / sck1/sck4/scl0/ irq 5 p34 / rxd1/sda0 p33 / txd1/scl1 p32 / sck0/sda1/ irq4 p31 / rxd0/irrxd p30 / txd0/irtxd p97 / an15/da3 p96 / an14/da2 p95 / an13 p94 / an12 p93 / an11 p92 / an10 p91 / an9 p90 / an8 p47 / an7/da1 p46 / an6/da0 p45 /an5 p44 /an4 p43 /an3 p42 /an2 p41 /an1 p40 /an0 vref avcc avss p17 / po8/ tioca0 p16 / po9/ tiocb0 p15 / po10/ tiocc0 /tclka p14 / po11/ tiocd0 /tclkb p13 / po12/ tioca1/ irq0 p12 / po13/ tiocb1 / tclkc p11 / po14/ tioca2/pwm2/ irq1 p10 / po15/ tiocb2 /pwm3/ tclkd p77/txd3 p76/rxd3 p75 / tmo3/sck3 p74 / tmo2/ mres p73 / tmo1/ cs7 p72 / tmo0/ cs6 p71 / tmri23/tmci23/ cs5 p70 / tmri01/tmci01/ cs4 pg4 / cs0 pg3 / cs1 pg2 / cs2 pg1 / cs3 / oe / irq7 pg0 / cas / irq6 pf7 / ? pf6 / as / lcas pf5 / rd pf4 / hwr pf3 / lwr / adtrg / irq3 pf2 / lcas / wait / breqo pf1 / back /buzz pf0 / breq / irq2 rom (masked rom, flash memory * 1 ) ram wdt 2 channels tpu sci 5 channels d/a converter 8 bit timer 4 channels 14-bit pwm timer a/d converter ppg md2 md1 md0 osc2 osc1 extal xtal pllvcc pllcap pllvss stby res wdtovf nmi test1 fwe* 2 h8s/2600 cpu dtc interrupt controller pc break controller port e port 4 port 1 p27 / po0/ tioca3 p26 / po1/ tiocb3 p25 / po2/ tiocc3 p24 / po3/ tiocd3 p23 / po4/ tioca4 p22 / po5/ tiocb4 p21 / po6/ tioca5 p20 / po7/ tiocb5 port 2 dmac internal address bus p52/ sck2 p51/ rxd2 p50/ txd2 port 5 port a port b port c port 3 p86 p85 / dack1 p84 / dack0 p83 / tend1 p82 / tend0 p81 / dreq1 p80 / dreq0 port f port g port 8 port 7 clock pulse generator bus controller i 2 c bus interface [option] (irda 1 channel) p l l port 9 notes: 1. 2. applies to the h8s/2643 only. the fwe pin is used only in the flash memory version. figure 1.1 internal block diagram
section 1 overview rev. 3.00 jan 11, 2005 page 7 of 1220 rej09b0186-0300o 1.3 pin description 1.3.1 pin arrangement figure 1.2 shows the pin arrangement of the h8s/2643 group. a0/pc0 a1/pc1 a2/pc2 a3/pc3 vss a4/pc4 vcc a5/pc5 pwm0/a6/pc6 pwm1/a7/pc7 tioca3/po0/p20 tiocb3/po1/p21 tiocc3/po2/p22 vss a8/pb0 pvcc a9/pb1 a10/pb2 a11/pb3 a12/pb4 a13/pb5 a14/pb6 a15/pb7 tiocd3/po3/p23 tioca4/po4/p24 tiocb4/po5/p25 a16/pa0 a17/pa1 a18/pa2 a19/pa3 vss tioca0/po8/p10 tiocb0/po9/p11 tclka/tiocc0/po10/p12 tclkb/tiocd0/po11/p13 irq0 /tioca1/po12/p14 pf0/ breq / irq2 pf1/ back /buzz pf2/ lcas / wait / breq o pf3/ lwr / adtrg / irq3 pf4/ hwr pf5/ rd pf6/ as / lcas p86 p85/ dack1 p84/ dack0 vss pf7/ ? pvcc osc2 osc1 vss extal vcc xtal fwe * stby nmi res pllvss pllcap pllvcc wdtovf p83/ tend1 p82/ tend0 p81/ dreq1 pg4/ cs0 pg3/ cs1 pg2/ cs2 pg1/ cs3 / oe / irq7 pg0/ cas / irq6 p37/txd4 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 avcc vref an0/p40 an1/p41 an2/p42 an3/p43 an4/p44 an5/p45 da0/an6/p46 da1/an7/p47 an8/p90 an9/p91 an10/p92 an11/p93 an12/p94 an13/p95 da2/an14/p96 da3/an15/p97 avss test1 a20/pa4 a21/pa5 a22/pa6 a23/pa7 cs4 /tmci01/tmri01/p70 cs5 /tmci23/tmri23/p71 cs6 /tmo0/p72 cs7 /tmo1/p73 mres /tmo2/p74 sck3/tmo3/p75 rxd3/p76 txd3/p77 md0 md1 md2 nc 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 p36/rxd4 p35/sck1/sck4/scl0/ irq5 p34/rxd1/sda0 p33/txd1/scl1 vss p32/sck0/sda1/ irq4 pvcc p31/rxd0/irrxd p30/txd0/irtxd p80/ dreq0 p52/sck2 p51/rxd2 pd7/d15 pd6/d14 pd5/d13 pd4/d12 pd3/d11 pd2/d10 pd1/d9 pvcc pd0/d8 vss pe7/d7 pe6/d6 pe5/d5 pe4/d4 p50/txd2 p27/po7/tiocb5 p26/po6/tioca5 pe3/d3 pe2/d2 pe1/d1 pe0/d0 p17/po15/tiocb2/tclkd/pwm3 p16/po14/tioca2/pwm2/ irq1 p15/po13/tiocb1/tclkc 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 top view (fp-144j) (tfp-144) note: * fwe is used only in the flash memory version. figure 1.2 pin arrangement (fp-144j, tfp-144: top view)
section 1 overview rev. 3.00 jan 11, 2005 page 8 of 1220 rej09b0186-0300o 1.3.2 pin functions in each operating mode table 1.2 shows the pin functions of the h8s/2643 group in each of the operating modes. table 1.2 pin functions in each operating mode pin name pin no. mode 4 mode 5 mode 6 mode 7 1a0a0pc0/a0pc0 2a1a1pc1/a1pc1 3a2a2pc2/a2pc2 4a3a3pc3/a3pc3 5 vss vss vss vss 6a4a4pc4/a4pc4 7 vcc vcc vcc vcc 8a5a5pc5/a5pc5 9a6a6pc6/a6/pwm0pc6/pwm0 10 a7 a7 pc7/a7/pwm1 pc7/pwm1 11 p20/po0/tioca3 p20/po0/tioca3 p20/po0/tioca3 p20/po0/tioca3 12 p21/po1/tiocb3 p21/po1/tiocb3 p21/po1/tiocb3 p21/po1/tiocb3 13 p22/po2/tiocc3 p22/po2/tiocc3 p22/po2/tiocc3 p22/po2/tiocc3 14 vss vss vss vss 15 pb0/a8 pb0/a8 pb0/a8 pb0 16 pvcc pvcc pvcc pvcc 17 pb1/a9 pb1/a9 pb1/a9 pb1 18 pb2/a10 pb2/a10 pb2/a10 pb2 19 pb3/a11 pb3/a11 pb3/a11 pb3 20 pb4/a12 pb4/a12 pb4/a12 pb4 21 pb5/a13 pb5/a13 pb5/a13 pb5 22 pb6/a14 pb6/a14 pb6/a14 pb6 23 pb7/a15 pb7/a15 pb7/a15 pb7 24 p23/po3/tiocd3 p23/po3/tiocd3 p23/po3/tiocd3 p23/po3/tiocd3 25 p24/po4/tioca4 p24/po4/tioca4 p24/po4/tioca4 p24/po4/tioca4 26 p25/po5/tiocb4 p25/po5/tiocb4 p25/po5/tiocb4 p25/po5/tiocb4 27 pa0/a16 pa0/a16 pa0/a16 pa0
section 1 overview rev. 3.00 jan 11, 2005 page 9 of 1220 rej09b0186-0300o pin name pin no. mode 4 mode 5 mode 6 mode 7 28 pa1/a17 pa1/a17 pa1/a17 pa1 29 pa2/a18 pa2/a18 pa2/a18 pa2 30 pa3/a19 pa3/a19 pa3/a19 pa3 31 vss vss vss vss 32 p10/po8/tioca0 p10/po8/tioca0 p10/po8/tioca0 p10/po8/tioca0 33 p11/po9/tiocb0 p11/po9/tiocb0 p11/po9/tiocb0 p11/po9/tiocb0 34 p12/po10/tiocc0/ tclka p12/po10/tiocc0/ tclka p12/po10/tiocc0/ tclka p12/po10/tiocc0/ tclka 35 p13/po11/tiocd0/ tclkb p13/po11/tiocd0/ tclkb p13/po11/tiocd0/ tclkb p13/po11/tiocd0/ tclkb 36 p14/po12/tioca1/ irq0 p14/po12/tioca1/ irq0 p14/po12/tioca1/ irq0 p14/po12/tioca1/ irq0 37 p15/po13/tiocb1/ tclkc p15/po13/tiocb1/ tclkc p15/po13/tiocb1/ tclkc p15/po13/tiocb1/ tclkc 38 p16/po14/tioca2/ pwm2/ irq1 p16/po14/tioca2/ pwm2/ irq1 p16/po14/tioca2/ pwm2/ irq1 p16/po14/tioca2/ pwm2/ irq1 39 p17/po15/tiocb2/ tclkd/pwm3 p17/po15/tiocb2/ tclkd/pwm3 p17/po15/tiocb2/ tclkd/pwm3 p17/po15/tiocb2/ tclkd/pwm3 40 pe0/d0 pe0/d0 pe0/d0 pe0 41 pe1/d1 pe1/d1 pe1/d1 pe1 42 pe2/d2 pe2/d2 pe2/d2 pe2 43 pe3/d3 pe3/d3 pe3/d3 pe3 44 p26/po6/tioca5 p26/po6/tioca5 p26/po6/tioca5 p26/po6/tioca5 45 p27/po7/tiocb5 p27/po7/tiocb5 p27/po7/tiocb5 p27/po7/tiocb5 46 p50/txd2 p50/txd2 p50/txd2 p50/txd2 47 pe4/d4 pe4/d4 pe4/d4 pe4 48 pe5/d5 pe5/d5 pe5/d5 pe5 49 pe6/d6 pe6/d6 pe6/d6 pe6 50 pe7/d7 pe7/d7 pe7/d7 pe7 51 vss vss vss vss 52 d8 d8 d8 pd0 53 pvcc pvcc pvcc pvcc 54 d9 d9 d9 pd1 55 d10 d10 d10 pd2
section 1 overview rev. 3.00 jan 11, 2005 page 10 of 1220 rej09b0186-0300o pin name pin no. mode 4 mode 5 mode 6 mode 7 56 d11 d11 d11 pd3 57 d12 d12 d12 pd4 58 d13 d13 d13 pd5 59 d14 d14 d14 pd6 60 d15 d15 d15 pd7 61 p51/rxd2 p51/rxd2 p51/rxd2 p51/rxd2 62 p52/sck2 p52/sck2 p52/sck2 p52/sck2 63 p80/ dreq0 p80/ dreq0 p80/ dreq0 p80/ dreq0 64 p30/txd0/irtxd p30/txd0/irtxd p30/txd0/irtxd p30/txd0/irtxd 65 p31/rxd0/irrxd p31/rxd0/irrxd p31/rxd0/irrxd p31/rxd0/irrxd 66 pvcc pvcc pvcc pvcc 67 p32/sck0/sda1/ irq4 p32/sck0/sda1/ irq4 p32/sck0/sda1/ irq4 p32/sck0/sda1/ irq4 68 vss vss vss vss 69 p33/txd1/scl1 p33/txd1/scl1 p33/txd1/scl1 p33/txd1/scl1 70 p34/rxd1/sda0 p34/rxd1/sda0 p34/rxd1/sda0 p34/rxd1/sda0 71 p35/sck1/sck4/ scl0/ irq5 p35/sck1/sck4/ scl0/ irq5 p35/sck1/sck4/ scl0/ irq5 p35/sck1/sck4/ scl0/ irq5 72 p36/rxd4 p36/rxd4 p36/rxd4 p36/rxd4 73 p37/txd4 p37/txd4 p37/txd4 p37/txd4 74 pg0/ cas / irq6 pg0/ cas / irq6 pg0/ cas / irq6 pg0/ irq6 75 pg1/ cs3 / oe / irq7 pg1/ cs3 / oe / irq7 pg1/ cs3 / oe / irq7 pg1/ irq7 76 pg2/ cs2 pg2/ cs2 pg2/ cs2 pg2 77 pg3/ cs1 pg3/ cs1 pg3/ cs1 pg3 78 pg4/ cs0 pg4/ cs0 pg4/ cs0 pg4 79 p81/ dreq1 p81/ dreq1 p81/ dreq1 p81/ dreq1 80 p82/ tend0 p82/ tend0 p82/ tend0 p82/ tend0 81 p83/ tend1 p83/ tend1 p83/ tend1 p83/ tend1 82 wdtovf wdtovf wdtovf wdtovf 83 pllvcc pllvcc pllvcc pllvcc 84 pllcap pllcap pllcap pllcap 85 pllvss pllvss pllvss pllvss
section 1 overview rev. 3.00 jan 11, 2005 page 11 of 1220 rej09b0186-0300o pin name pin no. mode 4 mode 5 mode 6 mode 7 86 res res res res 87 nmi nmi nmi nmi 88 stby stby stby stby 89 few * 2 fwe * 2 fwe * 2 fwe * 2 90 xtal xtal xtal xtal 91 vcc vcc vcc vcc 92 extal extal extal extal 93 vss vss vss vss 94 osc1 osc1 osc1 osc1 95 osc2 osc2 osc2 osc2 96 pvcc pvcc pvcc pvcc 97 pf7/ pf7/ pf7/ pf7/ 98 vss vss vss vss 99 p84/ dack0 p84/ dack0 p84/ dack0 p84/ dack0 100 p85/ dack1 p85/ dack1 p85/ dack1 p85/ dack1 101 p86 p86 p86 p86 102 as / lcas as / lcas as / lcas pf6 103 rd rd rd pf5 104 hwr hwr hwr pf4 105 lwr / adtrg / irq3 pf3/lwr/ adtrg / irq3 pf3/lwr/ adtrg / irq3 pf3/ adtrg / irq3 106 pf2/ lcas / wait / breqo pf2/ lcas / wait / breqo pf2/ lcas / wait / breqo pf2 107 pf1/ back /buzz pf1/ back /buzz pf1/ back /buzz pf1/buzz 108 pf0/ breq / irq2 pf0/ breq / irq2 pf0/ breq / irq2 pf0/ irq2 109 avcc avcc avcc avcc 110 vref vref vref vref 111 p40/an0 p40/an0 p40/an0 p40/an0 112 p41/an1 p41/an1 p41/an1 p41/an1 113 p42/an2 p42/an2 p42/an2 p42/an2 114 p43/an3 p43/an3 p43/an3 p43/an3 115 p44/an4 p44/an4 p44/an4 p44/an4 116 p45/an5 p45/an5 p45/an5 p45/an5
section 1 overview rev. 3.00 jan 11, 2005 page 12 of 1220 rej09b0186-0300o pin name pin no. mode 4 mode 5 mode 6 mode 7 117 p46/an6/da0 p46/an6/da0 p46/an6/da0 p46/an6/da0 118 p47/an7/da1 p47/an7/da1 p47/an7/da1 p47/an7/da1 119 p90/an8 p90/an8 p90/an8 p90/an8 120 p91/an9 p91/an9 p91/an9 p91/an9 121 p92/an10 p92/an10 p92/an10 p92/an10 122 p93/an11 p93/an11 p93/an11 p93/an11 123 p94/an12 p94/an12 p94/an12 p94/an12 124 p95/an13 p95/an13 p95/an13 p95/an13 125 p96/an14/da2 p96/an14/da2 p96/an14/da2 p96/an14/da2 126 p97/an15/da3 p97/an15/da3 p97/an15/da3 p97/an15/da3 127 avss avss avss avss 128 test1 test1 test1 test1 129 pa4/a20 pa4/a20 pa4/a20 pa4 130 pa5/a21 pa5/a21 pa5/a21 pa5 131 pa6/a22 pa6/a22 pa6/a22 pa6 132 pa7/a23 pa7/a23 pa7/a23 pa7 133 p70/tmri01/ tmci01/ cs4 p70/tmri01/ tmci01/ cs4 p70/tmri01/ tmci01/ cs4 p70/tmri01/tmci01 134 p71/tmri23/ tmci23/ cs5 p71/tmri23/ tmci23/ cs5 p71/tmri23/ tmci23/ cs5 p71/tmri23/tmci23 135 p72/tmo0/ cs6 p72/tmo0/ cs6 p72/tmo0/ cs6 p72/tmo0 136 p73/tmo1/ cs7 p73/tmo1/ cs7 p73/tmo1/ cs7 p73/tmo1 137 p74/tmo2/ mres p74/tmo2/ mres p74/tmo2/ mres p74/tmo2/ mres 138 p75/tmo3/sck3 p75/tmo3/sck3 p75/tmo3/sck3 p75/tmo3/sck3 139 p76/rxd3 p76/rxd3 p76/rxd3 p76/rxd3 140 p77/txd3 p77/txd3 p77/txd3 p77/txd3 141 md0 md0 md0 md0 142 md1 md1 md1 md1 143 md2 md2 md2 md2 144 nc * 1 nc * 1 nc * 1 nc * 1 notes: 1. nc pins should be left open. 2. fwe is used only in the flash memory version. leave open in the mask rom.
section 1 overview rev. 3.00 jan 11, 2005 page 13 of 1220 rej09b0186-0300o 1.3.3 pin functions table 1.3 outlines the pin functions of the h8s/2643 group. table 1.3 pin functions type symbol i/o name and function power vcc input power supply: for connection to the power supply. all vcc pins should be connected to the system power supply. pvcc input port power supply: connect all pins to the port power supply. vss input ground: for connection to ground (0 v). all vss pins should be connected to the system power supply (0 v). clock pllvcc input pll power supply: power supply for on-chip pll oscillator. pllvss input pll ground: ground for on-chip pll oscillator. pllcap input pll capacitance: external capacitance pin for on-chip pll oscillator. xtal input crystal: connects to a crystal oscillator. see section 23, clock pulse generator, for typical connection diagrams for a crystal oscillator and external clock input. extal input crystal: connects to a crystal oscillator. the extal pin can also input an external clock. see section 23, clock pulse generator, for typical connection diagrams for a crystal oscillator and external clock input. osc1 input sub clock: connects to a 32.768 khz crystal oscillator. see section 23, clock pulse generator, for examples of connections to a crystal oscillator. osc2 input sub clock: connects to a 32.768 khz crystal oscillator. see section 23, clock pulse generator, for examples of connections to a crystal oscillator. output system clock: supplies the system clock to an external device.
section 1 overview rev. 3.00 jan 11, 2005 page 14 of 1220 rej09b0186-0300o type symbol i/o name and function operating mode control md2 to md0 input mode pins: these pins set the operating mode. the relation between the settings of pins md2 to md0 and the operating mode is shown below. these pins should not be changed while the h8s/2643 group is operating. md2 md1 md0 operating mode 000 ? 1 ? 10 ? 1 ? 1 0 0 mode 4 1 mode 5 1 0 mode 6 1 mode 7 system control res input reset input: when this pin is driven low, the chip is reset. mres input manual reset: when this pin is driven low, a transmission is made to manual reset mode. stby input standby: when this pin is driven low, a transition is made to hardware standby mode. breq input bus request: used by an external bus master to issue a bus request to the h8s/2643 group. breqo output bus request output: the external bus request signal used when an internal bus master accesses external space in the external bus-released state. back output bus request acknowledge: indicates that the bus has been released to an external bus master. fwe input flash write enable: pin for flash memory use (in planning stage). test1 input test pin: used for testing. input pvcc.
section 1 overview rev. 3.00 jan 11, 2005 page 15 of 1220 rej09b0186-0300o type symbol i/o name and function interrupts nmi input nonmaskable interrupt: requests a nonmaskable interrupt. when this pin is not used, it should be fixed high. irq7 to irq0 input interrupt request: these pins request a maskable interrupt. address bus a23 to a0 output address bus: these pins output an address. data bus d15 to d0 i/o data bus: these pins constitute a bidirectional data bus. bus control cs7 to cs0 output chip select: selection signal for areas 0 to 7. as output address strobe: when this pin is low, it indicates that address output on the address bus is enabled. rd output read: when this pin is low, it indicates that the external address space can be read. hwr output high write/write enable/upper write enable: a strobe signal that writes to external space and indicates that the upper half (d15 to d8) of the data bus is enabled. the 2cas type dram write enable signal. the 2we type dram upper write enable signal. lwr output low write/lower column address strobe/lower write enable: a strobe signal that writes to external space and indicates that the lower half (d7 to d0) of the data bus is enabled. the 2cas type (lcass = 1) dram lower column address strobe signal. the 2we type dram lower write enable signal. cas output upper column address strobe/column address strobe: the 2cas type dram upper column address strobe signal. lcas output lower column address strobe: the 2cas type dram lower column address strobe signal. oe output output enable: output enable signal for dram space read access. wait input wait: requests insertion of a wait state in the bus cycle when accessing external 3-state address space.
section 1 overview rev. 3.00 jan 11, 2005 page 16 of 1220 rej09b0186-0300o type symbol i/o name and function dma controller (dmac) dreq1 , dreq0 input dma request: requests dmac activation. tend1 , tend0 output dma transfer completed 1,0: indicates dmac data transfer end. dack1 , dack0 output dma transfer acknowledge 1,0: dmac single address transfer acknowledge pin. 16-bit timer- pulse unit (tpu) tclkd to tclka input clock input d to a: these pins input an external clock. tioca0, tiocb0, tiocc0, tiocd0 i/o input capture/output compare match a0 to d0: the tgr0a to tgr0d input capture input or output compare output, or pwm output pins. tioca1, tiocb1 i/o input capture/output compare match a1 and b1: the tgr1a and tgr1b input capture input or output compare output, or pwm output pins. tioca2, tiocb2 i/o input capture/output compare match a2 and b2: the tgr2a and tgr2b input capture input or output compare output, or pwm output pins. tioca3, tiocb3, tiocc3, tiocd3 i/o input capture/output compare match a3 to d3: the tgr3a to tgr3d input capture input or output compare output, or pwm output pins. tioca4, tiocb4 i/o input capture/output compare match a4 and b4: the tgr4a and tgr4b input capture input or output compare output, or pwm output pins. tioca5, tiocb5 i/o input capture/output compare match a5 and b5: the tgr5a and tgr5b input capture input or output compare output, or pwm output pins. programmable pulse generator (ppg) po15 to po0 output pulse output: pulse output pins. 8-bit timer tmo0 to tmo3 output compare match output: the compare match output pins. tmci01, tmci23 input counter external clock input: input pins for the external clock input to the counter. tmri01, tmri23 input counter external reset input: the counter reset input pins.
section 1 overview rev. 3.00 jan 11, 2005 page 17 of 1220 rej09b0186-0300o type symbol i/o name and function 14-bit pwm timer (pwmx) pwm0 to pwm3 output pwmx timer output: pwm d/a pulse output pins. watchdog timer (wdt) wdtovf output watchdog timer overflows: the counter overflows signal output pin in watchdog timer mode. buzz output buzz output: output pins for the pulse divided by the watchdog timer. serial communication interface (sci)/ smart card interface txd4, txd3, txd2, txd1, txd0 output transmit data (channel 0 to 4): data output pins. rxd4, rxd3, rxd2, rxd1, rxd0 input receive data (channel 0 to 4): data input pins. sck4, sck3, sck2, sck1, sck0 i/o serial clock (channel 0 to 4): clock i/o pins. irda-equipped sci 1 channel (sci0) irtxd irrxd output/ input irda transmission data/receive data: input/output pins for the data encoded for the irda. i 2 c bus interface (iic) (optional) scl0 scl1 i/o i 2 c clock input (channel 1, 0): i 2 c clock input/output pins. these functions have a bus driving function. scl0's output format is an nmos open drain. sda0 sda1 i/o i 2 c data input/output (channel 1, 0): i 2 c clock input/output pins. these functions have a bus driving function. scl0's output format is an nmos open drain. a/d converter an15 to an0 input analog input: analog input pins. adtrg input a/d conversion external trigger input: pin for input of an external trigger to start a/d conversion. d/a converter da3 to da0 output analog output: analog output pins for d/a converter. a/d converter, d/a converter avcc input analog power supply: a/d converter and d/a converter power supply pin. when the a/d converter and d/a converter are not used, this pin should be connected to the system power supply (+5 v).
section 1 overview rev. 3.00 jan 11, 2005 page 18 of 1220 rej09b0186-0300o type symbol i/o name and function a/d converter, d/a converter avss i nput analog ground: analog circuit ground and reference voltage. a/d converter and d/a converter ground and reference voltage. connect to system power supply (0 v). vref input analog reference power supply: a/d converter and d/a converter reference voltage input pin. when the a/d converter and d/a converter are not used, this pin should be connected to the system power supply (+5 v). i/o ports p17 to p10 i/o port 1: an 8-bit i/o port. input or output can be designated for each bit by means of the port 1 data direction register (p1ddr). p27 to p20 i/o port 2: an 8-bit i/o port. input or output can be designated for each bit by means of the port 2 data direction register (p2ddr). p37 to p30 i/o port 3: an 8-bit i/o port. input or output can be designated for each bit by means of the port 3 data direction register (p3ddr). p47 to p40 input port 4: an 8-bit input port. p52 to p50 i/o port 5: a 3-bit i/o port. input or output can be designated for each bit by means of the port 5 data direction register (p5ddr). p77 to p70 i/o port 7: an 8-bit i/o port. input or output can be designated for each bit by means of the port 7 data direction register (p7ddr). p86 to p80 i/o port 8: a 7-bit i/o port. input or output can be designated for each bit by means of the port 8 data direction register (p8ddr). p97 to p90 input port 9: an 8-bit input port. pa7 to pa0 i/o port a: a 8-bit i/o port. input or output can be designated for each bit by means of the port a data direction register (paddr). pb7 to pb0 i/o port b: an 8-bit i/o port. input or output can be designated for each bit by means of the port b data direction register (pbddr). pc7 to pc0 i/o port c: an 8-bit i/o port. input or output can be designated for each bit by means of the port c data direction register (pcddr). pd7 to pd0 i/o port d: an 8-bit i/o port. input or output can be designated for each bit by means of the port d data direction register (pdddr).
section 1 overview rev. 3.00 jan 11, 2005 page 19 of 1220 rej09b0186-0300o type symbol i/o name and function i/o ports pe7 to pe0 i/o port e: an 8-bit i/o port. input or output can be designated for each bit by means of the port e data direction register (peddr). pf7 to pf0 i/o port f: an 8-bit i/o port. input or output can be designated for each bit by means of the port f data direction register (pfddr). pg4 to pg0 i/o port g: a 5-bit i/o port. input or output can be designated for each bit by means of the port g data direction register (pgddr).
section 1 overview rev. 3.00 jan 11, 2005 page 20 of 1220 rej09b0186-0300o
section 2 cpu rev. 3.00 jan 11, 2005 page 21 of 1220 rej09b0186-0300o section 2 cpu 2.1 overview the h8s/2600 cpu is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the h8/300 and h8/300h cpus. the h8s/2600 cpu has sixteen 16-bit general registers, can address a 16-mbyte (architecturally 4-gbyte) linear address space, and is ideal for realtime control. 2.1.1 features the h8s/2600 cpu has the following features. ? upward-compatible with h8/300 and h8/300h cpus ? can execute h8/300 and h8/300h object programs ? general-register architecture ? sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) ? sixty-nine basic instructions ? 8/16/32-bit arithmetic and logic instructions ? multiply and divide instructions ? powerful bit-manipulation instructions ? multiply-and-accumulate instructions ? eight addressing modes ? register direct [rn] ? register indirect [@ern] ? register indirect with displacement [@(d:16,ern) or @(d:32,ern)] ? register indirect with post-increment or pre-decrement [@ern+ or @?ern] ? absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] ? immediate [#xx:8, #xx:16, or #xx:32] ? program-counter relative [@(d:8,pc) or @(d:16,pc)] ? memory indirect [@@aa:8] ? 16-mbyte address space ? program: 16 mbytes ? data: 16 mbytes (4 gbytes architecturally)
section 2 cpu rev. 3.00 jan 11, 2005 page 22 of 1220 rej09b0186-0300o ? high-speed operation ? all frequently-used instructions execute in one or two states ? maximum clock rate : 25 mhz ? 8/16/32-bit register-register add/subtract : 40 ns ? 8 8-bit register-register multiply : 120 ns ? 16 8-bit register-register divide : 480 ns ? 16 16-bit register-register multiply : 160 ns ? 32 16-bit register-register divide : 800 ns ? two cpu operating modes ? normal mode* ? advanced mode note: * not available in the h8s/2643 group. ? power-down state ? transition to power-down state by sleep instruction ? cpu clock speed selection 2.1.2 differences between h8s/2600 cpu and h8s/2000 cpu the differences between the h8s/2600 cpu and the h8s/2000 cpu are as shown below. ? register configuration ? the mac register is supported only by the h8s/2600 cpu. ? basic instructions ? the four instructions mac, clrmac, ldmac, and stmac are supported only by the h8s/2600 cpu. ? number of execution states ? the number of execution states of the mulxu and mulxs instructions is different in each cpu. execution states instruction mnemonic h8s/2600 h8s/2000 mulxu mulxu.b rs, rd 3 12 mulxu.w rs, erd 4 20 mulxs mulxs.b rs, rd 4 13 mulxs.w rs, erd 5 21
section 2 cpu rev. 3.00 jan 11, 2005 page 23 of 1220 rej09b0186-0300o in addition, there are differences in address space, ccr and exr register functions, power-down modes, etc., depending on the model. 2.1.3 differences from h8/300 cpu in comparison to the h8/300 cpu, the h8s/2600 cpu has the following enhancements. ? more general registers and control registers ? eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added. ? expanded address space ? normal mode* supports the same 64-kbyte address space as the h8/300 cpu. ? advanced mode supports a maximum 16-mbyte address space. note: * not available in the h8s/2643 group. ? enhanced addressing ? the addressing modes have been enhanced to make effective use of the 16-mbyte address space. ? enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced. ? signed multiply and divide instructions have been added. ? a multiply-and-accumulate instruction has been added. ? two-bit shift instructions have been added. ? instructions for saving and restoring multiple registers have been added. ? a test and set instruction has been added. ? higher speed ? basic instructions execute twice as fast. 2.1.4 differences from h8/300h cpu in comparison to the h8/300h cpu, the h8s/2600 cpu has the following enhancements. ? additional control register ? one 8-bit and two 32-bit control registers have been added. ? enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced. ? a multiply-and-accumulate instruction has been added. ? two-bit shift instructions have been added.
section 2 cpu rev. 3.00 jan 11, 2005 page 24 of 1220 rej09b0186-0300o ? instructions for saving and restoring multiple registers have been added. ? a test and set instruction has been added. ? higher speed ? basic instructions execute twice as fast. 2.2 cpu operating modes the h8s/2600 cpu has two operating modes: normal and advanced. normal mode* supports a maximum 64-kbyte address space. advanced mode supports a maximum 16-mbyte total address space (architecturally a maximum 16-mbyte program area and a maximum of 4 gbytes for program and data areas combined). the mode is selected by the mode pins of the microcontroller. note: * not available in the h8s/2643 group. cpu operating modes note: * not available in the h8s/2643 group. normal mode * advanced mode maximum 64 kbytes, program and data areas combined maximum 16-mbytes for program and data areas combined figure 2.1 cpu operating modes (1) normal mode (not available in the h8s/2643 group) the exception vector table and stack have the same structure as in the h8/300 cpu. address space: a maximum address space of 64 kbytes can be accessed. extended registers (en): the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. when en is used as a 16-bit register it can contain any value, even when the corresponding general register (rn) is used as an address register. if the general register is referenced in the register indirect addressing mode with pre-decrement (@ ? rn) or post-increment (@rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (en) will be affected.
section 2 cpu rev. 3.00 jan 11, 2005 page 25 of 1220 rej09b0186-0300o instruction set: all instructions and addressing modes can be used. only the lower 16 bits of effective addresses (ea) are valid. exception vector table and memory indirect branch addresses: in normal mode the top area starting at h'0000 is allocated to the exception vector table. one branch address is stored per 16 bits (figure 2.2). the exception vector table differs depending on the microcontroller. for details of the exception vector table, see section 4, exception handling. h'0000 h'0001 h'0002 h'0003 h'0004 h'0005 h'0006 h'0007 h'0008 h'0009 h'000a h'000b power-on reset exception vector manual reset exception vector exception vector 1 exception vector 2 exception vector table (reserved for system use) figure 2.2 exception vector table (normal mode) the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in normal mode the operand is a 16-bit word operand, providing a 16- bit branch address. branch addresses can be stored in the top area from h'0000 to h'00ff. note that this area is also used for the exception vector table.
section 2 cpu rev. 3.00 jan 11, 2005 page 26 of 1220 rej09b0186-0300o stack structure: when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc, condition-code register (ccr), and extended control register (exr) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3. when exr is invalid, it is not pushed onto the stack. for details, see section 4, exception handling. (a) subroutine branch (b) exception handling pc (16 bits) exr * 1 reserved * 1 * 3 ccr ccr * 3 pc (16 bits) sp sp notes: 1. 2. 3. when exr is not used it is not stored on the stack. sp when exr is not used. ignored when returning. (sp ) * 2 figure 2.3 stack structure in normal mode (2) advanced mode address space: linear access is provided to a 16-mbyte maximum address space (architecturally a maximum 16-mbyte program area and a maximum 4-gbyte data area, with a maximum of 4 gbytes for program and data areas combined). extended registers (en): the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. instruction set: all instructions and addressing modes can be used.
section 2 cpu rev. 3.00 jan 11, 2005 page 27 of 1220 rej09b0186-0300o exception vector table and memory indirect branch addresses: in advanced mode the top area starting at h'00000000 is allocated to the exception vector table in units of 32 bits. in each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4). for details of the exception vector table, see section 4, exception handling. h'00000000 h'00000003 h'00000004 h'0000000b h'0000000c exception vector table reserved power-on reset exception vector (reserved for system use) reserved exception vector 1 reserved manual reset exception vector h'00000010 h'00000008 h'00000007 figure 2.4 exception vector table (advanced mode) the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. the upper 8 bits of these 32 bits are a reserved area that is regarded as h'00. branch addresses can be stored in the area from h'00000000 to h'000000ff. note that the first part of this range is also the exception vector table.
section 2 cpu rev. 3.00 jan 11, 2005 page 28 of 1220 rej09b0186-0300o stack structure: in advanced mode, when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc, condition-code register (ccr), and extended control register (exr) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. when exr is invalid, it is not pushed onto the stack. for details, see section 4, exception handling. (a) subroutine branch (b) exception handling pc (24 bits) exr * 1 reserved * 1 * 3 ccr pc (24 bits) sp sp notes: 1. 2. 3. when exr is not used it is not stored on the stack. sp when exr is not used. ignored when returning. (sp ) * 2 reserved figure 2.5 stack structure in advanced mode
section 2 cpu rev. 3.00 jan 11, 2005 page 29 of 1220 rej09b0186-0300o 2.3 address space figure 2.6 shows a memory map of the h8s/2600 cpu. the h8s/2600 cpu provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-mbyte (architecturally 4-gbyte) address space in advanced mode. (b) advanced mode h'0000 h'ffff h'00000000 h'ffffffff h'00ffffff (a) normal mode * data area program area cannot be used by the h8s/2643 group note: * not available in the h8s/2643 group. figure 2.6 memory map
section 2 cpu rev. 3.00 jan 11, 2005 page 30 of 1220 rej09b0186-0300o 2.4 register configuration 2.4.1 overview the cpu has the internal registers shown in figure 2.7. there are two types of registers: general registers and control registers. t ???? i2 i1 i0 exr 76543210 pc 23 0 15 07 07 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l general registers (rn) and extended registers (en) control registers (cr) legend: stack pointer program counter extended control register trace bit interrupt mask bits condition-code register interrupt mask bit user bit or interrupt mask bit * sp: pc: exr: t: i2 to i0: ccr: i: ui: note: * cannot be used as an interrupt mask bit in the h8s/2643 group. er0 er1 er2 er3 er4 er5 er6 er7 (sp) i ui hunzvc ccr 76543210 sign extension 63 32 41 0 31 mac macl half-carry flag user bit negative flag zero flag overflow flag carry flag multiply-accumulate register h: u: n: z: v: c: mac: mach figure 2.7 cpu registers
section 2 cpu rev. 3.00 jan 11, 2005 page 31 of 1220 rej09b0186-0300o 2.4.2 general registers the cpu has eight 32-bit general registers. these general registers are all functionally alike and can be used as both address registers and data registers. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. when the general registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit general registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum sixteen 8-bit registers. figure 2.8 illustrates the usage of the general registers. the usage of each register can be selected independently. address registers 32-bit registers 16-bit registers 8-bit registers er registers (er0 to er7) e registers (extended registers) (e0 to e7) r registers (r0 to r7) rh registers (r0h to r7h) rl registers (r0l to r7l) figure 2.8 usage of general registers
section 2 cpu rev. 3.00 jan 11, 2005 page 32 of 1220 rej09b0186-0300o general register er7 has the function of stack pointer (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2.9 shows the stack. free area stack area sp (er7) figure 2.9 stack 2.4.3 control registers the control registers are the 24-bit program counter (pc), 8-bit extended control register (exr), 8-bit condition-code register (ccr), and 64-bit multiply-accumulate register (mac). (1) program counter (pc) this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. (when an instruction is fetched, the least significant pc bit is regarded as 0.) (2) extended control register (exr) this 8-bit register contains the trace bit (t) and three interrupt mask bits (i2 to i0). bit 7?trace bit (t): selects trace mode. when this bit is cleared to 0, instructions are executed in sequence. when this bit is set to 1, a trace exception is generated each time an instruction is executed. bits 6 to 3?reserved: they are always read as 1.
section 2 cpu rev. 3.00 jan 11, 2005 page 33 of 1220 rej09b0186-0300o bits 2 to 0?interrupt mask bits (i2 to i0): these bits designate the interrupt mask level (0 to 7). for details, refer to section 5, interrupt controller. operations can be performed on the exr bits by the ldc, stc, andc, orc, and xorc instructions. all interrupts, including nmi, are disabled for three states after one of these instructions is executed, except for stc. (3) condition-code register (ccr) this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. bit 7?interrupt mask bit (i): masks interrupts other than nmi when set to 1. (nmi is accepted regardless of the i bit setting.) the i bit is set to 1 by hardware at the start of an exception- handling sequence. for details, refer to section 5, interrupt controller. bit 6?user bit or interrupt mask bit (ui): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. this bit can also be used as an interrupt mask bit. for details, refer to section 5, interrupt controller. bit 5?half-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. bit 4?user bit (u): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. bit 3?negative flag (n): stores the value of the most significant bit (sign bit) of data. bit 2?zero flag (z): set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. bit 1?overflow flag (v): set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. bit 0?carry flag (c): set to 1 when a carry occurs, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions, to indicate a borrow ? shift and rotate instructions, to store the value shifted out of the end bit
section 2 cpu rev. 3.00 jan 11, 2005 page 34 of 1220 rej09b0186-0300o the carry flag is also used as a bit accumulator by bit manipulation instructions. some instructions leave some or all of the flag bits unchanged. for the action of each instruction on the flag bits, refer to appendix a.1, list of instructions. operations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branching conditions for conditional branch (bcc) instructions. (4) multiply-accumulate register (mac) this 64-bit register stores the results of multiply-and-accumulate operations. it consists of two 32- bit registers denoted mach and macl. the lower 10 bits of mach are valid; the upper bits are a sign extension. 2.4.4 initial register values reset exception handling loads the cpu's program counter (pc) from the vector table, clears the trace bit in exr to 0, and sets the interrupt mask bits in ccr and exr to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (er7) is not initialized. the stack pointer should therefore be initialized by an mov.l instruction executed immediately after a reset.
section 2 cpu rev. 3.00 jan 11, 2005 page 35 of 1220 rej09b0186-0300o 2.5 data formats the cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ? , 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.5.1 general register data formats figure 2.10 shows the data formats in general registers. 76543210 don ? t care 70 don ? t care 76543210 43 70 70 don ? t care upper lower lsb msb lsb data type register number data format 1-bit data 1-bit data 4-bit bcd data 4-bit bcd data byte data byte data rnh rnl rnh rnl rnh rnl msb don ? t care upper lower 43 70 don ? t care 70 don ? t care 70 figure 2.10 general register data formats (1)
section 2 cpu rev. 3.00 jan 11, 2005 page 36 of 1220 rej09b0186-0300o 0 msb lsb 15 word data word data rn en 0 lsb 15 16 msb 31 en rn general register er general register e general register r general register rh general register rl most significant bit least significant bit legend: ern: en: rn: rnh: rnl: msb: lsb: 0 msb lsb 15 longword data ern data type register number data format figure 2.10 general register data formats (2)
section 2 cpu rev. 3.00 jan 11, 2005 page 37 of 1220 rej09b0186-0300o 2.5.2 memory data formats figure 2.11 shows the data formats in memory. the cpu can access word data and longword data in memory, but word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. this also applies to instruction fetches. 76543210 70 msb lsb msb lsb msb lsb data type data format 1-bit data byte data word data longword data address address l address l address 2m address 2m + 1 address 2n address 2n + 1 address 2n + 2 address 2n + 3 figure 2.11 memory data formats when er7 is used as an address register to access the stack, the operand size should be word size or longword size.
section 2 cpu rev. 3.00 jan 11, 2005 page 38 of 1220 rej09b0186-0300o 2.6 instruction set 2.6.1 overview the h8s/2600 cpu has 69 types of instructions. the instructions are classified by function in table 2.1. table 2.1 instruction classification function instructions size types data transfer mov bwl 5 pop * 1 , push * 1 wl ldm * 5 , stm * 5 l movfpe * 3 , movtpe * 3 b arithmetic add, sub, cmp, neg bwl 23 operations addx, subx, daa, das b inc, dec bwl adds, subs l mulxu, divxu, mulxs, divxs bw extu, exts wl tas * 4 b mac, ldmac, stmac, clrmac ? logic operations and, or, xor, not bwl 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr bwl 8 bit manipulation bset, bclr, bnot, btst, bld, bild, bst, bist, band, biand, bor, bior, bxor, bixor b14 branch bcc * 2 , jmp, bsr, jsr, rts ? 5 system control trapa, rte, sleep, ldc, stc, andc, orc, xorc, nop ? 9 block data transfer eepmov ? 1 legend: b: byte size w: word size l: longword size notes: 1. pop.w rn and push.w rn are identical to mov.w @sp+, rn and mov.w rn, @-sp. pop.l ern and push.l ern are identical to mov.l @sp+, ern and mov.l ern, @-sp. 2. bcc is the general name for conditional branch instructions. 3. not available in the h8s/2643 group. 4. only register er0, er1, er4, or er5 should be used when using the tas instruction. 5. only register er0 to er6 should be used when using the stm/ldm instruction.
section 2 cpu rev. 3.00 jan 11, 2005 page 39 of 1220 rej09b0186-0300o 2.6.2 instructions and addressing modes table 2.2 indicates the combinations of instructions and addressing modes that the h8s/2600 cpu can use. table 2.2 combinations of instructions and addressing modes addressing modes function data transfer arithmetic operations instruction mov bwl bwl bwl bwl bwl bwl b bwl ? bwl ? ? ? ? pop, push ? ? ? ? ? ? ? ? ? ? ? ? ? wl ldm * 3 , stm * 3 ? ? ? ? ? ? ? ? ? ? ? ? ? l add, cmp bwl bwl ? ? ? ? ? ? ? ? ? ? ? ? sub wl bwl ? ? ? ? ? ? ? ? ? ? ? ? addx, subx b b ? ? ? ? ? ? ? ? ? ? ? ? adds, subs ? l ? ? ? ? ? ? ? ? ? ? ? ? inc, dec ? bwl ? ? ? ? ? ? ? ? ? ? ? ? daa, das ? b ? ? ? ? ? ? ? ? ? ? ? ? neg ? bwl ? ? ? ? ? ? ? ? ? ? ? ? extu, exts ? wl ? ? ? ? ? ? ? ? ? ? ? ? tas * 2 ? ? b ? ? ? ? ? ? ? ? ? ? ? mac ? ? ? ? ? ? ? ? ? ? ? ? ? clrmac ? ? ? ? ? ? ? ? ? ? ? ? ? movepe * 1 , ? ? ? ? ? ? ? b ? ? ? ? ? ? movtpe * 1 mulxu, ? bw ? ? ? ? ? ? ? ? ? ? ? ? divxu mulxs, ? bw ? ? ? ? ? ? ? ? ? ? ? ? divxs ldmac, ? l ? ? ? ? ? ? ? ? ? ? ? ? stmac #xx rn @ern @(d:16,ern) @(d:32,ern) @ ? ern/@ern+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,pc) @(d:16,pc) @@aa:8 ?
section 2 cpu rev. 3.00 jan 11, 2005 page 40 of 1220 rej09b0186-0300o addressing modes function logic operations system control block data transfer shift bit manipulation branch instruction and, or, bwl bwl ? ? ? ? ? ? ? ? ? ? ? ? xor andc, b ? ? ? ? ? ? ? ? ? ? ? ? ? orc, xorc bcc, bsr ? ? ? ? ? ? ? ? ? ? ? ? jmp, jsr ? ? ? ? ? ? ? ? ? ? ? ? rts ? ? ? ? ? ? ? ? ? ? ? ? ? trapa ? ? ? ? ? ? ? ? ? ? ? ? ? rte ? ? ? ? ? ? ? ? ? ? ? ? ? sleep ? ? ? ? ? ? ? ? ? ? ? ? ? ldc b b w w w w ? w ? w ? ? ? ? stc ? b w w w w ? w ? w ? ? ? ? not ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? b b ? ? ? b b ? b ? ? ? ? nop ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bw legend: b: byte w: word l: longword #xx rn @ern @(d:16,ern) @(d:32,ern) @ ? ern/@ern+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,pc) @(d:16,pc) @@aa:8 ? notes: 1. 2. 3. not available in the h8s/2643 group. only register er0, er1, er4, or er5 should be used when using the tas instruction. onl y re g ister er0 to er6 should be used when usin g the stm/ldm instruction.
section 2 cpu rev. 3.00 jan 11, 2005 page 41 of 1220 rej09b0186-0300o 2.6.3 table of instructions classified by function table 2.3 summarizes the instructions in each functional category. the notation used in table 2.3 is defined below. operation notation rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register) mac multiply-accumulate register (32-bit register) (ead) destination operand (eas) source operand exr extended control register ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition ? subtraction multiplication division logical and logical or logical exclusive or move ? not (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7).
section 2 cpu rev. 3.00 jan 11, 2005 page 42 of 1220 rej09b0186-0300o table 2.3 instructions classified by function type instruction size * 1 function data transfer mov b/w/l (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b cannot be used in the h8s/2643 group. movtpe b cannot be used in the h8s/2643 group. pop w/l @sp+ rn pops a register from the stack. pop.w rn is identical to mov.w @sp+, rn. pop.l ern is identical to mov.l @sp+, ern. push w/l rn @ ? sp pushes a register onto the stack. push.w rn is identical to mov.w rn, @ ? sp. push.l ern is identical to mov.l ern, @ ? sp. ldm * 3 l @sp+ rn (register list) pops two or more general registers from the stack. stm * 3 l rn (register list) @ ? sp pushes two or more general registers onto the stack. arithmetic operations add sub b/w/l rd rs rd, rd #imm rd performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (immediate byte data cannot be subtracted from byte data in a general register. use the subx or add instruction.) addx subx b rd rs c rd, rd #imm c rd performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. inc dec b/w/l rd 1 rd, rd 2 rd increments or decrements a general register by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds subs l rd 1 rd, rd 2 rd, rd 4 rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa das b rd decimal adjust rd decimal-adjusts an addition or subtraction result in a general register by referring to the ccr to produce 4-bit bcd data.
section 2 cpu rev. 3.00 jan 11, 2005 page 43 of 1220 rej09b0186-0300o type instruction size * 1 function arithmetic operations mulxu b/w rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. mulxs b/w rd rs rd performs signed multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. divxu b/w rd rs rd performs unsigned division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16- bit remainder. divxs b/w rd rs rd performs signed division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16- bit remainder. cmp b/w/l rd ? rs, rd ? #imm compares data in a general register with data in another general register or with immediate data, and sets ccr bits according to the result. neg b/w/l 0 ? rd rd takes the two's complement (arithmetic complement) of data in a general register. extu w/l rd (zero extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. exts w/l rd (sign extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. tas b @erd ? 0, 1 ( of @erd) * 2 tests memory contents, and sets the most significant bit (bit 7) to 1. mac ? (eas) (ead) + mac mac performs signed multiplication on memory contents and adds the result to the multiply-accumulate register. the following operations can be performed: 16 bits 16 bits + 32 bits 32 bits, saturating 16 bits 16 bits + 42 bits 42 bits, non-saturating
section 2 cpu rev. 3.00 jan 11, 2005 page 44 of 1220 rej09b0186-0300o type instruction size * 1 function arithmetic operations clrmac ? 0 mac clears the multiply-accumulate register to zero. ldmac stmac lrs mac, mac rd transfers data between a general register and a multiply-accumulate register. logic operations and b/w/l rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l ? (rd) (rd) takes the one's complement of general register contents. shift operations shal shar b/w/l rd (shift) rd performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. shll shlr b/w/l rd (shift) rd performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. rotl rotr b/w/l rd (rotate) rd rotates general register contents. 1-bit or 2-bit rotation is possible. rotxl rotxr b/w/l rd (rotate) rd rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. bit- manipulation instructions bset b 1 ( of ) sets a specified bit in a general register or memory operand to 1. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. bclr b 0 ( of ) clears a specified bit in a general register or memory operand to 0. the bit number is specified by 3-bit immediate data or the lower three bits of a general register.
section 2 cpu rev. 3.00 jan 11, 2005 page 45 of 1220 rej09b0186-0300o type instruction size * 1 function bit- manipulation instructions bnot b ? ( of ) ( of ) inverts a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. btst b ? ( of ) z tests a specified bit in a general register or memory operand and sets or clears the z flag accordingly. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. band biand b b c ( of ) c ands the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ? ( of ) c ands the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bor bior b b c ( of ) c ors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ? ( of ) c ors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bxor bixor b b c ( of ) c exclusive-ors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ? ( of ) c exclusive-ors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bld bild b b ( of ) c transfers a specified bit in a general register or memory operand to the carry flag. ? ( of ) c transfers the inverse of a specified bit in a general register or memory operand to the carry flag. the bit number is specified by 3-bit immediate data.
section 2 cpu rev. 3.00 jan 11, 2005 page 46 of 1220 rej09b0186-0300o type instruction size * 1 function bit- manipulation instructions bst bist b b c ( of ) transfers the carry flag value to a specified bit in a general register or memory operand. ? c ( of ) transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediate data. branch instructions bcc ? branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra(bt) always (true) always brn(bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc(bhs) carry clear (high or same) c = 0 bcs(blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp ? branches unconditionally to a specified address. bsr ? branches to a subroutine at a specified address. jsr ? branches to a subroutine at a specified address. rts ? returns from a subroutine trapa ? starts trap-instruction exception handling. system control instructions rte ? returns from an exception-handling routine. sleep ? causes a transition to a power-down state.
section 2 cpu rev. 3.00 jan 11, 2005 page 47 of 1220 rej09b0186-0300o type instruction size * 1 function system control instructions ldc b/w (eas) ccr, (eas) exr moves the source operand contents or immediate data to ccr or exr. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. stc b/w ccr (ead), exr (ead) transfers ccr or exr contents to a general register or memory. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. andc b ccr #imm ccr, exr #imm exr logically ands the ccr or exr contents with immediate data. orc b ccr #imm ccr, exr #imm exr logically ors the ccr or exr contents with immediate data. xorc b ccr #imm ccr, exr #imm exr logically exclusive-ors the ccr or exr contents with immediate data. nop ? pc + 2 pc only increments the program counter. block data transfer instruction eepmov.b eepmov.w ? ? if r4l 0 then repeat @er5+ @er6+ r4l ? 1 r4l until r4l = 0 else next; if r4 0 then repeat @er5+ @er6+ r4 ? 1 r4 until r4 = 0 else next; transfers a data block according to parameters set in general registers r4l or r4, er5, and er6. r4l or r4: size of block (bytes) er5: starting source address er6: starting destination address execution of the next instruction begins as soon as the transfer is completed. notes: 1. size refers to the operand size. b: byte w: word l: longword
section 2 cpu rev. 3.00 jan 11, 2005 page 48 of 1220 rej09b0186-0300o 2. only register er0, er1, er4, or er5 should be used when using the tas instruction. 3. only register er0 to er6 should be used when using the stm/ldm instruction. 2.6.4 basic instruction formats the h8s/2643 group instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op field), a register field (r field), an effective address extension (ea field), and a condition field (cc). (1) operation field indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. the operation field always includes the first four bits of the instruction. some instructions have two operation fields. (2) register field specifies a general register. address registers are specified by 3 bits, data registers by 3 bits or 4 bits. some instructions have two register fields. some have no register field. (3) effective address extension eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. (4) condition field specifies the branching condition of bcc instructions.
section 2 cpu rev. 3.00 jan 11, 2005 page 49 of 1220 rej09b0186-0300o figure 2.12 shows examples of instruction formats. op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b @(d:16, rn), rm, etc. (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension rn rm op ea (disp) (4) operation field, effective address extension, and condition field op cc ea (disp) bra d:16, etc figure 2.12 instruction formats (examples)
section 2 cpu rev. 3.00 jan 11, 2005 page 50 of 1220 rej09b0186-0300o 2.7 addressing modes and effective address calculation 2.7.1 addressing mode the cpu supports the eight addressing modes listed in table 2.4. each instruction uses a subset of these addressing modes. arithmetic and logic instructions can use the register direct and immediate modes. data transfer instructions can use all addressing modes except program-counter relative and memory indirect. bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2.4 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:16,ern)/@(d:32,ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @ ? ern 5 absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 immediate #xx:8/#xx:16/#xx:32 7 program-counter relative @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8 (1) register direct?rn the register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. (2) register indirect?@ern the register field of the instruction code specifies an address register (ern) which contains the address of the operand on memory. if the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (h'00).
section 2 cpu rev. 3.00 jan 11, 2005 page 51 of 1220 rej09b0186-0300o (3) register indirect with displacement?@(d:16, ern) or @(d:32, ern) a 16-bit or 32-bit displacement contained in the instruction is added to an address register (ern) specified by the register field of the instruction, and the sum gives the address of a memory operand. a 16-bit displacement is sign-extended when added. (4) register indirect with post-increment or pre-decrement?@ern+ or @-ern ? register indirect with post-increment ? @ern+ the register field of the instruction code specifies an address register (ern) which contains the address of a memory operand. after the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. the value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. for word or longword transfer instruction, the register value should be even. ? register indirect with pre-decrement ? @-ern the value 1, 2, or 4 is subtracted from an address register (ern) specified by the register field in the instruction code, and the result becomes the address of a memory operand. the result is also stored in the address register. the value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. for word or longword transfer instruction, the register value should be even. (5) absolute address?@aa:8, @aa:16, @aa:24, or @aa:32 the instruction code contains the absolute address of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). to access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. for an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (h'ffff). for a 16-bit absolute address the upper 16 bits are a sign extension. a 32-bit absolute address can access the entire address space. a 24-bit absolute address (@aa:24) indicates the address of a program instruction. the upper 8 bits are all assumed to be 0 (h'00). table 2.5 indicates the accessible absolute address ranges.
section 2 cpu rev. 3.00 jan 11, 2005 page 52 of 1220 rej09b0186-0300o table 2.5 absolute address access ranges absolute address normal mode * advanced mode data address 8 bits (@aa:8) h'ff00 to h'ffff h'ffff00 to h'ffffff 16 bits (@aa:16) h'0000 to h'ffff h'000000 to h'007fff, h'ff8000 to h'ffffff 32 bits (@aa:32) h'000000 to h'ffffff program instruction address 24 bits (@aa:24) note: * not available in the h8s/2643 group. (6) immediate?#xx:8, #xx:16, or #xx:32 the instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the adds, subs, inc, and dec instructions contain immediate data implicitly. some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. the trapa instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) program-counter relative?@(d:8, pc) or @(d:16, pc) this mode is used in the bcc and bsr instructions. an 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit pc contents to generate a branch address. only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (h'00). the pc value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is ? 126 to +128 bytes ( ? 63 to +64 words) or ? 32766 to +32768 bytes ( ? 16383 to +16384 words) from the branch instruction. the resulting value should be an even number. (8) memory indirect?@@aa:8 this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memory operand. this memory operand contains a branch address. the upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff in normal mode, h'000000 to h'0000ff in advanced mode). in normal mode* the memory operand is a word operand and the branch address is 16 bits long. in advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (h'00). note that the first part of the address range is also the exception vector area. for further details, refer to section 4, exception handling.
section 2 cpu rev. 3.00 jan 11, 2005 page 53 of 1220 rej09b0186-0300o note: * not available in the h8s/2643 group. (a) normal mode * (b) advanced mode branch address specified by @aa:8 specified by @aa:8 reserved branch address note: * not available in the h8s/2643 group. figure 2.13 branch address specification in memory indirect mode if an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (for further information, see section 2.5.2, memory data formats.) 2.7.2 effective address calculation table 2.6 indicates how effective addresses are calculated in each addressing mode. in normal mode* the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. note: * not available in the h8s/2643 group.
section 2 cpu rev. 3.00 jan 11, 2005 page 54 of 1220 rej09b0186-0300o table 2.6 effective address calculation register indirect with post-increment or pre-decrement register indirect with post-increment @ern+ no. addressing mode and instruction format effective address calculation effective address (ea) 1 register direct (rn) op rm rn operand is general register contents. register indirect (@ern) 2 register indirect with displacement @(d:16, ern) or @(d:32, ern) 3 register indirect with pre-decrement @ ? ern 4 general register contents general register contents sign extension disp general register contents 1, 2, or 4 general register contents 1, 2, or 4 byte word longword 1 2 4 operand size value added 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 op r r op op r r op disp 24 23 don ? t care 24 23 don ? t care 24 23 don ? t care 24 23 don ? t care
section 2 cpu rev. 3.00 jan 11, 2005 page 55 of 1220 rej09b0186-0300o 5 @aa:8 absolute address @aa:16 @aa:32 6 immediate #xx:8/#xx:16/#xx:32 31 0 8 7 operand is immediate data. no. addressing mode and instruction format effective address calculation effective address (ea) @aa:24 31 0 16 15 31 0 24 23 31 0 op abs op abs abs op op abs op imm h'ffff don ? t care 24 23 don ? t care 24 23 don ? t care 24 23 don ? t care sign extension
section 2 cpu rev. 3.00 jan 11, 2005 page 56 of 1220 rej09b0186-0300o 31 0 0 0 7 program-counter relative @(d:8, pc)/@(d:16, pc) 8 memory indirect @@aa:8 normal mode * advanced mode 0 no. addressing mode and instruction format effective address calculation effective address (ea) 23 23 31 8 7 0 15 0 31 8 7 0 disp h'000000 abs h'000000 31 0 24 23 31 0 16 15 31 0 24 23 op disp op abs op abs sign extension pc contents abs memory contents memory contents h'00 don ? t care 24 23 don ? t care don ? t care note: * not available in the h8s/2643 group.
section 2 cpu rev. 3.00 jan 11, 2005 page 57 of 1220 rej09b0186-0300o 2.8 processing states 2.8.1 overview the cpu has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. figure 2.14 shows a diagram of the processing states. figure 2.15 indicates the state transitions. reset state the cpu and all on-chip supporting modules have been initialized and are stopped. exception-handling state a transient state in which the cpu changes the normal processing flow in response to a reset, interrupt, or trap instruction. program execution state the cpu executes program instructions in sequence. bus-released state the external bus has been released in response to a bus request signal from a bus master other than the cpu. power-down state cpu operation is stopped to conserve power. * sleep mode software standby mode hardware standby mode processing states note: * the power-down state also includes a medium-speed mode, module stop mode, subactive mode, subsleep mode, and watch mode. figure 2.14 processing states
section 2 cpu rev. 3.00 jan 11, 2005 page 58 of 1220 rej09b0186-0300o exception handling state bus-released state hardware standby mode * 2 software standby mode power-on reset state * 1 sleep mode power-down state * 3 program execution state end of bus request bus request interr upt request external interrupt request res= high request for ex ception handling stby= high, res= low end of bus request bus reque st sleep instruction with ssby = 0 sleep instruction with ssby = 1 notes: 1. 2. 3. from any state except hardware standby mode, a transition to the power-on reset state occurs whenever res goes low. from any state except hardware standby mode and power-on reset mode, a transition to the manual reset state occurs whenever mres goes low. a transition can also be made to the reset state when the watchdog timer overflows. from any state, a transition to hardware standby mode occurs when stby goes low. apart from these states, there are also the watch mode, subactive mode, and the subsleep mode. see section 24, power-down modes. e nd of exception handling manual reset state * 1 mres= high reset state * 1 figure 2.15 state transitions 2.8.2 reset state the cpu enters the reset state when the res pin goes low, or when the mres pin goes low while manual resets are enabled by the mrese bit. in the reset state, currently executing processing is halted and all interrupts are disabled. for details of mrese bit setting, see section 3.2.2, system control register (syscr). reset exception handling starts when the res or mres pin* changes from low to high. the reset state can also be entered in the event of watchdog timer overflow. for details see section 15, watchdog timer. note: * mres pin in the case of a manual reset.
section 2 cpu rev. 3.00 jan 11, 2005 page 59 of 1220 rej09b0186-0300o 2.8.3 exception-handling state the exception-handling state is a transient state that occurs when the cpu alters the normal processing flow due to a reset, interrupt, or trap instruction. the cpu fetches a start address (vector) from the exception vector table and branches to that address. (1) types of exception handling and their priority exception handling is performed for traces, resets, interrupts, and trap instructions. table 2.7 indicates the types of exception handling and their priority. trap instruction exception handling is always accepted, in the program execution state. exception handling and the stack structure depend on the interrupt control mode set in syscr. table 2.7 exception handling types and priority priority type of exception detection timing start of exception handling high reset synchronized with clock exception handling starts immediately after a low-to-high transition at the res pin, or when the watchdog timer overflows. trace end of instruction execution or end of exception-handling sequence * 1 when the trace (t) bit is set to 1, the trace starts at the end of the current instruction or current exception-handling sequence interrupt end of instruction execution or end of exception-handling sequence * 2 when an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence low trap instruction when trapa instruction is executed exception handling starts when a trap (trapa) instruction is executed * 3 notes: 1. traces are enabled only in interrupt control mode 2. trace exception-handling is not executed at the end of the rte instruction. 2. interrupts are not detected at the end of the andc, orc, xorc, and ldc instructions, or immediately after reset exception handling. 3. trap instruction exception handling is always accepted, in the program execution state.
section 2 cpu rev. 3.00 jan 11, 2005 page 60 of 1220 rej09b0186-0300o (2) reset exception handling after the res pin has gone low and the reset state has been entered, when res pin goes high again, reset exception handling starts. after the reset state has been entered by driving the mres pin low while manual resets are enabled by the mrese bit, reset exception handling starts when mres pin is driven high again. the cpu enters the power-on reset state when the res pin is low, and enters the manual reset state when the mres pin is low. when reset exception handling starts the cpu fetches a start address (vector) from the exception vector table and starts program execution from that address. all interrupts, including nmi, are disabled during reset exception handling and after it ends. (3) traces traces are enabled only in interrupt control mode 2. trace mode is entered when the t bit of exr is set to 1. when trace mode is established, trace exception handling starts at the end of each instruction. at the end of a trace exception-handling sequence, the t bit of exr is cleared to 0 and trace mode is cleared. interrupt masks are not affected. the t bit saved on the stack retains its value of 1, and when the rte instruction is executed to return from the trace exception-handling routine, trace mode is entered again. trace exception- handling is not executed at the end of the rte instruction. trace mode is not entered in interrupt control mode 0, regardless of the state of the t bit. (4) interrupt exception handling and trap instruction exception handling when interrupt or trap-instruction exception handling begins, the cpu references the stack pointer (er7) and pushes the program counter and other control registers onto the stack. next, the cpu alters the settings of the interrupt mask bits in the control registers. then the cpu fetches a start address (vector) from the exception vector table and program execution starts from that start address. figure 2.16 shows the stack after exception handling ends.
section 2 cpu rev. 3.00 jan 11, 2005 page 61 of 1220 rej09b0186-0300o (c) interrupt control mode 0 (d) interrupt control mode 2 ccr pc (24 bits) sp ccr pc (24 bits) sp exr reserved * 1 (a) interrupt control mode 0 (b) interrupt control mode 2 ccr ccr * 1 pc (16 bits) sp ccr ccr * 1 pc (16 bits) sp exr reserved * 1 normal mode * 2 advanced mode notes: 1. ignored when returning. 2. not available in the h8s/2643 group. figure 2.16 stack structure after exception handling (examples)
section 2 cpu rev. 3.00 jan 11, 2005 page 62 of 1220 rej09b0186-0300o 2.8.4 program execution state in this state the cpu executes program instructions in sequence. 2.8.5 bus-released state this is a state in which the bus has been released in response to a bus request from a bus master other than the cpu. while the bus is released, the cpu halts operations. bus masters other than the cpu are dma controller (dmac) and data transfer controller (dtc). for further details, refer to section 7, bus controller. 2.8.6 power-down state the power-down state includes both modes in which the cpu stops operating and modes in which the cpu does not stop. there are five modes in which the cpu stops operating: sleep mode, software standby mode, hardware standby mode, subsleep mode, and watch mode. there are also three other power-down modes: medium-speed mode, module stop mode, and subactive mode. in medium-speed mode the cpu and other bus masters operate on a medium-speed clock. module stop mode permits halting of the operation of individual m odules, other than the cpu. subactive mode, subsleep mode, and watch mode are power-down states using subclock input. for details, refer to section 24, power-down modes. (1) sleep mode a transition to sleep mode is made if the sleep instruction is executed while the software standby bit (ssby) in the standby control register (sbycr) is cleared to 0. in sleep mode, cpu operations stop immediately after execution of the sleep instruction. the contents of cpu registers are retained. (2) software standby mode a transition to software standby mode is made if the sleep instruction is executed while the ssby bit in sbycr is set to 1. in software standby mode, the cpu and clock halt and all mcu operations stop. as long as a specified voltage is supplied, the contents of cpu registers and on- chip ram are retained. the i/o ports also remain in their existing states.
section 2 cpu rev. 3.00 jan 11, 2005 page 63 of 1220 rej09b0186-0300o (3) hardware standby mode a transition to hardware standby mode is made when the stby pin goes low. in hardware standby mode, the cpu and clock halt and all mcu operations stop. the on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip ram contents are retained. 2.9 basic timing 2.9.1 overview the h8s/2600 cpu is driven by a system clock, denoted by the symbol . the period from one rising edge of to the next is referred to as a "state." the memory cycle or bus cycle consists of one, two, or three states. different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 on-chip memory (rom, ram) on-chip memory is accessed in one state. the data bus is 16 bits wide, permitting both byte and word transfer instruction. figure 2.17 shows the on-chip memory access cycle. figure 2.18 shows the pin states. internal address bus internal read signal internal data bus internal write signal internal data bus bus cycle t 1 address read data write data read access write access figure 2.17 on-chip memory access cycle
section 2 cpu rev. 3.00 jan 11, 2005 page 64 of 1220 rej09b0186-0300o bus cycle t 1 unchanged address bus as rd hwr , lwr data bus high high high hi g h-impedance state figure 2.18 pin states during on-chip memory access
section 2 cpu rev. 3.00 jan 11, 2005 page 65 of 1220 rej09b0186-0300o 2.9.3 on-chip supporting module access timing the on-chip supporting modules are accessed in two states. the data bus is either 8 bits or 16 bits wide, depending on the particular internal i/o register being accessed. figure 2.19 shows the access t iming for the on-chip supporting m odules. figure 2.20 shows the pin states. bus cycle t 1 t 2 address read data write data internal read signal internal data bus internal write signal internal data bus read access write access internal address bus figure 2.19 on-chip supporting module access cycle
section 2 cpu rev. 3.00 jan 11, 2005 page 66 of 1220 rej09b0186-0300o bus cycle t 1 t 2 unchanged address bus as rd hwr , lwr data bus high high high high-impedance state figure 2.20 pin states during on-chip supporting module access 2.9.4 external address space access timing the external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. in three-state access, wait states can be inserted. for further details, refer to section 7, bus controller. 2.10 usage note 2.10.1 tas instruction only register er0, er1, er4, or er5 should be used when using the tas instruction. the tas instruction is not generated by the renesas h8s and h8/300 series c/c++ compilers. if the tas instruction is used as a user-defined intrinsic function, ensure that only register er0, er1, er4, or er5 is used.
section 2 cpu rev. 3.00 jan 11, 2005 page 67 of 1220 rej09b0186-0300o 2.10.2 stm/ldm instruction with the stm or ldm instruction, the er7 register is used as the stack pointer, and thus cannot be used as a register that allows save (stm) or restore (ldm) operation. with a single stm or ldm instruction, two to four registers can be saved or restored. the available registers are as follows: for two registers: er0 and er1, er2 and er3, or er4 and er5 for three registers: er0 to er2, or er4 to er6 for four registers: er0 to er3 for the renesas h8s or h8/300 series c/c++ compiler, the stm/ldm instruction including er7 is not created. 2.10.3 bit manipulation instructions the bset, bclr, bnot, bst, and bist instructions are used to read data in byte-wise, operate the data in bit-wise, and write the result of the bit-wise operation in bit-wise again. therefore, special care is necessary to use these instructions for the registers and the ports that include write- only bit. the bclr instruction can be used to clear to 0 the flags in the internal i/o registers. in this time, if it is obvious that the flag has been set to 1 in the interrupt handler, there is no need to read the flag beforehand.
section 2 cpu rev. 3.00 jan 11, 2005 page 68 of 1220 rej09b0186-0300o
section 3 mcu operating modes rev. 3.00 jan 11, 2005 page 69 of 1220 rej09b0186-0300o section 3 mcu operating modes 3.1 overview 3.1.1 operating mode selection the h8s/2643 group has four operating modes (modes 4 to 7). these modes enable selection of the cpu operating mode, enabling/disabling of on-chip rom, and the initial bus width setting, by setting the mode pins (md2 to md0). table 3.1 lists the mcu operating modes. table 3.1 mcu operating mode selection mcu cpu external data bus operating mode md2 md1 md0 operating mode description on-chip rom initial width max. width 0 * 000? ? ? ? 1 * 1? 2 * 10 3 * 1 4 1 0 0 advanced on-chip rom disabled, expanded mode disabled 16 bits 16 bits 5 1 8 bits 16 bits 610 on-chip rom enabled, expanded mode enabled 8 bits 16 bits 7 1 single-chip mode ? note: * not available in the h8s/2643 group. the cpu?s architecture allows for 4 gbytes of address space, but the h8s/2643 group actually accesses a maximum of 16 mbytes. modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. the external expansion modes allow switching between 8-bit and 16-bit bus modes. after program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. if 16-bit access is selected for any one area, 16-bit bus mode is set; if 8- bit access is selected for all areas, 8-bit bus mode is set.
section 3 mcu operating modes rev. 3.00 jan 11, 2005 page 70 of 1220 rej09b0186-0300o note that the functions of each pin depend on the operating mode. the h8s/2643 group can be used only in modes 4 to 7. this means that the mode pins must be set to select one of these modes. do not change the inputs at the mode pins during operation. 3.1.2 register configuration the h8s/2643 group has a mode control register (mdcr) that indicates the inputs at the mode pins (md2 to md0), and a system control register (syscr) that controls the operation of the h8s/2643 group. table 3.2 summarizes these registers. table 3.2 mcu registers name abbreviation r/w initial value address * mode control register mdcr r/w undetermined h'fde7 system control register syscr r/w h'01 h'fde5 pin function control register pfcr r/w h'0d/h'00 h'fdeb note: * lower 16 bits of the address. 3.2 register descriptions 3.2.1 mode control register (mdcr) 7 ? 1 r/w 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 ? 0 ? 0 mds0 ? * r 2 mds2 ? * r 1 mds1 ? * r note: * determined b y pins md2 to md0. bit initial value r/w : : : mdcr is an 8-bit register that indicates the current operating mode of the h8s/2643 group. bit 7?reserved: only 1 should be written to this bit. bits 6 to 3?reserved: these bits always read as 0 and cannot be modified. bits 2 to 0?mode select 2 to 0 (mds2 to mds0): these bits indicate the input levels at pins md2 to md0 (the current operating mode). bits mds2 to mds0 correspond to md2 to md0. mds2 to mds0 are read-only bits-they cannot be written to. the mode pin (md2 to md0) input
section 3 mcu operating modes rev. 3.00 jan 11, 2005 page 71 of 1220 rej09b0186-0300o levels are latched into these bits when mdcr is read. these latches are cancelled by a power-on reset, but maintained by a manual reset. 3.2.2 system control register (syscr) 7 macs 0 r/w 6 ? 0 ? 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 mrese 0 r/w 1 ? 0 ? bit initial value r/w : : : syscr is an 8-bit readable-writable register that selects saturating or non-saturating calculation for the mac instruction, selects the interrupt control mode, selects the detected edge for nmi, enables or disenables mres pin input, and enables or disenables on-chip ram. syscr is initialized to h'01 by a power-on reset and in hardware standby mode. macs, intm1, intm0, nmieg, and rame bits are initialized in manual reset mode, but the mrese bit is not initialized. syscr is not initialized in software standby mode. bit 7?mac saturation (macs): selects either saturating or non-saturating calculation for the mac instruction. bit 7 macs description 0 non-saturating calculation for mac instruction (initial value ) 1 saturating calculation for mac instruction bit 6?reserved: this bit always read as 0 and cannot be modified. bits 5 and 4?interrupt control mode 1 and 0 (intm1, intm0): these bits select the control mode of the interrupt controller. for details of the interrupt control modes, see section 5.4.1, interrupt control modes and interrupt operation. bit 5 bit 4 interrupt intm1 intm0 control mode description 0 0 0 control of interrupts by i bit (initial value ) 1 ? setting prohibited 1 0 2 control of interrupts by i2 to i0 bits and ipr 1 ? setting prohibited
section 3 mcu operating modes rev. 3.00 jan 11, 2005 page 72 of 1220 rej09b0186-0300o bit 3?nmi edge select (nmieg): selects the valid edge of the nmi interrupt input. bit 3 nmieg description 0 an interrupt is requested at the falling edge of nmi input (initial value ) 1 an interrupt is requested at the rising edge of nmi input bit 2?manual reset selection bit (mrese): enables or disenables manual reset input. it is possible to set the p74/tm02/ mres pin to the manual reset input ( mres ). table 3.3 shows the relationship between the mres pin power-on reset and manual reset. bit 2 mrese description 0 disenables manual reset. possible to use p74/tm02/ mres pin as p74/tm02 input pin. (initial value ) 1 enables manual reset. possible to use p74/tm02/ mres pin as mres input pin. table 3.3 relationship between power-on reset and manual reset pin res mres reset type 0 * power-on reset (initial state ) 1 0 manual reset 1 1 operation state * : don ? t care bit 1?reserved: this bit always read as 0 and cannot be modified. bit 0?ram enable (rame): enables or disables the on-chip ram. the rame bit is initialized when the reset status is released. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value ) note: when the dtc is used, the rame bit must be set to 1.
section 3 mcu operating modes rev. 3.00 jan 11, 2005 page 73 of 1220 rej09b0186-0300o 3.2.3 pin function control register (pfcr) 7 css07 0 r/w 6 css36 0 r/w 5 buzze 0 r/w 4 lcass 0 r/w 3 ae3 1/0 r/w 0 ae0 1/0 r/w 2 ae2 1/0 r/w 1 ae1 0 r/w bit initial value r/w : : : pfcr is an 8-bit readable-writable register that carries out cs selection control for pg4 and pg1 pins, lcas selection control for pf2 and pf6 pins, and address output control during extension modes with rom. pfcr is initialized by h'0d/h'00 by a power-on reset or a hardware standby mode. the immediately previous state is maintained in manual reset or software sta ndby mode. bit 7? cs0 / cs7 select (css07): selects the cs output content for pg4 pin. in modes 4 to 6, the selected cs is output by setting the corresponding ddr to 1. bit 7 css07 description 0 select cs0 (initial value ) 1 select cs7 bit 6? cs3 / cs6 select (css36): selects the cs output content for pg1 pin. in modes 4 to 6, the selected cs is output by setting the corresponding ddr to 1. bit 6 css36 description 0 select cs3 (initial value ) 1 select cs
section 3 mcu operating modes rev. 3.00 jan 11, 2005 page 74 of 1220 rej09b0186-0300o bit 5?buzz output enable (buzze): disenables/enables buzz output of pf1 pin. input clock of wdt1 selected by pss, cks2 to cks0 bits is output as a buzz signal. bit 5 buzze description 0 functions as pf1 input pin (initial value ) 1 functions as buzz output pin bit 4?lcas output pin selection bit (lcass): selects the lcas signal output pin. bit 4 lcass description 0 outputs lcas signal from pf2 (initial value ) 1 outputs lcas signal from pf6 bits 3 to 0?address output enable 3 to 0 (ae3 to ae0): these bits select enabling or disabling of address outputs a8 to a23 in romless expanded mode and modes with rom. when a pin is enabled for address output, the address is output regardless of the corresponding ddr setting. when a pin is disabled for address output, it becomes an output port when the corresponding ddr bit is set to 1.
section 3 mcu operating modes rev. 3.00 jan 11, 2005 page 75 of 1220 rej09b0186-0300o bit 3 bit 2 bit 1 bit 0 ae3 ae2 ae1 ae0 description 0 0 0 0 a8 to a23 address output disabled (initial value * ) 1 a8 address output enabled; a9 to a23 address output disabled 10 a8, a9 address output enabled; a10 to a23 address output disabled 1 a8 to a10 address output enabled; a11 to a23 address output disabled 1 0 0 a8 to a11 address output enabled; a12 to a23 address output disabled 1 a8 to a12 address output enabled; a13 to a23 address output disabled 1 0 a8 to a13 address output enabled; a14 to a23 address output disabled 1 a8 to a14 address output enabled; a15 to a23 address output disabled 1000 a8 to a15 address output enabled; a16 to a23 address output disabled 1 a8 to a16 address output enabled; a17 to a23 address output disabled 1 0 a8 to a17 address output enabled; a18 to a23 address output disabled 1 a8 to a18 address output enabled; a19 to a23 address output disabled 1 0 0 a8 to a19 address output enabled; a20 to a23 address output disabled 1 a8 to a20 address output enabled; a21 to a23 address output disabled (initial value * ) 10 a8 to a21 address output enabled; a22, a23 address output disabled 1 a8 to a23 address output enabled note: * in expanded mode with rom, bits ae3 to ae0 are initialized to b'0000. in romless expanded mode, bits ae3 to ae0 are initialized to b'1101. address pins a0 to a7 are made address outputs by setting the corresponding ddr bits to 1.
section 3 mcu operating modes rev. 3.00 jan 11, 2005 page 76 of 1220 rej09b0186-0300o 3.3 operating mode descriptions 3.3.1 mode 4 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is disabled. ports a, b, and c, function as an address bus, ports d and e function as a data bus, and part of port f carries bus control signals. the initial bus mode after a reset is 16 bits, with 16-bit access to all areas. however, note that if 8- bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. 3.3.2 mode 5 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is disabled. ports a, b, and c, function as an address bus, ports d and e function as a data bus, and part of port f carries bus control signals. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. however, note that if 16- bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port e becomes a data bus. 3.3.3 mode 6 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is enabled. ports a, b, and c, function as input port pins immediately after a reset. address output can be performed by setting the corresponding ddr (data direction register) bits to 1. port d function as a data bus, and part of port f carries data bus signals. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. however, note that if 16- bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port e becomes a data bus. 3.3.4 mode 7 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is enabled, but external addresses cannot be accessed. all i/o ports are available for use as input-output ports.
section 3 mcu operating modes rev. 3.00 jan 11, 2005 page 77 of 1220 rej09b0186-0300o 3.4 pin functions in each operating mode the pin functions of ports a to g vary depending on the operating mode. table 3.3 shows their functions in each operating mode. table 3.3 pin functions in each mode port mode 4 mode 5 mode 6 mode 7 port a pa7 to pa5 p * /a p * /a p * /a p pa4 to pa0 p/a * p/a * p * /a p port b p/a * p/a * p * /a p port c aap * /a p port d dddp port e p/d * p * /d p * /d p port f pf7 p/c * p/c * p/c * p * /c pf6 to pf4cccp pf3 p/c * p * /c p * /c pf2 to pf0 p * /c p * /c p * /c port g pg4 c c p * /c p pg3 to pg0 p * /c p * /c p * /c legend: p: i/o port a: address bus output d: data bus i/o c: control signals, clock i/o * : after reset 3.5 address map in each operating mode an address map of the h8s/2643 is shown in figure 3.1, an address map of the h8s/2642 in figure 3.2, and an address map of the h8s/2641 in figure 3.3. the address space is 16 mbytes in modes 4 to 7 (advanced mode). the address space is divided into eight areas for modes 4 to 7. for details, see section 7, bus controller.
section 3 mcu operating modes rev. 3.00 jan 11, 2005 page 78 of 1220 rej09b0186-0300o h'000000 h'ffb000 h'ffefc0 h'fff800 h'040000 h'000000 h'03ffff h'000000 h'ffefbf external address space on-chip ram * 1 on-chip ram * 1 external address space external address space internal i/o registers on-chip ram * 1 external address space internal i/o registers on-chip rom external address space on-chip rom on-chip ram internal i/o registers * 2 internal i/o registers * 2 internal i/o registers * 2 internal i/o registers notes: h'ffffff h'ffff40 h'ffff60 h'ffffc0 h'ffb000 h'ffb000 h'ffefc0 h'fff800 h'ffff40 h'ffff60 h'ffffc0 h'ffff60 h'ffffc0 on-chip ram * 1 on-chip ram external address space h'ffffff h'ffffff h'fff800 h'ffff3f 1. external addresses can be accessed by clearing th rame bit in syscr to 0. 2. area h'fff800 to h'fffdab is reserved, and must not be accessed. modes 4 and 5 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) figure 3.1 memory map in each operating mode in the h8s/2643
section 3 mcu operating modes rev. 3.00 jan 11, 2005 page 79 of 1220 rej09b0186-0300o modes 4 and 5 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) h'000000 h'ffb000 h'ffb000 h'ffc000 h'ffefc0 h'fff800 h'040000 h'02ffff h'030000 h'000000 h'000000 h'ffefbf external address space on-chip ram * 1 reserved area reserved area on-chip ram * 1 external address space internal i/o registers * 2 internal i/o registers * 2 internal i/o registers * 2 external address space internal i/o registers on-chip ram * 1 external address space internal i/o registers on-chip rom external address space on-chip rom on-chip ram internal i/o registers h'ffffff h'ffff40 h'ffff60 h'ffffc0 h'ffc000 h'ffc000 h'ffefc0 h'fff800 h'ffff40 h'ffff60 h'ffffc0 h'ffff60 h'ffffc0 on-chip ram * 1 on-chip ram external address space h'ffffff h'ffffff h'fff800 h'ffff3f reserved area notes: 1. external addresses can be accessed by clearing th rame bit in syscr to 0. 2. area h'fff800 to h'fffdab is reserved, and must not be accessed. figure 3.2 memory map in each operating mode in the h8s/2642
section 3 mcu operating modes rev. 3.00 jan 11, 2005 page 80 of 1220 rej09b0186-0300o modes 4 and 5 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) h'000000 h'ffb000 h'ffb000 h'ffd000 h'ffefc0 h'fff800 h'040000 h'01ffff h'020000 h'000000 h'000000 h'ffefbf external address space on-chip ram * 1 reserved area reserved area on-chip ram * 1 external address space internal i/o registers * 2 external address space internal i/o registers on-chip ram * 1 external address space internal i/o registers on-chip rom external address space on-chip rom on-chip ram internal i/o registers * 2 internal i/o registers h'ffffff h'ffff40 h'ffff60 h'ffffc0 h'ffd000 h'ffd000 h'ffefc0 h'fff800 h'ffff40 h'ffff60 h'ffffc0 h'ffff60 h'ffffc0 on-chip ram * 1 on-chip ram external address space internal i/o registers * 2 h'ffffff h'ffffff h'fff800 h'ffff3f reserved area notes: 1. external addresses can be accessed by clearing th rame bit in syscr to 0. 2. area h'fff800 to h'fffdab is reserved, and must not be accessed. figure 3.3 memory map in each operating mode in the h8s/2641
section 4 exception handling rev. 3.00 jan 11, 2005 page 81 of 1220 rej09b0186-0300o section 4 exception handling 4.1 overview 4.1.1 exception handling types and priority as table 4.1 indicates, exception handling may be caused by a reset, direct transition, trap instruction, or interrupt. exception handling is prioritized as shown in table 4.1. if two or more exceptions occur simultaneously, they are accepted and processed in order of priority. trap instruction exceptions are accepted at all times, in the program execution state. exception handling sources, the stack structure, and the operation of the cpu vary depending on the interrupt control mode set by the intm0 and intm1 bits of syscr. table 4.1 exception types and priority priority exception type start of exception handling high reset starts immediately after a low-to-high transition at the res pin or mres pin, or when the watchdog overflows. the cpu enters the power-on reset state when the res pin is low, and the manual reset state when the mres pin is low. trace * 1 starts when execution of the current instruction or exception handling ends, if the trace (t) bit is set to 1 direct transition starts when a direct transition occurs due to execution of a sleep instruction. interrupt starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued * 2 low trap instruction (trapa) * 3 started by execution of a trap instruction (trapa) notes: 1. traces are enabled only in interrupt control mode 2. trace exception handling is not executed after execution of an rte instruction. 2. interrupt detection is not performed on completion of andc, orc, xorc, or ldc instruction execution, or on completion of reset exception handling. 3. trap instruction exception handling requests are accepted at all times in program execution state.
section 4 exception handling rev. 3.00 jan 11, 2005 page 82 of 1220 rej09b0186-0300o 4.1.2 exception handling operation exceptions originate from various sources. trap instructions and interrupts are handled as follows: 1. the program counter (pc), condition code register (ccr), and extended register (exr) are pushed onto the stack. 2. the interrupt mask bits are updated. the t bit is cleared to 0. 3. a vector address corresponding to the exception source is generated, and program execution starts from that address. for a reset exception, steps 2 and 3 above are carried out. 4.1.3 exception vector table the exception sources are classified as shown in figure 4.1. different vector addresses are assigned to different exception sources. table 4.2 lists the exception sources and their vector addresses. exception sources reset trace interrupts trap instruction power-on reset manual reset external interrupts: nmi, irq7 to irq0 internal interrupts: 72 interrupt sources in on-chip supporting modules figure 4.1 exception sources
section 4 exception handling rev. 3.00 jan 11, 2005 page 83 of 1220 rej09b0186-0300o table 4.2 exception vector table vector address * 1 exception source vector number advanced mode power-on reset 0 h'0000 to h'0003 manual reset * 3 1 h'0004 to h'0007 reserved for system use 2 h'0008 to h'000b 3 h'000c to h'000f 4 h'0010 to h'0013 trace 5 h'0014 to h'0017 direct transition * 3 6 h'0018 to h'001b external interrupt nmi 7 h'001c to h'001f trap instruction (4 sources) 8 h'0020 to h'0023 9 h'0024 to h'0027 10 h'0028 to h'002b 11 h'002c to h'002f reserved for system use 12 h'0030 to h'0033 13 h'0034 to h'0037 14 h'0038 to h'003b 15 h'003c to h'003f external interrupt irq0 16 h'0040 to h'0043 irq1 17 h'0044 to h'0047 irq2 18 h'0048 to h'004b irq3 19 h'004c to h'004f irq4 20 h'0050 to h'0053 irq5 21 h'0054 to h'0057 irq6 22 h'0058 to h'005b irq7 23 h'005c to h'005f internal interrupt * 2 24 ? 127 h'0060 to h'0063 ? h'01fc to h'01ff notes: 1. lower 16 bits of the address. 2. for details of internal interrupt vectors, see section 5.3.3, interrupt exception handling vector table. 3. see section 24.11, direct transitions for details on direct transition.
section 4 exception handling rev. 3.00 jan 11, 2005 page 84 of 1220 rej09b0186-0300o 4.2 reset 4.2.1 overview a reset has the highest exception handling priority. there are two kinds of reset: a power-on reset executed via the res pin, and a manual reset executed via the mres pin. when the res or mres pin* goes low, currently executing processing is halted and the chip enters the reset state. a reset initializes the internal state of the cpu and the registers of on-chip supporting modules. immediately after a reset, interrupt control mode 0 is set. reset exception handling starts when the res or mres pin* changes from low to high. the reset state can also be entered in the event of watchdog timer overflow. for details see section 15, watchdog timer. note: * mres pin in the case of a manual reset. 4.2.2 types of reset there are two types of reset: power-on reset and manual reset. table 4.3 shows the types of reset. when turning power on, do so as a power-on reset. both power-on reset and manual reset initialize the internal state of the cpu. in a power-on reset, all of the registers of the built-in vicinity modules are initialized, while in a manual reset, the registers of the built-in vicinity models except for bus controllers and i/o ports are initialized. the states of the bus controllers and i/o ports are maintained. during a manual reset built-in vicinity modules are initialized, and ports used as input pins for built-in vicinity modules switch to the input ports controlled by ddr and dr. if using manual reset, set the mrese bit to 1 beforehand, thereby enabling manual resets. see section 3.2.2, system control register (syscr) for settings of the mrese bit. there are also power-on resets and manual resets as the two types of reset carried out by the watchdog timer.
section 4 exception handling rev. 3.00 jan 11, 2005 page 85 of 1220 rej09b0186-0300o table 4.3 types of reset conditions for transition to reset internal state type mres res cpu built-in vicinity module power-on reset * low initialization initialization manual reset low high initialization initialization except for bus controller and i/o port * : don't care 4.2.3 reset sequence this lsi enters reset state when the res pin or mres pin goes low. to ensure that this lsi is reset, hold the res pin low for at least 20 ms at power-up. to reset during operation, hold the res pin or the mres pin low for at least 20 states. when the res pin or the mres pin goes high after being held low for the necessary time, this lsi starts reset exception handling as follows. 1. the internal state of the cpu and the registers of the on-chip supporting modules are initialized, the t bit is cleared to 0 in exr, and the i bit is set to 1 in exr and ccr. 2. the reset exception handling vector address is read and transferred to the pc, and program execution starts from the address indicated by the pc. figures 4.2 and 4.3 show examples of the reset sequence.
section 4 exception handling rev. 3.00 jan 11, 2005 page 86 of 1220 rej09b0186-0300o res , mres address bus rd hwr , lwr d15 to d0 (1) (3) high (2) (4) (5) (6) * * * vector fetch internal processing prefetch of first program instruction (1) (3) reset exception handling vector address (when power-on reset, (1) = h'000000 * , (3) = h'000002; when manual reset, (1)= h'000004, (3)= h'000006) (2) (4) start address (contents of reset exception handling vector address) (5) start address ((5) = (2) (4)) (6) first program instruction note: * three pro g ram wait states are inserted. figure 4.2 reset sequence (modes 4 and 5)
section 4 exception handling rev. 3.00 jan 11, 2005 page 87 of 1220 rej09b0186-0300o res , mres internal address bus internal read signal internal write signal internal data bus vector fetch (1) (3) (5) high internal processing prefetch of first program instruction (2) (4) (1) (3) reset exception handling vector address (when power-on reset, (1) = h'000000, (3) = h'000002) (2) (4) start address (contents of reset exception handling vector address) (5) start address ((5) = (2) (4)) (6) first program instruction (6) figure 4.3 reset sequence (modes 6 and 7) 4.2.4 interrupts after reset if an interrupt is accepted after a reset but before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immediately after a reset. since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.l #xx: 32, sp). 4.2.5 state of on-chip supporting modules after reset release after reset release, mstpcra to mstpcrc are initialized to h'3f, h'ff, and h'ff, respectively, and all modules except the dmac and dtc, enter module stop mode. consequently, on-chip supporting module registers cannot be read or written to. register reading and writing is enabled when module stop mode is exited.
section 4 exception handling rev. 3.00 jan 11, 2005 page 88 of 1220 rej09b0186-0300o 4.3 traces traces are enabled in interrupt control mode 2. trace mode is not activated in interrupt control mode 0, irrespective of the state of the t bit. for details of interrupt control modes, see section 5, interrupt controller. if the t bit in exr is set to 1, trace mode is activated. in trace mode, a trace exception occurs on completion of each instruction. trace mode is canceled by clearing the t bit in exr to 0. it is not affected by interrupt masking. table 4.4 shows the state of ccr and exr after execution of trace exception handling. interrupts are accepted even within the trace exception handling routine. the t bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the rte instruction, trace mode resumes. trace exception handling is not carried out after execution of the rte instruction. table 4.4 status of ccr and exr after trace exception handling ccr exr interrupt control mode i ui i2 to i0 t 0 trace exception handling cannot be used. 21??0 legend: 1: set to 1 0: cleared to 0 ?: retains value prior to execution.
section 4 exception handling rev. 3.00 jan 11, 2005 page 89 of 1220 rej09b0186-0300o 4.4 interrupts interrupt exception handling can be requested by nine external sources (nmi, irq7 to irq0) and 72 internal sources in the on-chip supporting modules. figure 4.4 classifies the interrupt sources and the number of interrupts of each type. the on-chip supporting modules that can request interrupts include the watchdog timer (wdt), 16-bit timer-pulse unit (tpu), 8-bit timer, serial communication interface (sci), data transfer controller (dtc), dma controller (dmac), pc break controller (pbc), a/d converter, and i 2 c bus interface (iic). each interrupt source has a separate vector address. nmi is the highest-priority interrupt. interrupts are controlled by the interrupt controller. the interrupt controller has two interrupt control modes and can assign interrupts other than nmi to eight priority/mask levels to enable multiplexed interrupt control. for details of interrupts, see section 5, interrupt controller. interrupts external interrupts internal interrupts nmi (1) irq7 to irq0 (8) wdt * 1 (2) refresh timer * 2 (1) tpu (26) 8-bit timer (12) sci (20) dtc (1) dmac (4) pbc (1) a/d converter (1) iic(4) (option) numbers in parentheses are the numbers of interrupt sources. 1. when the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. 2. when refresh timer is used as an interval time, an interrupt request is generated by compare match. notes: figure 4.4 interrupt sources and number of interrupts
section 4 exception handling rev. 3.00 jan 11, 2005 page 90 of 1220 rej09b0186-0300o 4.5 trap instruction trap instruction exception handling starts when a trapa instruction is executed. trap instruction exception handling can be executed at all times in the program execution state. the trapa instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. table 4.5 shows the status of ccr and exr after execution of trap instruction exception handling. table 4.5 status of ccr and exr after trap instruction exception handling ccr exr interrupt control mode i ui i2 to i0 t 01 ??? 21 ?? 0 legend: 1: set to 1 0: cleared to 0 ? : retains value prior to execution.
section 4 exception handling rev. 3.00 jan 11, 2005 page 91 of 1220 rej09b0186-0300o 4.6 stack status after exception handling figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. sp sp ccr ccr * pc (16 bits) ccr ccr * pc (16 bits) reserved * exr (a) interrupt control mode 0 (b) interrupt control mode 2 note: * i g nored on return. figure 4.5 (a) stack status after exception handling (normal modes: not available in the h8s/2643 group) sp sp ccr pc (24 bits) ccr pc (24 bits) reserved * exr (a) interrupt control mode 0 (b) interrupt control mode 2 note: * i g nored on return. figure 4.5 (b) stack status after exception handling (advanced modes)
section 4 exception handling rev. 3.00 jan 11, 2005 page 92 of 1220 rej09b0186-0300o 4.7 notes on use of the stack when accessing word data or longword data, the h8s/2643 group assumes that the lowest address bit is 0. the stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (sp, er7) should always be kept even. use the following instructions to save registers: push.w rn (or mov.w rn, @-sp) push.l ern (or mov.l ern, @-sp) use the following instructions to restore registers: pop.w rn (or mov.w @sp+, rn) pop.l ern (or mov.l @sp+, ern) setting sp to an odd value may lead to a malfunction. figure 4.6 shows an example of what happens when the sp value is odd. sp legend: note: this diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. sp sp ccr pc r1l pc h'fffefa h'fffefb h'fffefc h'fffefd h'fffeff mov.b r1l, @ ? er7 sp set to h'fffeff trap instruction executed data saved above sp contents of ccr lost ccr: condition code register pc: program counter r1l: general register r1l sp: stack pointer figure 4.6 operation when sp value is odd
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 93 of 1220 rej09b0186-0300o section 5 interrupt controller 5.1 overview 5.1.1 features the h8s/2643 group controls interrupts by means of an interrupt controller. the interrupt controller has the following features. ? two interrupt control modes ? any of two interrupt control modes can be set by means of the intm1 and intm0 bits in the system control register (syscr). ? priorities settable with ipr ? an interrupt priority register (ipr) is provided for setting interrupt priorities. eight priority levels can be set for each module for all interrupts except nmi. ? nmi is assigned the highest priority level of 8, and can be accepted at all times. ? independent vector addresses ? all interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. ? nine external interrupts ? nmi is the highest-priority interrupt, and is accepted at all times. rising edge or falling edge can be selected for nmi. ? falling edge, rising edge, or both edge detection, or level sensing, can be selected for irq7 to irq0. ? dtc and dmac control ? dtc and dmac activation is performed by means of interrupts.
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 94 of 1220 rej09b0186-0300o 5.1.2 block diagram a block diagram of the interrupt controller is shown in figure 5.1. syscr nmi input irq input internal interrupt request swdtend to tei4 intm1, intm0 nmieg nmi input unit irq input unit isr iscr ier ipr interrupt controller priority determination interrupt request vector number i i2 to i0 ccr exr cpu iscr: ier: isr: ipr: syscr: irq sense control register irq enable register irq status register interrupt priority register system control register legend: figure 5.1 block diagram of interrupt controller
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 95 of 1220 rej09b0186-0300o 5.1.3 pin configuration table 5.1 summarizes the pins of the interrupt controller. table 5.1 interrupt controller pins name symbol i/o function nonmaskable interrupt nmi input nonmaskable external interrupt; rising or falling edge can be selected external interrupt requests 7 to 0 irq7 to irq0 input maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected 5.1.4 register configuration table 5.2 summarizes the registers of the interrupt controller. table 5.2 interrupt controller registers name abbreviation r/w initial value address * 1 system control register syscr r/w h'01 h'fde5 irq sense control register h iscrh r/w h'00 h'fe12 irq sense control register l iscrl r/w h'00 h'fe13 irq enable register ier r/w h'00 h'fe14 irq status register isr r/(w) * 2 h'00 h'fe15 interrupt priority register a ipra r/w h'77 h'fec0 interrupt priority register b iprb r/w h'77 h'fec1 interrupt priority register c iprc r/w h'77 h'fec2 interrupt priority register d iprd r/w h'77 h'fec3 interrupt priority register e ipre r/w h'77 h'fec4 interrupt priority register f iprf r/w h'77 h'fec5 interrupt priority register g iprg r/w h'77 h'fec6 interrupt priority register h iprh r/w h'77 h'fec7 interrupt priority register i ipri r/w h'77 h'fec8 interrupt priority register j iprj r/w h'77 h'fec9 interrupt priority register k iprk r/w h'77 h'feca interrupt priority register l iprl r/w h'77 h'fecb interrupt priority register o ipro r/w h'77 h'fece notes: 1. lower 16 bits of the address. 2. can only be written with 0 for flag clearing.
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 96 of 1220 rej09b0186-0300o 5.2 register descriptions 5.2.1 system control register (syscr) 7 macs 0 r/w 6 ? 0 ? 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 mrese 0 r/w 1 ? 0 ? bit initial value r/w : : : syscr is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for nmi. only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, system control register (syscr). syscr is initialized to h'01 by a power-on reset, manual reset, and in hardware standby mode. syscr is not initialized in software standby mode. bits 5 and 4?interrupt control mode 1 and 0 (intm1, intm0): these bits select one of two interrupt control modes for the interrupt controller. bit 5 bit 4 interrupt intm1 intm0 control mode description 0 0 0 interrupts are controlled by i bit (initial value ) 1 ? setting prohibited 1 0 2 interrupts are controlled by bits i2 to i0, and ipr 1 ? setting prohibited bit 3?nmi edge select (nmieg): selects the input edge for the nmi pin. bit 3 nmieg description 0 interrupt request generated at falling edge of nmi input (initial value ) 1 interrupt request generated at rising edge of nmi input
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 97 of 1220 rej09b0186-0300o 5.2.2 interrupt priority registers a to l, o (ipra to iprl, ipro) 7 ? 0 ? 6 ipr6 1 r/w 5 ipr5 1 r/w 4 ipr4 1 r/w 3 ? 0 ? 0 ipr0 1 r/w 2 ipr2 1 r/w 1 ipr1 1 r/w bit initial value r/w : : : the ipr registers are thirteen 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than nmi. the correspondence between ipr settings and interrupt sources is shown in table 5.3. the ipr registers set a priority (level 7 to 0) for each interrupt source other than nmi. the ipr registers are initialized to h'77 by a reset and in hardware standby mode. bits 7 and 3?reserved: these bits are always read as 0 and cannot be modified. table 5.3 correspondence between interrupt sources and ipr settings bits register 6 to 4 2 to 0 ipra irq0 irq1 iprb irq2 irq3 irq4 irq5 iprc irq6 irq7 dtc iprd watchdog timer 0 refresh timer ipre pc break a/d converter, watchdog timer 1 iprf tpu channel 0 tpu channel 1 iprg tpu channel 2 tpu channel 3 iprh tpu channel 4 tpu channel 5 ipri 8-bit timer channel 0 8-bit timer channel 1 iprj dmac sci channel 0 iprk sci channel 1 sci channel 2 iprl 8-bit timer 2, 3 iic (option) ipro sci channel 3 sci channel 4
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 98 of 1220 rej09b0186-0300o as shown in table 5.3, multiple interrupts are assigned to one ipr. setting a value in the range from h'0 to h'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. the lowest priority level, level 0, is assigned by setting h'0, and the highest priority level, level 7, by setting h'7. when interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the ipr registers is selected. this interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (i2 to i0) in the extend register (exr) in the cpu, and if the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to the cpu. 5.2.3 irq enable register (ier) 7 irq7e 0 r/w 6 irq6e 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 0 irq0e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w bit initial value r/w : : : ier is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests irq7 to irq0. ier is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 0?irq7 to irq0 enable (irq7e to irq0e): these bits select whether irq7 to irq0 are enabled or disabled. bit n irqne description 0 irqn interrupts disabled (initial value ) 1 irqn interrupts enabled (n = 7 to 0)
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 99 of 1220 rej09b0186-0300o 5.2.4 irq sense control registers h and l (iscrh, iscrl) iscrh 15 irq7scb 0 r/w 14 irq7sca 0 r/w 13 irq6scb 0 r/w 12 irq6sca 0 r/w 11 irq5scb 0 r/w 8 irq4sca 0 r/w 10 irq5sca 0 r/w 9 irq4scb 0 r/w bit initial value r/w : : : iscrl 7 irq3scb 0 r/w 6 irq3sca 0 r/w 5 irq2scb 0 r/w 4 irq2sca 0 r/w 3 irq1scb 0 r/w 0 irq0sca 0 r/w 2 irq1sca 0 r/w 1 irq0scb 0 r/w bit initial value r/w : : : the iscr registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins irq7 to irq0 . the iscr registers are initialized to h'0000 by a reset and in hardware standby mode. they are not initialized in software standby mode. bits 15 to 0: irq7 sense control a and b (irq7sca, irq7scb) to irq0 sense control a and b (irq0sca, irq0scb) bits 15 to 0 irq7scb to irq0scb irq7sca to irq0sca description 0 0 interrupt request generated at irq7 to irq0 input low level (initial value ) 1 interrupt request generated at falling edge of irq7 to irq0 input 1 0 interrupt request generated at rising edge of irq7 to irq0 input 1 interrupt request generated at both falling and rising edges of irq7 to irq0 input
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 100 of 1220 rej09b0186-0300o 5.2.5 irq status register (isr) 7 irq7f 0 r/(w) * 6 irq6f 0 r/(w) * 5 irq5f 0 r/(w) * 4 irq4f 0 r/(w) * 3 irq3f 0 r/(w) * 0 irq0f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * bit initial value r/w note: * onl y 0 can be written, to clear the fla g . : : : isr is an 8-bit readable/writable register that indicates the status of irq7 to irq0 interrupt requests. isr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 0?irq7 to irq0 flags (irq7f to irq0f): these bits indicate the status of irq7 to irq0 interrupt requests. bit n irqnf description 0 [clearing conditions] (initial value ) ? cleared by reading irqnf flag when irqnf = 1, then writing 0 to irqnf flag ? when interrupt exception handling is executed when low-level detection is set (irqnscb = irqnsca = 0) and irqn input is high ? when irqn interrupt exception handling is executed when falling, rising, or both- edge detection is set (irqnscb = 1 or irqnsca = 1) ? when the dtc is activated by an irqn interrupt, and the disel bit in mrb of the dtc is cleared to 0 1 [setting conditions] ? when irqn input goes low when low-level detection is set (irqnscb = irqnsca = 0) ? when a falling edge occurs in irqn input when falling edge detection is set (irqnscb = 0, irqnsca = 1) ? when a rising edge occurs in irqn input when rising edge detection is set (irqnscb = 1, irqnsca = 0) ? when a falling or rising edge occurs in irqn input when both-edge detection is set (irqnscb = irqnsca = 1) (n = 5 to 0)
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 101 of 1220 rej09b0186-0300o 5.3 interrupt sources interrupt sources comprise external interrupts (nmi and irq7 to irq0) and internal interrupts (72 sources). 5.3.1 external interrupts there are nine external interrupts: nmi and irq7 to irq0. of these, nmi and irq7 to irq0 can be used to restore the h8s/2643 group from software standby mode. nmi interrupt: nmi is the highest-priority interrupt, and is always accepted by the cpu regardless of the interrupt control mode or the status of the cpu interrupt mask bits. the nmieg bit in syscr can be used to select whether an interrupt is requested at a rising edge or a falling edge on the nmi pin. the vector number for nmi interrupt exception handling is 7. irq7 to irq0 interrupts: interrupts irq7 to irq0 are requested by an input signal at pins irq7 to irq0 . interrupts irq5 to irq0 have the following features: ? using iscr, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins irq7 to irq0 . ? enabling or disabling of interrupt requests irq7 to irq0 can be selected with ier. ? the interrupt priority level can be set with ipr. ? the status of interrupt requests irq7 to irq0 is indicated in isr. isr flags can be cleared to 0 by software. a block diagram of interrupts irq7 to irq0 is shown in figure 5.2.
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 102 of 1220 rej09b0186-0300o irqn interrupt request irqne irqnf s r q clear signal edge/level detection circuit irqnsca, irqnscb irqn input note: n = 7 to 0 figure 5.2 block diagram of interrupts irq7 to irq0 figure 5.3 shows the t iming of setting irqnf. irqn input pin irqnf figure 5.3 timing of setting irqnf the vector numbers for irq7 to irq0 interrupt exception handling are 23 to 16. detection of irq7 to irq0 interrupts does not depend on whether the relevant pin has been set for input or output. however, when a pin is used as an external interrupt input pin, do not clear the corresponding ddr to 0 and use the pin as an i/o pin for another function. 5.3.2 internal interrupts there are 72 sources for internal interrupts from on-chip supporting modules. ? for each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. if both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller.
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 103 of 1220 rej09b0186-0300o ? the interrupt priority level can be set by means of ipr. ? the dmac and dtc can be activated by a tpu, 8-bit timer, sci, or other interrupt request. when the dmac and dtc are activated by an interrupt, the interrupt control mode and interrupt mask bits are not affected. 5.3.3 interrupt exception handling vector table table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. for default priorities, the lower the vector number, the higher the priority. priorities among modules can be set by means of the ipr. the situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5.4.
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 104 of 1220 rej09b0186-0300o table 5.4 interrupt sources, vector addresses, and interrupt priorities vector address * interrupt source origin of interrupt source vector number advanced mode ipr priority nmi external 7 h'001c high irq0 pin 16 h'0040 ipra6 to 4 irq1 17 h'0044 ipra2 to 0 irq2 irq3 18 19 h'0048 h'004c iprb6 to 4 irq4 irq5 20 21 h'0050 h'0054 iprb2 to 0 irq6 irq7 22 23 h'0058 h'005c iprc6 to 4 swdtend (software activation interrupt end) dtc 24 h'0060 iprc2 to 0 wovi0 (interval timer) watchdog timer 0 25 h'0064 iprd6 to 4 cmi refresh timer 26 h'0068 iprd2 to 0 pc break pc break 27 h'006c ipre6 to 4 adi (a/d conversion end) a/d 28 h'0070 ipre2 to 0 wovi1 (interval timer) watchdog timer 1 29 h'0074 reserved ? 30 31 h'0078 h'007c tgi0a (tgr0a input capture/compare match) tgi0b (tgr0b input capture/compare match) tgi0c (tgr0c input capture/compare match) tgi0d (tgr0d input capture/compare match) tci0v (overflow 0) tpu channel 0 32 33 34 35 36 h'0080 h'0084 h'0088 h'008c h'0090 iprf6 to 4 reserved ? 37 38 39 h'0094 h'0098 h'009c low
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 105 of 1220 rej09b0186-0300o vector address * interrupt source origin of interrupt source vector number advanced mode ipr priority tgi1a (tgr1a input capture/compare match) tgi1b (tgr1b input capture/compare match) tci1v (overflow 1) tci1u (underflow 1) tpu channel 1 40 41 42 43 h'00a0 h'00a4 h'00a8 h'00ac iprf2 to 0 high tgi2a (tgr2a input capture/compare match) tgi2b (tgr2b input capture/compare match) tci2v (overflow 2) tci2u (underflow 2) tpu channel 2 44 45 46 47 h'00b0 h'00b4 h'00b8 h'00bc iprg6 to 4 tgi3a (tgr3a input capture/compare match) tgi3b (tgr3b input capture/compare match) tgi3c (tgr3c input capture/compare match) tgi3d (tgr3d input capture/compare match) tci3v (overflow 3) tpu channel 3 48 49 50 51 52 h'00c0 h'00c4 h'00c8 h'00cc h'00d0 iprg2 to 0 reserved ? 53 54 55 h'00d4 h'00d8 h'00dc tgi4a (tgr4a input capture/compare match) tgi4b (tgr4b input capture/compare match) tci4v (overflow 4) tci4u (underflow 4) tpu channel 4 56 57 58 59 h'00e0 h'00e4 h'00e8 h'00ec iprh6 to 4 tgi5a (tgr5a input capture/compare match) tgi5b (tgr5b input capture/compare match) tci5v (overflow 5) tci5u (underflow 5) tpu channel 5 60 61 62 63 h'00f0 h'00f4 h'00f8 h'00fc iprh2 to 0 low
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 106 of 1220 rej09b0186-0300o vector address * interrupt source origin of interrupt source vector number advanced mode ipr priority cmia0 (compare match a0) cmib0 (compare match b0) ovi0 (overflow 0) 8-bit timer channel 0 64 65 66 h'0100 h'0104 h'0108 ipri6 to 4 high reserved ? 67 h'010c cmia1 (compare match a1) cmib1 (compare match b1) ovi1 (overflow 1) 8-bit timer channel 1 68 69 70 h'0110 h'0114 h'0118 ipri2 to 0 reserved ? 71 h'011c ded0a (channel 0/channel 0a transfer end) dend0b (channel 0b transfer end) dend1a (channel 1/channel 1a transfer end) dend1b (channel 1b transfer end) dmac 72 73 74 75 h'0120 h'0124 h'0128 h'012c iprj6 to 4 reserved ? 76 77 78 79 h'0130 h'0134 h'0138 h'013c eri0 (receive error 0) rxi0 (reception completed 0) txi0 (transmit data empty 0) tei0 (transmission end 0) sci channel 0 80 81 82 83 h'0140 h'0144 h'0148 h'014c iprj2 to 0 eri1 (receive error 1) rxi1 (reception completed 1) txi1 (transmit data empty 1) tei1 (transmission end 1) sci channel 1 84 85 86 87 h'0150 h'0154 h'0158 h'015c iprk6 to 4 eri2 (receive error 2) rxi2 (reception completed 2) txi2 (transmit data empty 2) tei2 (transmission end 2) sci channel 2 88 89 90 91 h'0160 h'0164 h'0168 h'016c iprk2 to 0 low
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 107 of 1220 rej09b0186-0300o vector address * interrupt source origin of interrupt source vector number advanced mode ipr priority cmia0 (compare match a2) cmib0 (compare match b2) ovi0 (overflow 2) 8 bit timer channel 2 92 93 94 h'0170 h'0174 h'0178 iprl6 to 4 high reserved ? 95 h'017c cmia1 (compare match a3) cmib1 (compare match b3) ovi1 (overflow 3) 8 bit timer channel 3 96 97 98 h'0180 h'0184 h'0188 reserved ? 99 h'018c iici0 (1 byte transmission/reception completed) ddcsw1 (format switch) iic channel 0 (optional) 100 101 h'0190 h'0194 iprl2 to 0 iici1 (1 byte transmission/reception completed) reserved iic channel 1 (optional) 102 103 h'0198 h'019c reserved ? 104 105 106 107 h'01a0 h'01a4 h'01a8 h'01ac iprm6 to 4 reserved ? 108 109 110 111 h'01b0 h'01b4 h'01b8 h'01bc iprm2 to 0 reserved ? 112 113 114 115 h'01c0 h'01c4 h'01c8 h'01cc iprn6 to 4 reserved ? 116 117 118 119 h'01d0 h'01d4 h'01d8 h'01dc iprn2 to 0 eri3 (reception error 3) rxi3 (reception completed 3) txi3 (transmission data empty 3) tei3 (transmission end 3) sci channel 3 120 121 122 123 h'01e0 h'01e4 h'01e8 h'01ec ipro6 to 4 eri4 (reception error 4) rxi4 (reception completed 4) txi4 (transmission data empty 4) tei4 (transmission end 4) sci channel 4 124 125 126 127 h'01f0 h'01f4 h'01f8 h'01fc ipro2 to 0 low note: * lower 16 bits of the start address.
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 108 of 1220 rej09b0186-0300o 5.4 interrupt operation 5.4.1 interrupt control modes and interrupt operation interrupt operations in the h8s/2643 group differ depending on the interrupt control mode. nmi interrupts are accepted at all times except in the reset state and the hardware standby state. in the case of irq interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. clearing an enable bit to 0 disables the corresponding interrupt request. interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. table 5.5 shows the interrupt control modes. the interrupt controller performs interrupt control according to the interrupt control mode set by the intm1 and intm0 bits in syscr, the priorities set in ipr, and the masking state indicated by the i and ui bits in the cpu?s ccr, and bits i2 to i0 in exr. table 5.5 interrupt control modes interrupt syscr priority setting interrupt control mode intm1 intm0 registers mask bits description 000 ? i interrupt mask control is performed by the i bit. ? 1 ?? setting prohibited 2 1 0 ipr i2 to i0 8-level interrupt mask control is performed by bits i2 to i0. 8 priority levels can be set with ipr. ? 1 ?? setting prohibited
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 109 of 1220 rej09b0186-0300o figure 5.4 shows a block diagram of the priority decision circuit. interrupt acceptance control 8-level mask control default priority determination vector numbe r interrupt control mode 2 ipr interrupt source i2 to i0 interrupt control mode 0 i figure 5.4 block diagram of interrupt control operation (1) interrupt acceptance control in interrupt control mode 0, interrupt acceptance is controlled by the i bit in ccr. table 5.6 shows the interrupts selected in each interrupt control mode. table 5.6 interrupts selected in each interrupt control mode (1) interrupt mask bits interrupt control mode i selected interrupts 0 0 all interrupts 1 nmi interrupts 2 * all interrupts * : don't care
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 110 of 1220 rej09b0186-0300o (2) 8-level control in interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (ipr). the interrupt source selected is the interrupt with the highest priority level, and whose priority level set in ipr is higher than the mask level. table 5.7 interrupts selected in each interrupt control mode (2) interrupt control mode selected interrupts 0 all interrupts 2 highest-priority-level (ipr) interrupt whose priority level is greater than the mask level (ipr > i2 to i0). (3) default priority determination when an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. if the same value is set for ipr, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. interrupt sources with a lower priority than the accepted interrupt source are held pending.
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 111 of 1220 rej09b0186-0300o table 5.8 shows operations and control signal functions in each interrupt control mode. table 5.8 operations and control signal functions in each interrupt control mode setting interrupt acceptance control 8-level control interrupt control mode intm1 intm0 i i2 to i0 ipr default priority determination t (trace) 000 o im x ? ? * 2 o ? 210 x ? * 1 o im pr o t legend: o : interrupt operation control performed. x: no operation (all interrupts enabled). im: used as interrupt mask bit pr: sets priority. ? : not used. notes: 1. set to 1 when interrupt is accepted. 2. keep the initial setting. 5.4.2 interrupt control mode 0 enabling and disabling of irq interrupts and on-chip supporting module interrupts can be set by means of the i bit in the cpu?s ccr. interrupts are enabled when the i bit is cleared to 0, and disabled when set to 1. figure 5.5 shows a flowchart of the interrupt acceptance operation in this case. [1] if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] the i bit is then referenced. if the i bit is cleared to 0, the interrupt request is accepted. if the i bit is set to 1, only an nmi interrupt is accepted, and other interrupt requests are held pending. [3] interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. [4] when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] the pc and ccr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] next, the i bit in ccr is set to 1. this masks all interrupts except nmi. [7] a vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address.
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 112 of 1220 rej09b0186-0300o program execution status interrupt generated? nmi irq0 irq1 tei4 i = 0 save pc and ccr i 1 read vector address branch to interrupt handling routine yes no yes yes yes no no no yes yes no hold pending figure 5.5 flowchart of procedure up to interrupt acceptance in interrupt control mode 0
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 113 of 1220 rej09b0186-0300o 5.4.3 interrupt control mode 2 eight-level masking is implemented for irq interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits i2 to i0 of exr in the cpu with ipr. figure 5.6 shows a flowchart of the interrupt acceptance operation in this case. [1] if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] when interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in ipr is selected, and lower-priority interrupt requests are held pending. if a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.4 is selected. [3] next, the priority of the selected interrupt request is compared with the interrupt mask level set in exr. an interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. [4] when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] the pc, ccr, and exr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] the t bit in exr is cleared to 0. the interrupt mask level is rewritten with the priority level of the accepted interrupt. if the accepted interrupt is nmi, the interrupt mask level is set to h'7. [7] a vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address.
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 114 of 1220 rej09b0186-0300o yes program execution status interrupt generated? nmi level 6 interrupt? mask level 5 or below? level 7 interrupt? mask level 6 or below? save pc, ccr, and exr clear t bit to 0 update mask level read vector address branch to interrupt handling routine hold pending level 1 interrupt? mask level 0? yes yes no yes yes yes no yes yes no no no no no no figure 5.6 flowchart of procedure up to interrupt acceptance in interrupt control mode 2
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 115 of 1220 rej09b0186-0300o 5.4.4 interrupt exception handling sequence figure 5.7 shows the interrupt exception handling sequence. the example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. (14) (12) (10) (8) (6) (4) (2) (1) (5) (7) (9) (11) (13) interrupt service routine instruction prefetch internal operation vector fetch stack instruction prefetch internal operation interrupt acceptance interrupt level determination wait for end of instruction interrupt request signal internal a ddress bus internal read signal internal w rite signal internal d ata us (3) (1) (2) (4) (3) (5) (7) instruction prefetch address (not executed. this is the contents of the saved pc, the return address) instruction code (not executed) instruction prefetch address (not executed) sp-2 sp-4 saved pc and saved ccr vector address interrupt handling routine start address (vector address contents) interrupt handling routine start address ((13) = (10) (12)) first instruction of interrupt handling routine (6) (8) (9) (11) (10) (12) (13) (14) figure 5.7 interrupt exception handling
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 116 of 1220 rej09b0186-0300o 5.4.5 interrupt response times the h8s/2643 group is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip rom and the stack area in on-chip ram, enabling high- speed processing. table 5.9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. the execution status symbols used in table 5.9 are explained in table 5.10. table 5.9 interrupt response times normal mode * 5 advanced mode no. execution status intm1 = 0 intm1 = 1 intm1 = 0 intm1 = 1 1 interrupt priority determination * 1 33 33 2 number of wait states until executing instruction ends * 2 1 to (19 + 2 s i ) 1 to (19 + 2 s i ) 1 to (19 + 2 s i ) 1 to (19 + 2 s i ) 3 pc, ccr, exr stack save 2 s k 3 s k 2 s k 3 s k 4 vector fetch s i s i 2 s i 2 s i 5 instruction fetch * 3 2 s i 2 s i 2 s i 2 s i 6 internal processing * 4 22 22 total (using on-chip memory) 11 to 31 12 to 32 12 to 32 13 to 33 notes: 1. two states in case of internal interrupt. 2. refers to mulxs and di vxs instructions. 3. prefetch after interrupt acceptance and interrupt handling routine prefetch. 4. internal processing after interrupt acceptance and internal processing after vector fetch. 5. not available in the h8s/2643 group.
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 117 of 1220 rej09b0186-0300o table 5.10 number of states in interrupt handling routine execution statuses object of access external device 8 bit bus 16 bit bus symbol internal memory 2-state access 3-state access 2-state access 3-state access instruction fetch s i 1 4 6 + 2m 2 3 + m branch address read s j stack manipulation s k legend: m: number of wait states in an external device access. 5.5 usage notes 5.5.1 contention between interrupt generation and disabling when an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. in other words, when an interrupt enable bit is cleared to 0 by an instruction such as bclr or mov, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instructi on, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. however, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. the same also applies when an interrupt source flag is cleared to 0. figure 5.8 shows an example in which the cmiea bit in the tmr?s tcr register is cleared to 0.
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 118 of 1220 rej09b0186-0300o internal address bus internal write signal cmiea cmfa cmia interrupt signal tcr write cycle by cpu cmia exception handling tcr address figure 5.8 contention between interrupt generation and disabling the above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 5.5.2 instructions that disable interrupts instructions that disable interrupts are ldc, andc, orc, and xorc. after any of these instructions is executed, all interrupts including nmi are disabled and the next instruction is always executed. when the i bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.5.3 times when interrupts are disabled there are times when interrupt acceptance is disabled by the interrupt controller. the interrupt controller disables interrupt acceptance for a 3-state period after the cpu has updated the mask level with an ldc, andc, orc, or xorc instruction.
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 119 of 1220 rej09b0186-0300o 5.5.4 interrupts during execution of eepmov instruction interrupt operation differs between the eepmov.b instruction and the eepmov.w instruction. with the eepmov.b instruction, an interrupt request (including nmi) issued during the transfer is not accepted until the move is completed. with the eepmov.w instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. the pc value saved on the stack in this case is the address of the next instruction. therefore, if an interrupt is generated during execution of an eepmov.w instruction, the following coding should be used. l1: eepmov.w mov.w r4,r4 bne l1 5.5.5 irq interrupt when operating by clock input, acceptance of input to an irq is synchronized with the clock. in software standby mode, the input is accepted asynchronously. for details on the input conditions, see section 25.3.2, control signal t iming. 5.5.6 nmi interrupt usage notes the nmi interrupt is part of the exception processing performed cooperatively by the lsi?s internal interrupt controller and the cpu when the system is operating normally under the specified electrical conditions. no operations, including nmi interrupts, are guaranteed when operation is not normal (runaway status) due to software problems or abnormal input to the lsi?s pins. in such cases, the lsi may be restored to the normal program execution state by applying an external reset.
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 120 of 1220 rej09b0186-0300o 5.6 dtc and dmac activation by interrupt 5.6.1 overview the dtc and dmac can be activated by an interrupt. in this case, the following options are available: ? interrupt request to cpu ? activation request to dtc ? activation request to dmac ? selection of a number of the above for details of interrupt requests that can be used with to activate the dtc and dmac, see section 9, data transfer controller and section 8, dma controller. 5.6.2 block diagram figure 5.9 shows a block diagram of the dtc interrupt controller. dmac selection circuit dtcer dtvecr control logic determination of priority cpu dtc select signal irq interrupt on-chip supporting module disenable signal clear signal clear signal interrupt controller i, i2 to i0 interrupt source clear signal interrupt request dtc activation request vector number cpu interrupt request vector number swdte clear signal clear signal figure 5.9 interrupt control for dtc and dmac
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 121 of 1220 rej09b0186-0300o 5.6.3 operation the interrupt controller has three main functions in dtc and dmac control. (1) selection of interrupt source dmac inputs activation factor directly to each channel. the activation factors for each channel of dmac are selected by dtf3 to dtf0 bits of dmacr. the dta bit of dmabcr can be used to select whether the selected activation factors are managed by dmac. by setting the dta bit to 1, the interrupt factor which were the activation factor for that dmac do not act as the dtc activation factor or the cpu interrupt factor. interrupt factors other than the interrupts managed by the dmac are selected as dtc activation request or cpu interrupt request by the dtcera to dtcerf of dtc and the dtce bit of dtceri. by specifying the disel bit of the dtc's mrb, it is possible to clear the dtce bit to 0 after dtc data transfer, and request a cpu interrupt. if dtc carries out the designate number of data transfers and the transfer counter reads 0, after dtc data transfer, the dtce bit is also cleared to 0, and a cpu interrupt requested. (2) determination of priority the dtc activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. see sections 8.6, interrupts and 9.3.3, dtc vector table for the respective priority. (3) operation order if the same interrupt is selected as a dtc activation source and a cpu interrupt source, the dtc data transfer is performed first, followed by cpu interrupt exception handling. if the same interrupt is selected as the dmac activation factor and as the dtc activation factor or cpu interrupt factor, these operate independently. they operate in accordance with the respective operating states and bus priorities. table 5.11 shows the interrupt factor clear control and selection of interrupt factors by specification of the dta bit of dmac's dmabcr, dtc's dtcera to dtcerf, dtceri's dtce bits, and the disel bit of dtc's mrb.
section 5 interrupt controller rev. 3.00 jan 11, 2005 page 122 of 1220 rej09b0186-0300o table 5.11 interrupt source selection and clearing control settings dmac dtc interrupt source selection/clearing control dta dtce disel dmac dtc cpu 00 * o ? 10 o ? 1 oo ? 1 ** ? legend: ? : the relevant interrupt is used. interrupt source clearing is performed. (the cpu should clear the source flag in the interrupt handling routine.) o : the relevant interrupt is used. the interrupt source is not cleared. : the relevant bit cannot be used. * : don ? t care (4) notes on use sci and a/d converter interrupt sources are cleared when the dmac or dtc reads or writes to the prescribed register, and are not dependent upon the dta, dtce, and disel bits.
section 6 pc break controller (pbc) rev. 3.00 jan 11, 2005 page 123 of 1220 rej09b0186-0300o section 6 pc break controller (pbc) 6.1 overview the pc break controller (pbc) provides functions that simplify program debugging. using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. four break conditions can be set in the pbc: instruction fetch, data read, data write, and data read/write. 6.1.1 features the pc break controller has the following features. ? two break channels (a and b) ? the following can be set as break compare conditions ? 24 address bits bit masking possible ? bus cycle instruction fetch data access: data read, data write, data read/write ? bus master either cpu or cpu/dtc can be selected ? the timing of pc break exception handling after the occurrence of a break condition is as follows ? immediately before execution of the instruction fetched at the set address (instruction fetch) ? immediately after execution of the instruction that accesses data at the set address (data access) ? module stop mode can be set ? the initial setting is for pbc operation to be halted. register access is enabled by clearing module stop mode.
section 6 pc break controller (pbc) rev. 3.00 jan 11, 2005 page 124 of 1220 rej09b0186-0300o 6.1.2 block diagram figure 6.1 shows a block diagram of the pc break controller. output control mask control output control match signal pc break interrupt match signal mask control bara bcra barb bcrb comparator control logic comparator control logic internal address access status figure 6.1 block diagram of pc break controller
section 6 pc break controller (pbc) rev. 3.00 jan 11, 2005 page 125 of 1220 rej09b0186-0300o 6.1.3 register configuration table 6.1 shows the pc break controller registers. table 6.1 pc break controller registers initial value name abbreviation r/w power-on reset manual reset address * 1 break address register a bara r/w h'xx000000 retained h'fe00 break address register b barb r/w h'xx000000 retained h'fe04 break control register a bcra r/(w) * 2 h'00 retained h'fe08 break control register b bcrb r/(w) * 2 h'00 retained h'fe09 module stop control register c mstpcrc r/w h'ff retained h'fdea notes: 1. lower 16 bits of the address. 2. only 0 can be written, for flag clearing. 6.2 register descriptions 6.2.1 break address register a (bara) bit : initial value : r/w : ? ? 31 unde- fined ? ? 24 unde- fined r/w baa 23 23 0 r/w baa 22 22 0 r/w baa 21 21 0 r/w baa 20 20 0 r/w baa 19 19 0 r/w baa 18 18 0 r/w baa 17 17 0 r/w baa 16 16 0 r/w 0 baa 7 7 r/w 0 baa 6 6 r/w 0 baa 5 5 r/w 0 baa 4 4 r/w 0 baa 3 3 r/w 0 baa 2 2 r/w 0 baa 1 1 r/w 0 baa 0 0 bara is a 32-bit readable/writable register that specifies the channel a break address. baa23 to baa0 are initialized to h'000000 by a power-on reset and in hardware standby mode. bits 31 to 24?reserved: these bits return an undefined value if read, and cannot be modified. bits 23 to 0?break address a23 to a0 (baa23 to baa0): these bits hold the channel a pc break address.
section 6 pc break controller (pbc) rev. 3.00 jan 11, 2005 page 126 of 1220 rej09b0186-0300o 6.2.2 break address register b (barb) barb is the channel b break address register. the bit configuration is the same as for bara. 6.2.3 break control register a (bcra) bit : initial value : r/w : note: * only 0 can be written, for flag clearing. r/(w) * 0 cmfa 7 r/w 0 cda 6 r/w 0 bamra2 5 r/w 0 bamra1 4 r/w 0 bamra0 3 r/w 0 csela1 2 r/w 0 csela0 1 r/w 0 biea 0 bcra is an 8-bit readable/writable register that controls channel a pc breaks. bcra (1) selects the break condition bus master, (2) specifies bits subject to address comparison masking, and (3) specifies whether the break condition is applied to an instruction fetch or a data access. it also contains a condition match flag. bcra is initialized to h'00 by a power-on reset and in hardware standby mode. bit 7?condition match flag a (cmfa): set to 1 when a break condition set for channel a is satisfied. this flag is not cleared to 0. bit 7 cmfa description 0 [clearing condition] ? when 0 is written to cmfa after reading cmfa = 1 (initial value ) 1 [setting condition] ? when a condition set for channel a is satisfied bit 6?cpu cycle/dtc cycle select a (cda): selects the channel a break condition bus master. bit 6 cda description 0 pc break is performed when cpu is bus master (initial value) 1 pc break is performed when cpu or dtc is bus master
section 6 pc break controller (pbc) rev. 3.00 jan 11, 2005 page 127 of 1220 rej09b0186-0300o bits 5 to 3?break address mask register a2 to a0 (bamra2 to bamra0): these bits specify which bits of the break address (baa23 to baa0) set in bara are to be masked. bit 5 bit 4 bit 3 bamra2 bamra1 bamra0 description 000all bara bits are unmasked and included in break conditions (initial value) 1 baa0 (lowest bit) is masked, and not included in break conditions 10 baa1 to 0 (lower 2 bits) are masked, and not included in break conditions 1 baa2 to 0 (lower 3 bits) are masked, and not included in break conditions 1 0 0 baa3 to 0 (lower 4 bits) are masked, and not included in break conditions 1 baa7 to 0 (lower 8 bits) are masked, and not included in break conditions 1 0 baa11 to 0 (lower 12 bits) are masked, and not included in break conditions 1 baa15 to 0 (lower 16 bits) are masked, and not included in break conditions bits 2 and 1?break condition select a (csela1, csela0): these bits selection an instruction fetch, data read, data write, or data read/write cycle as the channel a break condition. bit 2 bit 1 csela1 csela0 description 0 0 instruction fetch is used as break condition (initial value) 1 data read cycle is used as break condition 1 0 data write cycle is used as break condition 1 data read/write cycle is used as break condition bit 0?break interrupt enable a (biea): enables or disables channel a pc break interrupts. bit 0 biea description 0 pc break interrupts are disabled (initial value) 1 pc break interrupts are enabled
section 6 pc break controller (pbc) rev. 3.00 jan 11, 2005 page 128 of 1220 rej09b0186-0300o 6.2.4 break control register b (bcrb) bcrb is the channel b break control register. the bit configuration is the same as for bcra. 6.2.5 module stop control register c (mstpcrc) 7 mstpc7 1 r/w bit : initial value : r/w : 6 mstpc6 1 r/w 5 mstpc5 1 r/w 4 mstpc4 1 r/w 3 mstpc3 1 r/w 2 mstpc2 1 r/w 1 mstpc1 1 r/w 0 mstpc0 1 r/w mstpcrc is an 8-bit readable/writable register that performs module stop mode control. when the mstpc4 bit is set to 1, pc break controller operation is stopped at the end of the bus cycle, and module stop mode is entered. register read/write accesses are not possible in module stop mode. for details, see section 24.5, module stop mode. mstpcrc is initialized to h'ff by a power on reset and in hardware standby mode. it is not initialized by a manual reset and in software standby mode. bit 4?module stop (mstpc4): specifies the pc break controller module stop mode. bit 4 mstpc4 description 0 pc break controller module stop mode is cleared 1 pc break controller module stop mode is set (initial value) 6.3 operation the operation flow from break condition setting to pc break interrupt exception handling is shown in sections 6.3.1, pc break interrupt due to instruction fetch, and 6.3.2, pc break interrupt due to data access, taking the example of channel a. 6.3.1 pc break interrupt due to instruction fetch (1) initial settings ? set the break address in bara. for a pc break caused by an instruction fetch, set the address of the first instruction byte as the break address.
section 6 pc break controller (pbc) rev. 3.00 jan 11, 2005 page 129 of 1220 rej09b0186-0300o ? set the break conditions in bcra. bcra bit 6 (cda): with a pc break caused by an instruction fetch, the bus master must be the cpu. set 0 to select the cpu. bcra bits 5 to 3 (bama2 to 0): set the address bits to be masked. bcra bits 2 and 1 (csela1 and 0): set 00 to specify an instruction fetch as the break condition. bcra bit 0 (biea): set to 1 to enable break interrupts. (2) satisfaction of break condition ? when the instruction at the set address is fetched, a pc break request is generated immediately before execution of the fetched instructi on, and the condition match flag (cmfa) is set. (3) interrupt handling ? after priority determination by the interrupt controller, pc break interrupt exception handling is started. 6.3.2 pc break interrupt due to data access (1) initial settings ? set the break address in bara. for a pc break caused by a data access, set the target rom, ram, i/o, or external address space address as the break address. stack operations and branch address reads are included in data accesses. ? set the break conditions in bcra. bcra bit 6 (cda): select the bus master. bcra bits 5 to 3 (bama2 to 0): set the address bits to be masked. bcra bits 2 and 1 (csela1 and 0): set 01, 10, or 11 to specify data access as the break condition. bcra bit 0 (biea): set to 1 to enable break interrupts. (2) satisfaction of break condition ? after execution of the instruction that performs a data access on the set address, a pc break request is generated and the condition match flag (cmfa) is set. (3) interrupt handling ? after priority determination by the interrupt controller, pc break interrupt exception handling is started.
section 6 pc break controller (pbc) rev. 3.00 jan 11, 2005 page 130 of 1220 rej09b0186-0300o 6.3.3 notes on pc break interrupt handling (1) the pc break interrupt is shared by channels a and b. the channel from which the request was issued must be determined by the interrupt handler. (2) the cmfa and cmfb flags are not cleared to 0, so 0 must be written to cmfa or cmfb after first reading the flag while it is set to 1. if the flag is left set to 1, another interrupt will be requested after interrupt handling ends. (3) a pc break interrupt generated when the dtc is the bus master is accepted after the bus has been transferred to the cpu by the bus controller. 6.3.4 operation in transitions to power-down modes the operation when a pc break interrupt is set for an instruction fetch at the address after a sleep instruction is shown below. (1) when the sleep instruction causes a transition from high-speed (medium-speed) mode to sleep mode, or from subactive mode to subsleep mode after execution of the sleep instruction, a transition is not made to sleep mode or subsleep mode, and pc break interrupt handling is executed. after execution of pc break interrupt handling, the instruction at the address after the sleep instruction is executed (figure 6.2 (a)). (2) when the sleep instruction causes a transition from high-speed (medium-speed) mode to subactive mode after execution of the sleep instruction, a transition is made to subactive mode via direct transition exception handling. after the transition, pc break interrupt handling is executed, then the instruction at the address after the sleep instruction is executed (figure 6.2 (b)). (3) when the sleep instruction causes a transition from subactive mode to high-speed (medium- speed) mode after execution of the sleep instruction, and following the clock osc illation settling time, a transition is made to high-speed (medium-speed) mode via direct transition exception handling. after the transition, pc break interrupt handling is executed, then the instruction at the address after the sleep instruction is executed (figure 6.2 (c)). (4) when the sleep instruction causes a transition to software standby mode or watch mode after execution of the sleep instruction, a transition is made to the respective mode, and pc break interrupt handling is not executed. however, the cmfa or cmfb flag is set (figure 6.2 (d)).
section 6 pc break controller (pbc) rev. 3.00 jan 11, 2005 page 131 of 1220 rej09b0186-0300o sleep instruction execution high-speed (medium-speed) mode sleep instruction execution subactive mode system clock subclock direct transition exception handling pc break exception handling execution of instruction after sleep instruction subclock system clock, oscillation settling time sleep instruction execution transition to respective mode direct transition exception handling pc break exception handling execution of instruction after sleep instruction pc break exception handling execution of instruction after sleep instruction (a) ( b )( c ) (d) sleep instruction execution figure 6.2 operation in power-down mode transitions 6.3.5 pc break operation in continuous data transfer if a pc break interrupt is generated when the following operations are being performed, exception handling is executed on completion of the specified transfer. (1) when a pc break interrupt is generated at the transfer address of an eepmov.b instruction pc break exception handling is executed after all data transfers have been completed and the eepmov.b instruction has ended. (2) when a pc break interrupt is generated at a dtc transfer address pc break exception handling is executed after the dtc has completed the specified number of data transfers, or after data for which the disel bit is set to 1 has been transferred. 6.3.6 when instruction execution is delayed by one state caution is required in the following cases, as instruction execution is one state later than usual. (1) when the pbc is enabled (i.e. when the break interrupt enable bit is set to 1), execution of a one-word branch instruction (bcc d:8, bsr, jsr, jmp, trapa, rte, or rts) located in on- chip rom or ram is always delayed by one state. (2) when break interruption by instruction fetch is set, the set address indicates on-chip rom or ram space, and that address is used for data access, the instruction that executes the data access is one state later than in normal operation.
section 6 pc break controller (pbc) rev. 3.00 jan 11, 2005 page 132 of 1220 rej09b0186-0300o (3) when break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction has one of the addressing modes shown below, and that address indicates on-chip rom or ram, and that address is used for data access, the instruction will be one state later than in normal operation. @ern, @(d:16,ern), @(d:32,ern), @-ern/ern+, @aa:8, @aa:24, @aa:32, @(d:8,pc), @(d:16,pc), @@aa:8 (4) when break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction is nop or sleep, or has #xx,rn as its addressing mode, and that instruction is located in on-chip rom or ram, the instruction will be one state later than in normal operation. 6.3.7 additional notes (1) when a pc break is set for an instruction fetch at the address following a bsr, jsr, jmp, trapa, rte, or rts instruction even if the instruction at the address following a bsr, jsr, jmp, trapa, rte, or rts instruction is fetched, it is not executed, and so a pc break interrupt is not generated by the instruction fetch at the next address. (2) when the i bit is set by an ldc, andc, orc, or xorc instruction a pc break interrupt becomes valid two states after the end of the executing instruction. if a pc break interrupt is set for the instruction following one of these instructions, since interrupts, including nmi, are disabled for a 3-state period in the case of ldc, andc, orc, and xorc, the next instruction is always executed. for details, see section 5, interrupt controller. (3) when a pc break is set for an instruction fetch at the address following a bcc instruction a pc break interrupt is generated if the instruction at the next address is executed in accordance with the branch condition, but is not generated if the instruction at the next address is not executed. (4) when a pc break is set for an instruction fetch at the branch destination address of a bcc instruction a pc break interrupt is generated if the instruction at the branch destination is executed in accordance with the branch condition, but is not generated if the instruction at the branch destination is not executed.
section 7 bus controller rev. 3.00 jan 11, 2005 page 133 of 1220 rej09b0186-0300o section 7 bus controller 7.1 overview the h8s/2643 group has a built-in bus controller (bsc) that manages the external address space divided into eight areas. the bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. the bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the cpu, dma controller (dmac), and data transfer controller (dtc). 7.1.1 features the features of the bus controller are listed below. ? manages external address space in area units ? manages the external space as 8 areas of 2-mbytes ? bus specifications can be set independently for each area ? dram/burst rom interface can be set ? basic bus interface ? chip selects ( cs0 to cs7 ) can be output for areas 0 to 7 ? 8-bit access or 16-bit access can be selected for each area ? 2-state access or 3-state access can be selected for each area ? program wait states can be inserted for each area ? dram interface ? dram interface can be set for areas 2 to 5 (in advanced mode) ? multiplexed output of row and column addresses (8/9/10-bit) ? 2 cas method ? burst operation (in high-speed mode) ? insertion of t p cycle to secure ras precharge time ? selection of cas-before-ras refresh and self refresh ? burst rom interface ? burst rom interface can be set for area 0 ? choice of 1- or 2-state burst access
section 7 bus controller rev. 3.00 jan 11, 2005 page 134 of 1220 rej09b0186-0300o ? idle cycle insertion ? an idle cycle can be inserted in case of an external read cycle between different areas ? an idle cycle can be inserted in case of an external write cycle immediately after an external read cycle ? write buffer functions ? external write cycle and internal access can be executed in parallel ? dmac single-address mode and internal access can be executed in parallel ? bus arbitration function ? includes a bus arbiter that arbitrates bus mastership among the cpu, dmac and dtc ? other features ? refresh counter (refresh timer) can be used as an interval timer ? external bus release function
section 7 bus controller rev. 3.00 jan 11, 2005 page 135 of 1220 rej09b0186-0300o 7.1.2 block diagram figure 7.1 shows a block diagram of the bus controller. area decoder bus controller abwcr astcr bcrh bcrl internal address bus external bus control signals cs0 to cs7 legend: abwcr: bus width control register astcr: access state control register bcrh: bus control register h bcrl: bus control register l wcrh: wait control register h wcrl: wait control register l mcr: dramcr: rtcnt: rtcor: memory control register dram control register refresh timer counter refresh time constand register breq back breqo internal control signals wait controller wcrh wcrl dram controller external dram control signal mcr dramcr rtcnt rtcor bus mode signal bus arbiter cpu bus request signal dtc bus request signal dmac bus request signal cpu bus acknowledge signal dtc bus acknowledge signal dmac bus acknowledge signal wait internal data bus figure 7.1 block diagram of bus controller
section 7 bus controller rev. 3.00 jan 11, 2005 page 136 of 1220 rej09b0186-0300o 7.1.3 pin configuration table 7.1 summarizes the pins of the bus controller. table 7.1 bus controller pins name symbol i/o function address strobe as output strobe signal indicating that address output on address bus is enabled. read rd output strobe signal indicating that external space is being read. high write/ write enable hwr output strobe signal indicating that external space is to be written, and upper half (d15 to d8) of data bus is enabled. low write lwr output strobe signal indicating that external space is to be written, and lower half (d7 to d0) of data bus is enabled. chip select 0 cs0 output strobe signal showing selection of area 0 chip select 1 cs1 output strobe signal showing selection of area 1 chip select 2/row address strobe 2 cs2 output strobe signal showing selection of area 2. when area 2 is allocated to dram space, this is the row address strobe signal for dram. when areas 2 to 5 are contiguous dram space, this is the row address strobe signal for dram. chip select 3/row address strobe 3 cs3 / oe output strobe signal showing selection of area 3. when area 3 is allocated to dram space, this is the row address strobe signal for dram. when only area 2 is allocated to dram space, or when areas 2 to 5 are contiguous dram space, this is output enable signal. chip select 4/row address strobe 4 cs4 output strobe signal showing selection of area 4. when area 4 is allocated to dram space, this is the row address strobe signal for dram. chip select 5/row address strobe 5 cs5 output strobe signal showing selection of area 5. when area 5 is allocated to dram space, this is the row address strobe signal for dram. chip select 6 cs6 output strobe signal showing selection of area 6. chip select 7 cs7 output strobe signal showing selection of area 7. upper column address strobe cas output 2 cas method dram upper column address strobe signal lower column strobe lcas output dram lower column address strobe signal
section 7 bus controller rev. 3.00 jan 11, 2005 page 137 of 1220 rej09b0186-0300o name symbol i/o function wait wait input wait request signal when accessing external 3-state access space. bus request breq input request signal that releases bus to external device. bus request acknowledge back output acknowledge signal indicating that bus has been released. bus request output breqo output external bus request signal used when internal bus master accesses external space when external bus is released. 7.1.4 register configuration table 7.2 summarizes the registers of the bus controller. table 7.2 bus controller registers initial value name abbreviation r/w power-on reset manual reset address * 1 bus width control register abwcr r/w h'ff/h'00 * 2 retained h'fed0 access state control register astcr r/w h'ff retained h'fed1 wait control register h wcrh r/w h'ff retained h'fed2 wait control register l wcrl r/w h'ff retained h'fed3 bus control register h bcrh r/w h'd0 retained h'fed4 bus control register l bcrl r/w h'08 retained h'fed5 pin function control register pfcr r/w h'0d/h'00 retained h'fdeb memory control register mcr r/w h'00 retained h'fed6 dram control register dramcr r/w h'00 retained h'fed7 refresh timer counter rtcnt r/w h'00 retained h'fed8 refresh time constant register rtcor r/w h'ff retained h'fed9 notes: 1. lower 16 bits of the address. 2. determined by the mcu operating mode.
section 7 bus controller rev. 3.00 jan 11, 2005 page 138 of 1220 rej09b0186-0300o 7.2 register descriptions 7.2.1 bus width control register (abwcr) 7 abw7 1 r/w 0 r/w 6 abw6 1 r/w 0 r/w 5 abw5 1 r/w 0 r/w 4 abw4 1 r/w 0 r/w 3 abw3 1 r/w 0 r/w 0 abw0 1 r/w 0 r/w 2 abw2 1 r/w 0 r/w 1 abw1 1 r/w 0 r/w bit : initial value : modes 5 to 7 mode 4 : rw initial value : : rw abwcr is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. abwcr sets the data bus width for the external memory space. the bus width for on-chip memory and internal i/o registers is fixed regardless of the settings in abwcr. in normal mode, the settings of bits abw7 to abw1 have no effect on operation. after a power-on reset and in hardware standby mode, abwcr is initialized to h'ff in modes 5 to 7, and to h'00 in mode 4. it is not initialized by a manual reset or in software standby mode. bits 7 to 0?area 7 to 0 bus width control (abw7 to abw0): these bits select whether the corresponding area is to be designated for 8-bit access or 16-bit access. bit n abwn description 0 area n is designated for 16-bit access 1 area n is designated for 8-bit access (n = 7 to 0)
section 7 bus controller rev. 3.00 jan 11, 2005 page 139 of 1220 rej09b0186-0300o 7.2.2 access state control register (astcr) 7 ast7 1 r/w 6 ast6 1 r/w 5 ast5 1 r/w 4 ast4 1 r/w 3 ast3 1 r/w 0 ast0 1 r/w 2 ast2 1 r/w 1 ast1 1 r/w bit initial value r/w : : : astcr is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. astcr sets the number of access states for the external memory space. the number of access states for on-chip memory and internal i/o registers is fixed regardless of the settings in astcr. in normal mode, the settings of bits ast7 to ast1 have no effect on operation. astcr is initialized to h'ff by a power-on reset and in hardware standby mode. it is not initialized by a manual reset or in software standby mode. bits 7 to 0?area 7 to 0 access state control (ast7 to ast0): these bits select whether the corresponding area is to be designated as a 2-state access space or a 3-state access space. wait state insertion is enabled or disabled at the same time. bit n astn description 0 area n is designated for 2-state access wait state insertion in area n external space is disabled 1 area n is designated for 3-state access (initial value ) wait state insertion in area n external space is enabled (n = 7 to 0)
section 7 bus controller rev. 3.00 jan 11, 2005 page 140 of 1220 rej09b0186-0300o 7.2.3 wait control registers h and l (wcrh, wcrl) wcrh and wcrl are 8-bit readable/writable registers that select the number of program wait states for each area. program waits are not inserted in the case of on-chip memory or internal i/o registers. wcrh and wcrl are initialized to h'ff by a power-on reset and in hardware standby mode. they are not initialized by a manual reset or in software standby mode. (1) wcrh 7 w71 1 r/w 6 w70 1 r/w 5 w61 1 r/w 4 w60 1 r/w 3 w51 1 r/w 0 w40 1 r/w 2 w50 1 r/w 1 w41 1 r/w bit initial value r/w : : : bits 7 and 6?area 7 wait control 1 and 0 (w71, w70): these bits select the number of program wait states when area 7 in external space is accessed while the ast7 bit in astcr is set to 1. bit 7 bit 6 w71 w70 description 0 0 program wait not inserted when external space area 7 is accessed 1 1 program wait state inserted when external space area 7 is accessed 1 0 2 program wait states inserted when external space area 7 is accessed 1 3 program wait states inserted when external space area 7 is accessed (initial value )
section 7 bus controller rev. 3.00 jan 11, 2005 page 141 of 1220 rej09b0186-0300o bits 5 and 4?area 6 wait control 1 and 0 (w61, w60): these bits select the number of program wait states when area 6 in external space is accessed while the ast6 bit in astcr is set to 1. bit 5 bit 4 w61 w60 description 0 0 program wait not inserted when external space area 6 is accessed 1 1 program wait state inserted when external space area 6 is accessed 1 0 2 program wait states inserted when external space area 6 is accessed 1 3 program wait states inserted when external space area 6 is accessed (initial value ) bits 3 and 2?area 5 wait control 1 and 0 (w51, w50): these bits select the number of program wait states when area 5 in external space is accessed while the ast5 bit in astcr is set to 1. bit 3 bit 2 w51 w50 description 0 0 program wait not inserted when external space area 5 is accessed 1 1 program wait state inserted when external space area 5 is accessed 1 0 2 program wait states inserted when external space area 5 is accessed 1 3 program wait states inserted when external space area 5 is accessed (initial value ) bits 1 and 0?area 4 wait control 1 and 0 (w41, w40): these bits select the number of program wait states when area 4 in external space is accessed while the ast4 bit in astcr is set to 1. bit 1 bit 0 w41 w40 description 0 0 program wait not inserted when external space area 4 is accessed 1 1 program wait state inserted when external space area 4 is accessed 1 0 2 program wait states inserted when external space area 4 is accessed 1 3 program wait states inserted when external space area 4 is accessed (initial value )
section 7 bus controller rev. 3.00 jan 11, 2005 page 142 of 1220 rej09b0186-0300o (2) wcrl 7 w31 1 r/w 6 w30 1 r/w 5 w21 1 r/w 4 w20 1 r/w 3 w11 1 r/w 0 w00 1 r/w 2 w10 1 r/w 1 w01 1 r/w bit initial value r/w : : : bits 7 and 6?area 3 wait control 1 and 0 (w31, w30): these bits select the number of program wait states when area 3 in external space is accessed while the ast3 bit in astcr is set to 1. bit 7 bit 6 w31 w30 description 0 0 program wait not inserted when external space area 3 is accessed 1 1 program wait state inserted when external space area 3 is accessed 1 0 2 program wait states inserted when external space area 3 is accessed 1 3 program wait states inserted when external space area 3 is accessed (initial value ) bits 5 and 4?area 2 wait control 1 and 0 (w21, w20): these bits select the number of program wait states when area 2 in external space is accessed while the ast2 bit in astcr is set to 1. bit 5 bit 4 w21 w20 description 0 0 program wait not inserted when external space area 2 is accessed 1 1 program wait state inserted when external space area 2 is accessed 1 0 2 program wait states inserted when external space area 2 is accessed 1 3 program wait states inserted when external space area 2 is accessed (initial value )
section 7 bus controller rev. 3.00 jan 11, 2005 page 143 of 1220 rej09b0186-0300o bits 3 and 2?area 1 wait control 1 and 0 (w11, w10): these bits select the number of program wait states when area 1 in external space is accessed while the ast1 bit in astcr is set to 1. bit 3 bit 2 w11 w10 description 0 0 program wait not inserted when external space area 1 is accessed 1 1 program wait state inserted when external space area 1 is accessed 1 0 2 program wait states inserted when external space area 1 is accessed 1 3 program wait states inserted when external space area 1 is accessed (initial value ) bits 1 and 0?area 0 wait control 1 and 0 (w01, w00): these bits select the number of program wait states when area 0 in external space is accessed while the ast0 bit in astcr is set to 1. bit 1 bit 0 w01 w00 description 0 0 program wait not inserted when external space area 0 is accessed 1 1 program wait state inserted when external space area 0 is accessed 1 0 2 program wait states inserted when external space area 0 is accessed 1 3 program wait states inserted when external space area 0 is accessed (initial value )
section 7 bus controller rev. 3.00 jan 11, 2005 page 144 of 1220 rej09b0186-0300o 7.2.4 bus control register h (bcrh) 7 icis1 1 r/w 6 icis0 1 r/w 5 brstrm 0 r/w 4 brsts1 1 r/w 3 brsts0 0 r/w 0 rmts0 0 r/w 2 rmts2 0 r/w 1 rmts1 0 r/w bit initial value r/w : : : bcrh is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. bcrh is initialized to h'd0 by a power-on reset and in hardware standby mode. it is not initialized by a manual reset or in software standby mode. bit 7?idle cycle insert 1 (icis1): selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. bit 7 icis1 description 0 idle cycle not inserted in case of successive external read cycles in different areas 1 idle cycle inserted in case of successive external read cycles in different areas (initial value ) bit 6?idle cycle insert 0 (icis0): selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed. bit 6 icis0 description 0 idle cycle not inserted in case of successive external read and external write cycles 1 idle cycle inserted in case of successive external read and external write cycles (initial value ) bit 5?burst rom enable (brstrm): selects whether area 0 is used as a burst rom interface. bit 5 brstrm description 0 area 0 is basic bus interface (initial value ) 1 area 0 is burst rom interface
section 7 bus controller rev. 3.00 jan 11, 2005 page 145 of 1220 rej09b0186-0300o bit 4?burst cycle select 1 (brsts1): selects the number of burst cycles for the burst rom interface. bit 4 brsts1 description 0 burst cycle comprises 1 state 1 burst cycle comprises 2 states (initial value ) bit 3?burst cycle select 0 (brsts0): selects the number of words that can be accessed in a burst rom interface burst access. bit 3 brsts0 description 0 max. 4 words in burst access (initial value ) 1 max. 8 words in burst access bits 2 to 0?ram type select (rmts2 to rmts0): in advanced mode, these bits select the memory interface for areas 2 to 5. when dram space is selected, the appropriate area becomes the dram interface. bit 2 bit 1 bit 0 description rmts2 rmts1 rmts0 area 5 area 4 area 3 area 2 0 0 0 normal space 1 normal space dram space 1 0 normal space dram space 1 dram space 1 1 1 contiguous dram space note: when all areas selected in dram are 8-bit space, the pf2 pin can be used as an i/o port and for breqo and wait . when contiguous ram is selected set the appropriate bus width and number of access states (the number of programmable waits) to the same values for all of areas 2 to 5. do not set other than the above combinations.
section 7 bus controller rev. 3.00 jan 11, 2005 page 146 of 1220 rej09b0186-0300o 7.2.5 bus control register l (bcrl) 7 brle 0 r/w 6 breqoe 0 r/w 5 ? 0 ? 4 oes 0 r/w 3 dds 1 r/w 0 waite 0 r/w 2 rcts 0 r/w 1 wdbe 0 r/w bit initial value r/w : : : bcrl is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of wait pin input. bcrl is initialized to h'08 by a power-on reset and in hardware standby mode. it is not initialized by a manual reset or in software standby mode. bit 7?bus release enable (brle): enables or disables external bus release. bit 7 brle description 0 external bus release is disabled. breq , back and breqo can be used as i/o ports (initial value ) 1 external bus release is enabled bit 6?breqo pin enable (breqoe): outputs a signal that requests the external bus master to drop the bus request signal ( breq ) in the external bus release state, when an internal bus master performs an external space access, or when a refresh request is generated. bit 6 breqoe description 0 breqo output disabled. breqo can be used as i/o port (initial value) 1 breqo output enabled bit 5?reserved: this bit cannot be modified and is always read as 0.
section 7 bus controller rev. 3.00 jan 11, 2005 page 147 of 1220 rej09b0186-0300o bit 4?oe select (oes): selects the cs3 pin as the oe pin. bit 4 oes description 0 uses the cs3 pin as the port or as cs3 signal output (initial value) 1 when only area 2 is set for dram, or when areas 2 to 5 are set as contiguous dram space, the cs3 pin is used as the oe pin bit 3?dack timing select (dds): when using the dram interface, this bit selects the dmac single address transfer bus timing. bit 3 dds description 0 when performing dmac single address transfers to dram, always execute full access. the dack signal is output as a low-level signal from the t r or t 1 cycle 1 burst access is also possible when performing dmac single address tranfers to dram. the dack signal is output as a low-level signal from the t c1 or t 2 cycle (initial value) bit 2?read cas timing select (rcts): selects the cas signal output timing. bit 2 rcts description 0 cas signal output timing is same when reading and writing (initial value) 1 when reading, cas signal is asserted half cycle earlier than when writing bit 1?write data buffer enable (wdbe): this bit selects whether or not to use the write buffer function in the external write cycle or the dmac single address cycle. bit 1 wdbe description 0 write data buffer function not used (initial value) 1 write data buffer function used
section 7 bus controller rev. 3.00 jan 11, 2005 page 148 of 1220 rej09b0186-0300o bit 0?wait pin enable (waite): selects enabling or disabling of wait input by the wait pin. bit 0 waite description 0 wait input by wait pin disabled. wait pin can be used as i/o port (initial value ) 1 wait input by wait pin enabled 7.2.6 pin function control register (pfcr) 7 css07 0 r/w 6 css36 0 r/w 5 buzze 0 r/w 4 lcass 0 r/w 3 ae3 1/0 r/w 0 ae0 1/0 r/w 2 ae2 1/0 r/w 1 ae1 0 r/w bit initial value r/w : : : pfcr is an 8-bit read/write register that controls the cs selection of pins pg4 and pg1, controls lcas selection of pins pf2 and pf6, and controls the address output in expanded mode with rom. pfcr is initialized to h'0d/h'00 by a power-on reset and in hardware standby mode. it retains its previous state by a manual reset or in software standby mode. bit 7? cs0 / cs7 select (css07): this bit selects the contents of cs output via the pg4 pin. in modes 4, 5, and 6, setting the corresponding ddr to 1 outputs the selected cs. bit 7 css07 description 0 selects cs0 (initial value) 1 selects cs7 bit 6? cs3 / cs6 select (css36): this bit selects the contents of cs output via the pg1 pin. in modes 4, 5, and 6, setting the corresponding ddr to 1 outputs the selected cs. bit 6 css36 description 0 selects cs3 (initial value) 1 selects cs6
section 7 bus controller rev. 3.00 jan 11, 2005 page 149 of 1220 rej09b0186-0300o bit 5?buzz output enable (buzze): this bit enables/disables buzz output via the pf1 pin. the wdt1 input clock, selected with pss and cks2 to cks0, is output as the buzz signal. see section 15.2.4, pin function control register (pfcr) for details of buzz output. bit 5 buzze description 0 functions as pf1 input pin (initial value) 1 functions as buzz output pin bit 4?lcas output pin select bit (lcass): selects output pin for lcas signal. bit 4 lcass description 0 outputs lcas signal from pf2 (initial value) 1 outputs lcas signal from pf6
section 7 bus controller rev. 3.00 jan 11, 2005 page 150 of 1220 rej09b0186-0300o bits 3 to 0?address output enable 3 to 0 (ae3 to ae0): these bits select enabling or disabling of address outputs a8 to a23 in romless expanded mode and modes with rom. when a pin is enabled for address output, the address is output regardless of the corresponding ddr setting. when a pin is disabled for address output, it becomes an output port when the corresponding ddr bit is set to 1. bit 3 bit 2 bit 1 bit 0 ae3 ae2 ae1 ae0 description 0 0 0 0 a8 to a23 address output disabled (initial value * ) 1 a8 address output enabled; a9 to a23 address output disabled 1 0 a8, a9 address output enabled; a10 to a23 address output disabled 1 a8 to a10 address output enabled; a11 to a23 address output disabled 1 0 0 a8 to a11 address output enabled; a12 to a23 address output disabled 1 a8 to a12 address output enabled; a13 to a23 address output disabled 1 0 a8 to a13 address output enabled; a14 to a23 address output disabled 1 a8 to a14 address output enabled; a15 to a23 address output disabled 1 0 0 0 a8 to a15 address output enabled; a16 to a23 address output disabled 1 a8 to a16 address output enabled; a17 to a23 address output disabled 1 0 a8 to a17 address output enabled; a18 to a23 address output disabled 1 a8 to a18 address output enabled; a19 to a23 address output disabled 1 0 0 a8 to a19 address output enabled; a20 to a23 address output disabled 1 a8 to a20 address output enabled; a21 to a23 address output disabled (initial value * ) 10 a8 to a21 address output enabled; a22, a23 address output disabled 1 a8 to a23 address output enabled note: * in expanded mode with rom, bits ae3 to ae0 are initialized to b'0000. in romless expanded mode, bits ae3 to ae0 are initialized to b'1101. address pins a0 to a7 are made address outputs by setting the corresponding ddr bits to 1.
section 7 bus controller rev. 3.00 jan 11, 2005 page 151 of 1220 rej09b0186-0300o 7.2.7 memory control register (mcr) 7 tpc 0 r/w 6 be 0 r/w 5 rcdm 0 r/w 4 cw2 0 r/w 3 mxc1 0 r/w 0 rlw0 0 r/w 2 mxc0 0 r/w 1 rlw1 0 r/w bit initial value r/w : : : the mcr is an 8-bit read/write register that, when areas 2 to 5 are set as the dram interface, controls the dram strobe method, number of precharge cycles, access mode, address multiplex shift amount, and number of wait states to be inserted when a refresh is performed. the mcr is initialized to h'00 at a power-on reset and in hardware standby mode. it is not initialized at a manual reset or in software standby mode. bit 7?tp cycle control (tpc): when accessing areas 2 to 5, allocated to dram, this bit selects whether the precharge cycle (t p ) is 1 state or 2 states. bit 7 tpc description 0 insert 1 precharge cycle (initial value) 1 insert 2 precharge cycles bit 6?burst access enable (be): this bit enables/disables burst access of areas 2 to 5, allocated as dram space. dram space burst access is in high-speed page mode. when using edo type in this case, either select oe output or ras up mode. bit 6 be description 0 burst disabled (always full access) (initial value) 1 access dram space in high-speed page mode
section 7 bus controller rev. 3.00 jan 11, 2005 page 152 of 1220 rej09b0186-0300o bit 5?ras down mode (rcdm): when areas 2 to 5 are allocated to dram space, this bit selects whether the ras signal level remains low while waiting for the next dram access (ras down mode) or the ras signal level returns to high (ras up mode), when dram access is discontinued. bit 5 rcdm description 0 dram interface: selects ras up mode (initial value) 1 dram interface: selects ras down mode bit 4?reserved (cw2): only write 0 to this bit. bits 3 and 2?multiplex shift counts 1 and 0 (mxc1, mxc0): these bits select the shift amount to the low side of the row address of the multiplexed row/column address in dram interface mode. they also select the row address to be compared in burst operation of the dram interface. bit 3 bit 2 mxc1 mxc0 description 0 0 8-bit shift (initial value) (1) 8-bit access space: target row addresses for comparison are a23 to a8 (2) 16-bit access space: target row addresses for comparison are a23 to a9 1 9-bit shift (1) 8-bit access space: target row addresses for comparison are a23 to a9 (2) 16-bit access space: target row addresses for comparison are a23 to a10 1 0 10-bit shift (1) 8-bit access space: target row addresses for comparison are a23 to a10 (2) 16-bit access space: target row addresses for comparison are a23 to a11 1 ?
section 7 bus controller rev. 3.00 jan 11, 2005 page 153 of 1220 rej09b0186-0300o bits 1 and 0?refresh cycle wait control 1 and 0 (rlw1, rlw0): these bits select the number of wait states to be inserted in the cas-before-ras refresh cycle of the dram interface. the selected number of wait states is applied to all areas set as dram space. wait input via the wait pin is disabled. bit 1 bit 0 rlw1 rlw0 description 0 0 do not insert wait state (initial value) 1 insert 1 wait state 1 0 insert 2 wait states 1 insert 3 wait states 7.2.8 dram control register (dramcr) 7 rfshe 0 r/w 6 cbrm 0 r/w 5 rmode 0 r/w 4 cmf 0 r/w 3 cmie 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value r/w : : : the dramcr is an 8-bit read/write register that selects dram refresh mode, the refresh counter clock, and sets the refresh timer control. the dramcr is initialized to h'00 at a power-on reset and in hardware standby mode. it is not initialized at a manual reset or in software standby mode. bit 7?refresh control (rfshe): this bit selects whether or not to perform refresh control. when not performing refresh control, the refresh timer can be used as an interval timer. bit 7 rfshe description 0 do not perform refresh control (initial value) 1 perform refresh control
section 7 bus controller rev. 3.00 jan 11, 2005 page 154 of 1220 rej09b0186-0300o bit 6?cbr refresh mode (cbrm): this bit selects whether cbr refresh is performed in parallel with other external access, or only cbr refresh is performed. bit 6 cbrm description 0 enables external access during cas-before-ras refresh (initial value) 1 disables external access during cas-before-ras refresh bit 5?refresh mode (rmode): this bit selects whether or not to perform a self refresh in software standby mode when performing refresh control (rfshe = 1). bit 5 rmode description 0 do not perform self-refresh in software standby mode (initial value) 1 perform self-refresh in software standby mode bit 4?compare match flag (cmf): this status flag shows a match between rtcnt and rtcor values. when performing refresh control (rfshe = 1), write 1 to cmf when writing to the dramcr. bit 4 cmf description 0 [clearing condition] ? when cmf = 1, read the cmf flag, then clear the cmf flag to 0 (initial value) 1 [setting condition] ? cmf is set when rtcnt = rtcor bit 3?compare match interrupt enable (cmie): this bit enables/disables the cmf flag interrupt request (cmi) when the dramcr cmf flag is set to 1. cmie is always 0 when performing a self-refresh. bit 3 cmie description 0 disables cmf flag interrupt requests (cmi) (initial value) 1 enables cmf flag interrupt requests (cmi)
section 7 bus controller rev. 3.00 jan 11, 2005 page 155 of 1220 rej09b0186-0300o bits 2 to 0?refresh counter clock select (cks2 to cks0): these bits select from the seven internal clocks derived by dividing the system clock ( ) to be input to rtcnt. the rtcnt count up starts when cks2 to cks0 are set to select the input clock. bit 2 bit 1 bit 0 cks2 cks1 cks0 description 0 0 0 stops count (initial value) 1 counts on /2 1 0 counts on /8 1 counts on /32 1 0 0 counts on /128 1 counts on /512 1 0 counts on /2048 1 counts on /4096 7.2.9 refresh timer counter (rtcnt) 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : rtcnt is an 8-bit read/write up-counter. rtcnt counts up using the internal clock selected by the dramcr cks2 to cks0 bits. when rtcnt matches the value in rtcor (compare match), the dramcr cmf flag is set to 1 and rtcnt is cleared to h'00. if, at this point, dramcr rfshe is set to 1, the refresh cycle starts. when the dramcr cmie bit is set to 1, a compare match interrupt (cmi) is also generated. rtcnt is initialized to h'00 at a power-on reset and in hardware standby mode. it is not initialized at a manual reset or in software standby mode.
section 7 bus controller rev. 3.00 jan 11, 2005 page 156 of 1220 rej09b0186-0300o 7.2.10 refresh time constant register (rtcor) 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : : rtcor is an 8-bit read/write register that sets thertcnt compare match cycle. the values of rtcor and rtcnt are constantly compared and, when both value match, the dramcr cmf flag is set to 1 and rtcnt is cleared to h'00. rtcor is initialized to h'ff at a power-on reset and in hardware standby mode. it is not initialized at a manual reset or in software standby mode.
section 7 bus controller rev. 3.00 jan 11, 2005 page 157 of 1220 rej09b0186-0300o 7.3 overview of bus control 7.3.1 area partitioning in advanced mode, the bus controller partitions the 16 mbytes address space into eight areas, 0 to 7, in 2-mbyte units, and performs bus control for external space in area units. a chip select signal ( cs0 to cs7 ) can be output for each area. in normal mode*, it controls a 64-kbyte address space comprising part of area 0. figure 7.2 shows an outline of the memory map. note: * not available in the h8s/2643 group. area 0 (2 mbytes) h'000000 h'ffffff (1) (2) h'0000 h'1fffff h'200000 area 1 (2 mbytes) h'3fffff h'400000 area 2 (2 mbytes) h'5fffff h'600000 area 3 (2 mbytes) h'7fffff h'800000 area 4 (2 mbytes) h'9fffff h'a00000 area 5 (2 mbytes) h'bfffff h'c00000 area 6 (2 mbytes) h'dfffff h'e00000 area 7 (2 mbytes) h'ffff advanced mode normal mode * note: * not available in the h8s/2643 group. figure 7.2 overview of area partitioning
section 7 bus controller rev. 3.00 jan 11, 2005 page 158 of 1220 rej09b0186-0300o 7.3.2 bus specifications the external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. the bus width and number of access states for on-chip memory and internal i/o registers are fixed, and are not affected by the bus controller. (1) bus width a bus width of 8 or 16 bits can be selected with adwcr. an area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. if all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. when the burst rom interface is designated, 16-bit bus mode is always set. (2) number of access states two or three access states can be selected with astcr. an area for which 2-state access is selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a 3-state access space. with the dram interface or the burst rom interface, the number of access states may be determined without regard to astcr. when 2-state access space is designated, wait insertion is disabled. (3) number of program wait states when 3-state access space is designated by astcr, the number of program wait states to be inserted automatically is selected with wcrh and wcrl. from 0 to 3 program wait states can be selected. table 7.3 shows the bus specifications for each basic bus interface area.
section 7 bus controller rev. 3.00 jan 11, 2005 page 159 of 1220 rej09b0186-0300o table 7.3 bus specifications for each area (basic bus interface) abwcr astcr wcrh, wcrl bus specifications (basic bus interface) abwn astn wn1 wn0 bus width access states program wait states 00 ?? 16 2 0 100 3 0 11 10 2 13 10 ?? 82 0 100 3 0 11 10 2 13 7.3.3 memory interfaces the h8s/2643 group memory interfaces comprise a basic bus interface that allows direct connection or rom, sram, and so on, dram interface with direct dram connection and a burst rom interface that allows direct connection of burst rom. the memory interface can be selected independently for each area. an area for which the basic bus interface is designated functions as normal space, and areas set for dram interface are dram spaces an area for which the burst rom interface is designated functions as burst rom space.
section 7 bus controller rev. 3.00 jan 11, 2005 page 160 of 1220 rej09b0186-0300o 7.3.4 interface specifications for each area the initial state of each area is basic bus interface, 3-state access space. the initial bus width is selected according to the operating mode. the bus specifications described here cover basic items only, and the sections on each memory interface (sections 7.4, basic bus interface, 7.5, dram interface, and 7.7, burst rom interface) should be referred to for further details. (1) area 0 area 0 includes on-chip rom, and in rom-disabled expansion mode, all of area 0 is external space. in rom-enabled expansion mode, the space excluding on-chip rom is external space. a cs0 signal can be output when accessing area 0 external space. either basic bus interface or burst rom interface can be selected for area 0. (2) areas 1 and 6 in external expansion mode, all of areas 1 and 6 is external space. cs1 and cs6 pin signals can be output when accessing the area 1 and 6 external space. only the basic bus interface can be used for areas 1 and 6. (3) areas 2 to 5 in external expansion mode, all of areas 2 to 5 is external space. cs2 to cs5 signals can be output when accessing area 2 to 5 external space. the standard bus interface or dram interface can be selected for areas 2 to 5. in dram interface mode, signals cs2 to cs5 are used as ras signals. (4) area 7 area 7 includes the on-chip ram and internal i/o registers. in external expansion mode, the space excluding the on-chip ram and internal i/o registers is external space. the on-chip ram is enabled when the rame bit in the system control register (syscr) is set to 1; when the rame bit is cleared to 0, the on-chip ram is disabled and the corresponding space becomes external space. a cs7 signal can be output when accessing area 7 external space. only the basic bus interface can be used for the area 7.
section 7 bus controller rev. 3.00 jan 11, 2005 page 161 of 1220 rej09b0186-0300o 7.3.5 chip select signals this lsi allows chip select signals ( cs0 to cs7 ) to be output for each of areas 0 to 7. the level of these signals is set low when accessing the external space of the respective area. figure 7.3 shows example csn (where n = 0 to 7) signal output timing. the output of the csn signal can be enabled or disabled by the data direction register (ddr) of the port of the corresponding csn pin. in rom-disabled expanded mode, the cs0 pin is set for output after a power-on reset. the cs1 to cs7 pins are set for input after a power-on reset, so the corresponding ddr must be set to 1 to allow the output of cs1 to cs7 signals. in rom-disabled expanded mode, all of pins cs0 to cs7 are set for input after a power-on reset, so the corresponding ddr must be set to 1 to allow the output of cs0 to cs7 signals. see section 10, i/o ports for details. when areas 2 to 5 are set as dram space, cs2 to cs5 outputs are used as ras signals. bus cycle t 1 t 2 t 3 area n external address address bus csn figure 7.3 csn signal output timing (where n=0 to 7)
section 7 bus controller rev. 3.00 jan 11, 2005 page 162 of 1220 rej09b0186-0300o 7.4 basic bus interface 7.4.1 overview the basic bus interface enables direct connection of rom, sram, and so on. the bus specifications can be selected with abwcr, astcr, wcrh, and wcrl (see table 7.3). 7.4.2 data size and data alignment data sizes for the cpu and other internal bus masters are byte, word, and longword. the bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (d15 to d8) or lower data bus (d7 to d0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. (1) 8-bit access space figure 7.4 illustrates data alignment control for the 8-bit access space. with the 8-bit access space, the upper data bus (d15 to d8) is always used for accesses. the amount of data that can be accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses. d15 d8 d7 d0 upper data bus lower data bus byte size word size 1st bus cycle 2nd bus cycle longword size 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle figure 7.4 access sizes and data alignment control (8-bit access space)
section 7 bus controller rev. 3.00 jan 11, 2005 page 163 of 1220 rej09b0186-0300o (2) 16-bit access space figure 7.5 illustrates data alignment control for the 16-bit access sp ace. with the 16-bit access space, the upper data bus (d15 to d8) and lower data bus (d7 to d0) are used for accesses. the amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. in byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. the upper data bus is used for an even address, and the lower data bus for an odd address. d15 d8 d7 d0 upper data bus byte size word size 1st bus cycle 2nd bus cycle longword size even address byte size odd address lower data bus figure 7.5 access sizes and data alignment control (16-bit access space)
section 7 bus controller rev. 3.00 jan 11, 2005 page 164 of 1220 rej09b0186-0300o 7.4.3 valid strobes table 7.4 shows the data buses used and valid strobes for the access spaces. in a read, the rd signal is valid without discr imination between the upper and lower halves of the data bus. in a write, the hwr signal is valid for the upper half of the data bus, and the lwr signal for the lower half. table 7.4 data buses used and valid strobes area access size read/ write address valid strobe upper data bus (d15 to d8) lower data bus (d7 to d0) byte read ? rd valid invalid 8-bit access space write ? hwr hi-z byte read even rd valid invalid 16-bit access space odd invalid valid write even hwr valid hi-z odd lwr hi-z valid word read ? rd valid valid write ? hwr , lwr valid valid notes: hi-z: high impedance. invalid: input state; input value is ignored.
section 7 bus controller rev. 3.00 jan 11, 2005 page 165 of 1220 rej09b0186-0300o 7.4.4 basic timing (1) 8-bit 2-state access space figure 7.6 shows the bus t iming for an 8-bit 2-state access space. when an 8-bit access space is accessed, the upper half (d15 to d8) of the data bus is used. the lwr pin is fixed high. wait states cannot be inserted. bus cycle t 1 t 2 address bus as csn rd d15 to d8 valid d7 to d0 invalid read hwr lwr d15 to d8 valid d7 to d0 high impedance write note: n = 0 to 7 high figure 7.6 bus timing for 8-bit 2-state access space
section 7 bus controller rev. 3.00 jan 11, 2005 page 166 of 1220 rej09b0186-0300o (2) 8-bit 3-state access space figure 7.7 shows the bus t iming for an 8-bit 3-state access space. when an 8-bit access space is accessed, the upper half (d15 to d8) of the data bus is used. the lwr pin is fixed high. wait states can be inserted. bus cycle t 1 t 2 address bus as csn rd d15 to d8 valid d7 to d0 invalid read hwr lwr d15 to d8 valid d7 to d0 high impedance write high note: n = 0 to 7 t 3 figure 7.7 bus timing for 8-bit 3-state access space
section 7 bus controller rev. 3.00 jan 11, 2005 page 167 of 1220 rej09b0186-0300o (3) 16-bit 2-state access space figures 7.8 to 7.10 show bus t imings for a 16-bit 2-state access space. when a 16-bit access space is accessed, the upper half (d15 to d8) of the data bus is used for the even address, and the lower half (d7 to d0) for the odd address. wait states cannot be inserted. bus cycle t 1 t 2 address bus as csn rd d15 to d8 valid d7 to d0 invalid read hwr lwr d15 to d8 valid d7 to d0 high impedance write high note: n = 0 to 7 figure 7.8 bus timing for 16-bit 2-state access space (even address byte access)
section 7 bus controller rev. 3.00 jan 11, 2005 page 168 of 1220 rej09b0186-0300o bus cycle t 1 t 2 address bus as csn rd d15 to d8 invalid d7 to d0 valid read hwr lwr d15 to d8 high impedance d7 to d0 valid write note: n = 0 to 7 high figure 7.9 bus timing for 16-bit 2-state access space (odd address byte access)
section 7 bus controller rev. 3.00 jan 11, 2005 page 169 of 1220 rej09b0186-0300o bus cycle t 1 t 2 address bus as csn rd d15 to d8 valid d7 to d0 valid read hwr lwr d15 to d8 valid d7 to d0 valid write note: n = 0 to 7 figure 7.10 bus timing for 16-bit 2-state access space (word access)
section 7 bus controller rev. 3.00 jan 11, 2005 page 170 of 1220 rej09b0186-0300o (4) 16-bit 3-state access space figures 7.11 to 7.13 show bus t imings for a 16-bit 3-state access space. when a 16-bit access space is accessed , the upper half (d15 to d8) of the data bus is used for the even address, and the lower half (d7 to d0) for the odd address. wait states can be inserted. bus cycle t 1 t 2 address bus as csn rd d15 to d8 valid d7 to d0 invalid read hwr lwr d15 to d8 valid d7 to d0 high impedance write high note: n = 0 to 7 t 3 figure 7.11 bus timing for 16-bit 3-state access space (even address byte access)
section 7 bus controller rev. 3.00 jan 11, 2005 page 171 of 1220 rej09b0186-0300o bus cycle t 1 t 2 address bus as csn rd d15 to d8 invalid d7 to d0 valid read hwr lwr d15 to d8 high impedance d7 to d0 valid write high note: n = 0 to 7 t 3 figure 7.12 bus timing for 16-bit 3-state access space (odd address byte access)
section 7 bus controller rev. 3.00 jan 11, 2005 page 172 of 1220 rej09b0186-0300o bus cycle t 1 t 2 address bus as csn rd d15 to d8 valid d7 to d0 valid read hwr lwr d15 to d8 valid d7 to d0 valid write note: n = 0 to 7 t 3 figure 7.13 bus timing for 16-bit 3-state access space (word access)
section 7 bus controller rev. 3.00 jan 11, 2005 page 173 of 1220 rej09b0186-0300o 7.4.5 wait control when accessing external space, the h8s/2643 group can extend the bus cycle by inserting one or more wait states (t w ). there are two ways of inserting wait states: program wait insertion and pin wait insertion using the wait pin. (1) program wait insertion from 0 to 3 wait states can be inserted automatically between the t 2 state and t 3 state on an individual area basis in 3-state access space, according to the settings of wcrh and wcrl. (2) pin wait insertion setting the waite bit in bcrl to 1 enables wait insertion by means of the wait pin. program wait insertion is first carried out according to the settings in wcrh and wcrl. then, if the wait pin is low at the falling edge of in the last t 2 or t w state, a t w state is inserted. if the wait pin is held low, t w states are inserted until it goes high. this is useful when inserting four or more t w states, or when changing the number of t w states for different external devices. the waite bit setting applies to all areas.
section 7 bus controller rev. 3.00 jan 11, 2005 page 174 of 1220 rej09b0186-0300o figure 7.14 shows an example of wait state insertion t iming. by program wait t 1 address bus as rd data bus read data read hwr , lwr write data write note: indicates the timing of wait pin sampling. wait data bus t 2 t w t w t w t 3 by wait pin figure 7.14 example of wait state insertion timing the settings after a power-on reset are: 3-state access, 3 program wait state insertion, and wait input disabled. at a manual reset, the bus control register values are retained and wait control continues as before the reset.
section 7 bus controller rev. 3.00 jan 11, 2005 page 175 of 1220 rej09b0186-0300o 7.5 dram interface 7.5.1 overview this lsi allows area 2 to 5 external space to be set as dram space and dram interfacing to be performed. with the dram interface, dram can be directly connected to the lsi. bcrh rmts2 to rmts0 allow the setting up of 2-, 4-, or 8-mbyte dram space. burst operation is possible using high-speed page mode. 7.5.2 setting up dram space to set up areas 2 to 5 as dram space, set the rmts2 to rmts0 bits of bcrh. table 7.5 shows the relationship between the settings of the rmts2 to rmts0 bits and dram space. you can select (1) one area (area 2), (2) two areas (areas 2 and 3), or (3) four areas (areas 2 to 5). using 16 bits 64-m drams requires a 4-m word (8-mbyte) contiguous space. setting rmts2 to rmts0 to 1 allows areas 2 to 5 to be configured as one contiguous dram space. the ras signal can be output from the cs2 pin, and cs3 to cs5 can be used as input ports. in this configuration, the bus widths are the same for areas 2 to 5. table 7.5 rmts2 to rmts0 settings vs dram space rmts2 rmts1 rmts0 area 5 area 4 area 3 area 2 0 0 1 normal space dram space 1 0 normal space dram space 1 dram space 1 1 1 contiguous dram space
section 7 bus controller rev. 3.00 jan 11, 2005 page 176 of 1220 rej09b0186-0300o 7.5.3 address multiplexing in the case of dram space, the row address and column address are multiplexed. with address multiplexing, the mxc1 and mxc0 bits of the mcr select the amount of shift in the row address. table 7.6 shows the relationship between mxc1 and mxc0 settings and the shift amount. table 7.6 mxc1 and mxc0 settings vs address multiplexing mcr address pin mxc1 mxc0 shift amount a23 to a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 row 0 0 8 bits a23 to a13 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 address 1 9 bits a23 to a13 a12 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 1 0 10 bits a23 to a13 a12 a11 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 1 setting prohibited ? ????????????? column address ??? a23 to a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 7.5.4 data bus setting the abwcr bit of an area set as dram space to 1 sets the corresponding area as 8-bit dram space. clearing the abwcr bit to 0 sets the area as 16-bit dram. 16-bit drams can be directly connected in the case of 16-bit dram space. with 8-bit dram space, the high data bus byte (d15 to d8) is valid. with 16-bit dram space, the high and low data bus bytes (d15 to d0) are valid. the access size and data alignment are the same as for the standard bus interface. see section 7.4.2, data size and data alignment for details.
section 7 bus controller rev. 3.00 jan 11, 2005 page 177 of 1220 rej09b0186-0300o 7.5.5 dram interface pins table 7.7 shows the pins used for the dram interface, and their functions. table 7.7 dram interface pin configuration pin in dram mode name direction function hwr we write enable output write enable when accessing dram space in 2 cas mode. lcas lcas lower column address strobe output lower column address strobe signal when accessing 16-bit dram space. cs2 ras2 row address strobe 2 output row address strobe when area 2 set as dram space. cs3 ras3 row address strobe 3 output row address strobe when area 3 set as dram space. cs4 ras4 row address strobe 4 output row address strobe when area 4 set as dram space. cs5 ras5 row address strobe 5 output row address strobe when area 5 set as dram space. cas ucas upper column address strobe output upper column address strobe when accessing dram space. wait wait wait input wait request signal a12 to a0 a12 to a0 address pin output multiplexed output of row address and column address. d15 to d0 d15 to d0 data pin input/output data input/output pin. oe oe * output enable pin output output enable signal when accessing dram space in read mode. note: * valid when oes bit set to 1. 7.5.6 basic timing figure 7.15 shows the basic access t iming for dram sp ace. there are four basic dram t iming states. in contrast to the standard bus interface, the corresponding astcr bit only controls the enabling/disabling of wait insertion and has no effect on the number of access states. when the corresponding astcr bit is cleared to 0, no wait states can be inserted in the dram access cycle.
section 7 bus controller rev. 3.00 jan 11, 2005 page 178 of 1220 rej09b0186-0300o the four basic timing states are as follows: t p (precharge cycle) 1 state, t r (row address output cycle) 1 state, t c1 and t c2 (column address output cycle) two states. when rcts is set to 1, the cas signal timing differs when reading and writing, being asserted ? cycle earlier when reading. t p csn (ras) read write cas, lcas cas, lcas hwr (we) rd as rd d15 tod0 hwr (we) d15 to d0 a23 to a0 t r t c1 t c2 row column note: n = 2 to 5 rcts = 1 rcts = 0 figure 7.15 basic access timing
section 7 bus controller rev. 3.00 jan 11, 2005 page 179 of 1220 rej09b0186-0300o 7.5.7 precharge state control when accessing dram, it is essential to secure a time for ras precharging. in this lsi, it is therefore necessary to insert 1 t p state when accessing dram space. by setting the tpc bit of the mcr to 1, t p can be changed from 1 state to 2 states. set the appropriate number of t p cycles according to the type of dram connected and the operation frequency of the lsi. figure 7.16 shows the timing when t p is set for 2 states. setting the tpc bit to 1 also sets the refresh cycle t p to 2 states. t p1 read write d15 to d0 d15 to d0 a23 to a0 t p2 t r t c1 row column t c2 note: n = 2 to 5 csn (ras) cas, lcas cas, lcas hwr (we) hwr (we) rcts = 0 rcts = 1 figure 7.16 timing with two precharge cycles
section 7 bus controller rev. 3.00 jan 11, 2005 page 180 of 1220 rej09b0186-0300o 7.5.8 wait control there are two methods of inserting wait states in dram access: (1) insertion of program wait states, and (2) insertion of pin waits via wait pin. (1) insertion of program wait states setting the astcr bit of an area set for dram to 1 automatically inserts from 0 to 3 wait states, as set by wcrh and wcrl, between the t c1 state and t c2 state. when a program wait is inserted, the write wait function is activated and only the cas signal is output only during the t c2 state when writing.
section 7 bus controller rev. 3.00 jan 11, 2005 page 181 of 1220 rej09b0186-0300o figure 7.17 shows example t iming for the insertion of program waits. program waits t p address bus csn (ras) cas, lcas data bus read data read cas, lcas hwr (we) rd as write data write note: shows timing for wait pin sampling. data bus t r t c1 t w t w t c2 n = 2 to 5 rcts = 0 rcts = 1 figure 7.17 example program wait insertion timing (wait 2 state insertion)
section 7 bus controller rev. 3.00 jan 11, 2005 page 182 of 1220 rej09b0186-0300o (2) insertion of pin waits when the waite bit of bcrh is set to 1, wait input via the wait pin is valid regardless of the astcr ast bit. in this state, a program wait is inserted when the dram space is accessed. if the wait pin level is low at the fall in in the final t c1 or t w state, a further t w is inserted. if the level of the wait pin is kept low, t w is inserted until the level of the wait pin changes to high. when wait states are inserted via the wait pin, the cas when writing is output after the t w state.
section 7 bus controller rev. 3.00 jan 11, 2005 page 183 of 1220 rej09b0186-0300o figure 7.18 shows example t iming for the insertion of wait states via the wait pin. wait pin wait states program waits t p address bus csn (ras) cas, lcas data bus read data read cas, lcas hwr (we) rd as write data write note: shows timing for /wait pin sampling. data bus t r t c1 t w t w t c2 n = 2 to 5 rcts = 0 rcts = 1 figure 7.18 example timing for insertion of wait states via wait pin
section 7 bus controller rev. 3.00 jan 11, 2005 page 184 of 1220 rej09b0186-0300o 7.5.9 byte access control when 16-bit drams are connected, the 2 cas method can be used as the control signal required for byte access. figure 7.19 shows the 2 cas method control t iming. figure 7.20 shows an example of connecting dram in high-speed page mode. when all areas selected as dram space are set as 8-bit space, the lcas pin functions as an i/o port. t p csn (ras) byte control a23 to a0 t r t c1 t c2 row cas lcas hwr (we) column note: n = 2 to 5 figure 7.19 2 cas method control timing (for high byte write access) when using dram edo page mode, either use oe to control the read data or, as shown in figure 7.20, select ras up mode. figure 7.21 is an example of dram connection in edo page mode when oes = 1.
section 7 bus controller rev. 3.00 jan 11, 2005 page 185 of 1220 rej09b0186-0300o this lsi (address shift set to 9 bits) cs (ras) 2cas 4-mbit dram 256 kbytes 16-bit configuration 9-bit column address oe ras cas ucas lcas lcas hwr (we) we a9 a8 a8 a7 a7 a6 a6 a5 a5 a4 a4 a3 a3 a2 a2 a1 a1 a0 d15 to d0 d15 to d0 row address input: a8 to a0 column address input: a8 to a0 figure 7.20 high-speed page mode dram
section 7 bus controller rev. 3.00 jan 11, 2005 page 186 of 1220 rej09b0186-0300o this lsi (address shift set to 10 bits) cs2 (ras) 2cas 16-mbit dram 1 mbyte 16-bit configuration 10-bit column address oe ras cas ucas lcas lcas hwr (we) cs3 (oe) we a9 a8 a10 a9 a8 a7 a7 a6 a6 a5 a5 a4 a4 a3 a3 a2 a2 a1 a1 a0 d15 to d0 d15 to d0 row address input: a9 to a0 column address input: a9 to a0 figure 7.21 example connection of edo page mode dram (oes = 1) 7.5.10 burst operation in addition to full dram access (normal dram access), in which the row address is output each time the data in dram is accessed, there is also a high-speed page mode that allows high-speed access (burst access). in this method, if the same row address is accessed successively, the row address is output once and then only the column address is changed. burst access is selected by setting the be bit of the mcr to 1.
section 7 bus controller rev. 3.00 jan 11, 2005 page 187 of 1220 rej09b0186-0300o (1) operation timing for burst access (high-speed page mode) figure 7.22 shows the operation t iming for burst access. when the dram space is successively accessed, the cas signal and column address output cycle (2 state) are continued as long as the row address is the same in the preceding and succeeding access cycles. the mxc1 and mxc0 bits of the mcr specify which row address is compared. t p cs n (ras) read write cas, lcas cas, lcas as oe oe * hwr (we) d15 to d0 hwr (we) d15 to d0 a23 to a0 t r t c1 t c2 row column1 column2 t c1 t c2 notes: n = 2 to 5 * oe is enabled when oes = 1. rcts = 1 rcts = 0 figure 7.22 operating timing in high-speed page mode the bus cycle can also be extended in burst access by inserting wait states. the method and timing of inserting the wait states is the same as in full access. for details, see section 7.5.8, wait control.
section 7 bus controller rev. 3.00 jan 11, 2005 page 188 of 1220 rej09b0186-0300o (2) ras down mode and ras up mode even when burst operation is selected, dram access may not be continuous, but may be interrupted by accessing another area. in this case, burst operation can be continued by keeping the ras signal level low while the other area is accessed and then accessing the same row address in the dram space. ? ras down mode to select ras down mode, set the rcdm bit of the mcr to 1. when dram access is interrupted and another area accessed, the ras signal level is kept low and, if the row address is the same as previously when the dram space is again accessed, burst access is continued. figure 7.23 shows example ras down mode t iming. note that if the refresh operation occurs when ras is down, the ras signal level changes to high. external space read access t p a23 to a0 csn (ras) cas, lcas rd hwr (we) oe * d15 to d0 t r t c1 t c2 t 1 t 2 dram write access dram read access t c1 t c2 notes: n = 2 to 5 * oe is enabled when oes = 1. rcts = 1 rcts = 0 figure 7.23 example operation timing in ras down mode
section 7 bus controller rev. 3.00 jan 11, 2005 page 189 of 1220 rej09b0186-0300o ? ras up mode to select ras up mode, clear the rcdm bit of the mcr to 0. if dram access is interrupted to access another area, the ras signal level returns to high. burst operation is only possible when the dram space is contiguous. figure 7.24 shows example t iming in ras up mode. note that the ras signal level does not return to high in burst rom space access. external space write access t p a23 to a0 t r t c1 t c2 t c1 t c2 dram read access dram write access t 1 t 2 d15 to d0 note: n = 2 to 5 csn (ras) cas, lcas rd hwr (we) figure 7.24 example operation timing in ras up mode
section 7 bus controller rev. 3.00 jan 11, 2005 page 190 of 1220 rej09b0186-0300o 7.5.11 refresh control this lsi has a dram refresh control function. there are two refresh methods: (1) cas-before- ras (cbr), and (2) self refresh. (1) cas-before-ras (cbr) refresh to select cbr refresh, set the rfshe bit of dramcr to 1 and clear the rmode bit to 0. in cbr refresh, the input clock selected with the cks2 to cks0 bits of dramcr are used for the rtcnt count-up. refresh control is performed when the count reaches the value set in rtcor (compare match). the rtcnt is then reset and the count again started from h'00. that is, the refresh is repeated at the set interval determined by rtcor and cks2 to cks0. set rtcor and cks2 to cks0 to satisfy the refresh cycle for the dram being used. the rtcnt count up starts when the cks2 to cks0 bits are set. the rtcnt and rtcor values should therefore be set before setting cks2 to cks0. when a value is set in rtcor, rtcnt is cleared. when rtcnt is set at the same time that it is reset by a compare match, the value written to rtcnt takes precedence. when performing refresh control (rfshe = 1), do not clear the cmf flag. figure 7.25 shows rtcnt operation. figure 7.26 shows compare match t iming. and figure 7.27 shows cbr refresh timing. some types of dram do not allow the we signal to be changed during the refresh cycle. in this case, set cbrm to 1. figure 7.28 shows the t iming. the cs signal is not controlled and a low level is output when an access request occurs. note that other normal spaces are accessed during the cbr refresh cycle. rtcor h'00 refresh re q uest rtcnt figure 7.25 rtcnt operation
section 7 bus controller rev. 3.00 jan 11, 2005 page 191 of 1220 rej09b0186-0300o rtcnt n rtcor n h'00 refresh request signal and cmf bit settin g si g nal figure 7.26 compare match timing a23 to a0 read access of normal space ras cas hwr (we) cs as rd write access of normal space refresh cycle figure 7.27 example cbr refresh timing (cbrm = 0)
section 7 bus controller rev. 3.00 jan 11, 2005 page 192 of 1220 rej09b0186-0300o a23 to a0 normal space access request ras cas hwr (we) cs as rd refresh cycle figure 7.28 example cbr refresh timing (cbrm = 1)
section 7 bus controller rev. 3.00 jan 11, 2005 page 193 of 1220 rej09b0186-0300o (2) self-refresh one of the dram standby modes is the self-refresh mode (battery backup mode), in which the dram generates its own refresh timing and refresh address. to select self-refresh, set the rfshe bit and rmode bits of the dramcr to 1. next, execute a sleep instruction to make a transition to software standby mode. as shown in figure 7.29, the cas and ras signals are output and the dram enters self-refresh mode. when you exit software standby mode, the rmode bit is cleared to 0 and self-refresh mode is exited. when making a transition to software standby mode, self-refresh mode starts after a cbr refresh, providing there is a cbr refresh request. cbr refresh requests occurring immediately before entering software standby mode are cleared on completion of the self-refresh when the software standby mode is exited. t rp t rcr cas, lcas software standby t rc3 hwr (we) csn (ras) note: n = 2 to 5 high level figure 7.29 self-refresh timing
section 7 bus controller rev. 3.00 jan 11, 2005 page 194 of 1220 rej09b0186-0300o 7.6 dmac single address mode and dram interface when burst mode is set for the dram interface, the dds bit selects the output timing for the dack signal. it also selects whether or not to perform burst access when accessing the dram space in dmac single address mode. 7.6.1 dds = 1 burst access is performed on the basis of the address only, regardless of the bus master. the dack output level changes to low afer the t c1 state in the case of the dram interface. figure 7.30 shows the dack output timing for the dram interf ace when dds = 1.
section 7 bus controller rev. 3.00 jan 11, 2005 page 195 of 1220 rej09b0186-0300o t p read write d15 to d0 d15 to d0 a23 to a0 t r t c1 t c2 row column csn (ras) cas (ucas) lcas (lcas) cas (ucas) lcas (lcas) dack hwr (we) hwr (we) rcts = 1 rcts = 0 note: n = 2 to 5 figure 7.30 dack output timing when dds = 1 (example showing dram access)
section 7 bus controller rev. 3.00 jan 11, 2005 page 196 of 1220 rej09b0186-0300o 7.6.2 dds = 0 when the dram space is accessed in dmac single address mode, always perform full access (normal access). the dack output level changes to low afer the t r state in the case of the dram interface. in other than dmac signle address mode, burst access is possible when the dram space is accessed. figure 7.31 shows the dack output timing for the dram interf ace when dds = 0.
section 7 bus controller rev. 3.00 jan 11, 2005 page 197 of 1220 rej09b0186-0300o t p read write note: n = 2 to 5 d15 to d0 d15 to d0 a23 to a0 t r t c1 t c2 row column csn ( ras ) cas ( ucas ) lcas ( lcas ) cas ( ucas ) lcas ( lcas ) dack hwr ( we ) hwr ( we ) rcts = 1 rcts = 0 figure 7.31 dack output timing when dds = 0 (example showing dram access)
section 7 bus controller rev. 3.00 jan 11, 2005 page 198 of 1220 rej09b0186-0300o 7.7 burst rom interface 7.7.1 overview in this lsi, the area 0 external space can be set as burst rom space and burst rom interfacing performed. burst rom space interfacing allows 16-bit rom capable of burst access to be accessed at high-speed. the brstrm bit of bcrh sets area 0 as burst rom space. cpu instruction fetches (only) can be performed using a maximum of 4-word or 8-word continuous burst access. 1 state or 2 states can be selected in the case of burst access. 7.7.2 basic timing the ast0 bit of astcr sets the number of access states in the initial cycle (full access) of the burst rom interface. wait states can be inserted when the ast0 bit is set to 1. the burst cycle can be set for 1 state or 2 sttes by setting the brsts1 bit of bcrh. wait states cannot be inserted. when area 0 is set as burst rom space, area 0 is a 16-bit access space regardless of the abw0 bit of abwcr. when the brsts0 bit of bcrh is cleared to 0, 4-word max. burst access is performed. when the brsts0 bit is set to 1, 8-word max. burst access is performed. figure 7.32 (a) and (b) shows the basic access t iming for the burst rom sp ace. figure 7.32 (a) is an example when both the ast0 and brsts1 bits are set to 1. figure 7.32 (b) is an example when both the ast0 and brsts1 bits are set to 0.
section 7 bus controller rev. 3.00 jan 11, 2005 page 199 of 1220 rej09b0186-0300o t 1 address bus cs0 as data bus t 2 t 3 t 1 t 2 t 1 full access t 2 rd burst access low address only changes read data read data read data figure 7.32 (a) example burst rom access timing (ast0 = brsts1 = 1)
section 7 bus controller rev. 3.00 jan 11, 2005 page 200 of 1220 rej09b0186-0300o t 1 address bus cs0 as data bus t 2 t 1 t 1 full access rd burst access low address only changes read data read data read data figure 7.32 (b) example burst rom access timing (ast0 = brsts1 = 0) 7.7.3 wait control as with the basic bus interface, either program wait insertion or pin wait insertion using the wait pin can be used in the initial cycle (full access) of the burst rom interface. see section 7.4.5, wait control. wait states cannot be inserted in the burst cycle.
section 7 bus controller rev. 3.00 jan 11, 2005 page 201 of 1220 rej09b0186-0300o 7.8 idle cycle 7.8.1 operation when the h8s/2643 group accesses external space, it can insert a 1-state idle cycle (t i ) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. by inserting an idle cycle it is possible, for example, to avoid data collisions between rom, with a long output floating time, and high-speed memory, i/o interfaces, and so on. (1) consecutive reads between different areas if consecutive reads between different areas occur while the icis1 bit in bcrh is set to 1, an idle cycle is inserted at the start of the second read cycle. figure 7.33 shows an example of the operation in this case. in this example, bus cycle a is a read cycle from rom with a long output floating time, and bus cycle b is a read cycle from sram, each being located in a different area. in (a), an idle cycle is not inserted, and a co llision occurs in cycle b between the read data from rom and that from sram. in (b), an idle cycle is inserted, and a data collision is prevented. t 1 address bus rd bus cycle a data bus t 2 t 3 t 1 t 2 bus cycle b bus cycle a bus cycle b long output floating time data collision (a) idle cycle not inserted (icis1 = 0) (b) idle cycle inserted (initial value icis1 = 1) t 1 address bus rd data bus t 2 t 3 t i t 1 t 2 cs (area a) cs (area b) cs (area a) cs (area b) figure 7.33 example of idle cycle operation (1)
section 7 bus controller rev. 3.00 jan 11, 2005 page 202 of 1220 rej09b0186-0300o (2) write after read if an external write occurs after an external read while the icis0 bit in bcrh is set to 1, an idle cycle is inserted at the start of the write cycle. figure 7.34 shows an example of the operation in this case. in this example, bus cycle a is a read cycle from rom with a long output floating time, and bus cycle b is a cpu write cycle. in (a), an idle cycle is not inserted, and a collision occurs in cycle b between the read data from rom and the cpu write data. in (b), an idle cycle is inserted, and a data collision is prevented. t 1 address bus rd bus cycle a t 2 t 3 t 1 t 2 bus cycle b possibility of overlap between cs (area b) and rd t 1 address bus bus cycle a t 2 t 3 t i t 1 bus cycle b t 2 cs (area a) cs (area b) rd cs (area a) cs (area b) (a) idle cycle not inserted (icis1 = 0) (b) idle cycle inserted (initial value icis1 = 1) figure 7.34 example of idle cycle operation (2)
section 7 bus controller rev. 3.00 jan 11, 2005 page 203 of 1220 rej09b0186-0300o (3) relationship between chip select ( cs ) signal and read ( rd ) signal depending on the system?s load conditions, the rd signal may lag behind the cs signal. an example is shown in figure 7.35. in this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle a rd signal and the bus cycle b cs signal. setting idle cycle insertion, as in (b), however, will prevent any overlap between the rd and cs signals. in the initial state after reset release, idle cycle insertion (b) is set. t 1 address bus rd bus cycle a data bus t 2 t 3 t 1 t 2 bus cycle b long output floating time data collision t 1 address bus rd bus cycle a data bus t 2 t 3 t i t 1 bus cycle b t 2 hwr hwr cs (area a) cs (area b) cs (area a) cs (area b) (a) idle cycle not inserted (icis1 = 0) (b) idle cycle inserted (initial value icis1 = 1) figure 7.35 relationship between chip select ( cs ) and read ( rd )
section 7 bus controller rev. 3.00 jan 11, 2005 page 204 of 1220 rej09b0186-0300o (4) notes the setting of the icis0 and icis1 bits is invalid when accessing the dram space. for example, if the 2nd of successive reads of different areas is a dram access, only the t p cycle is inserted, not the t 1 cycle. figure 7.36 shows the t iming. note, however, that icis0 and icis1 settings are valid in burst access in ras down mode, and an idle cycle is inserted. figure 7.37 (a) and (b) shows the timing. t 1 address bus rd external read data bus t 2 t 3 t p t r dram space read t c1 t c2 figure 7.36 example of dram access after external read extal address rd ras cas, lcas data bus dram space read t p t r t c1 t c2 t 1 t 1 t 2 t 3 t c1 t c1 t c2 external read dram space read idle cycle figure 7.37 (a) example idle cycle operation in ras down mode (icis1 = 1)
section 7 bus controller rev. 3.00 jan 11, 2005 page 205 of 1220 rej09b0186-0300o extal address rd hwr ras cas, lcas data bus dram space read t p t r t c1 t c2 t 1 t 1 t 2 t 3 t c1 t c1 t c2 external read dram space read idle cycle figure 7.37 (b) example idle cycle operation in ras down mode (icis0 = 1) 7.8.2 pin states in idle cycle table 7.8 shows pin states in an idle cycle. table 7.8 pin states in idle cycle pins pin state a23 to a0 contents of next bus cycle d15 to d0 high impedance csn high * cas high as high rd high hwr high lwr high dackn high note: * remains low in dram space ras down mode or a refresh cycle.
section 7 bus controller rev. 3.00 jan 11, 2005 page 206 of 1220 rej09b0186-0300o 7.9 write data buffer function the h8s/2643 group has a write data buffer function in the external data bus. using the write data buffer function enables external writes and dma single address mode transmission to be executed in parallel with internal accesses. the write data buffer function is made available by setting the wdbe bit in bcrl to 1. figure 7.38 shows an example of the t iming when the write data buffer function is used. when this function is used, if an external write and dma single address mode transmission continues for 2 states or longer, and there is an internal access next, only an external write is executed in the first state, but from the next state onward an internal access (on-chip memory or internal i/o register read/write) is executed in parallel with the external write rather than waiting until it ends. t 1 internal address bus a23 to a0 external write cycle hwr , lwr t 2 t w t w t 3 on-chip memory read internal i/o register read csn internal read signal d15 to d0 external address internal memory external space write internal i/o register address figure 7.38 example of timing when write data buffer function is used
section 7 bus controller rev. 3.00 jan 11, 2005 page 207 of 1220 rej09b0186-0300o 7.10 bus release 7.10.1 overview the h8s/2643 group can release the external bus in response to a bus request from an external device. in the external bus released state, the internal bus master continues to operate as long as there is no external access. if an internal bus master wants to make an external access and when a refresh request occurs in the external bus released state, it can issue a bus request off-chip. 7.10.2 operation in external expansion mode, the bus can be released to an external device by setting the brle bit in bcrl to 1. driving the breq pin low issues an external bus request to the h8s/2643 group. when the breq pin is sampled, at the prescribed timing the back pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus-released state. in the external bus released state, an internal bus master can perform accesses using the internal bus. when an internal bus master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request from the external bus master to be dropped. also, when a refresh request occurs in the external bus released state, refresh control is deferred until the external bus master drops the bus request. if the breqoe bit in bcrl is set to 1, when an internal bus master wants to make an external access and when a refresh request occurs in the external bus released state, the breqo pin is driven low and a request can be made off-chip to drop the bus request. when the breq pin is driven high, the back pin is driven high at the prescribed timing and the external bus released state is terminated. the following shows the order of priority when an external bus release request, refresh request, and external access by the internal bus master occur simultaneously: when cbrm = 1 (high) refresh > external bus release > external access by internal bus master (low) when cbrm = 0 (high) refresh > external bus release (low) (high) external bus release > external access by internal bus master (low)
section 7 bus controller rev. 3.00 jan 11, 2005 page 208 of 1220 rej09b0186-0300o note: a refresh can be executed at the same time as external access by the internal bus master. 7.10.3 pin states in external bus released state table 7.9 shows pin states in the external bus released state. table 7.9 pin states in bus released state pins pin state a23 to a0 high impedance d15 to d0 high impedance csn high impedance cas high impedance as high impedance rd high impedance hwr high impedance lwr high impedance dackn high
section 7 bus controller rev. 3.00 jan 11, 2005 page 209 of 1220 rej09b0186-0300o 7.10.4 transition timing figure 7.39 shows the t iming for transition to the bus-released state. cpu cycle external bus released state cpu cycle address minimum 1 state t 0 t 1 t 2 address bus hwr , lwr breq back csn [1] [2] [3] [4] [5] [6] data bus as rd [1] [2] [3] [4] [5] [6] note: * output onl y when breqoe is set to 1. low level of breq pin is sampled at rise of t 2 state. back pin is driven low at end of cpu read cycle, releasing bus to external bus master. breq pin state is still sampled in external bus released state. high level of breq pin is sampled. back pin is driven high, ending bus release cycle. breqo signal goes high 1.5 clocks after back signal goes high. high impedance high impedance high impedance high impedance high impedance high impedance breqo * figure 7.39 bus-released state transition timing
section 7 bus controller rev. 3.00 jan 11, 2005 page 210 of 1220 rej09b0186-0300o ras cas breq back a23 to a0 as cs rd dram space read access external bus released figure 7.40 example bus release transition timing after dram access (reading dram) 7.10.5 notes the external bus release function is deactivated when mstpcr is set to h'ffffff or h'efffff and a transition is made to sleep mode. to use the external bus release function in sleep mode, do not set mstpcr to h'ffffff and h'efffff. when the cbrm bit is set to 1 to use the cbr refresh function, set the breq = 1 width greater than the number of the slowest external access states. otherwise, cbr refresh requests from the refresh timer may not be performed.
section 7 bus controller rev. 3.00 jan 11, 2005 page 211 of 1220 rej09b0186-0300o 7.11 bus arbitration 7.11.1 overview the h8s/2643 group has a bus arbiter that arbitrates bus master operations. there are two bus masters, the cpu, dtc, and dmac which perform read/write operations when they have possession of the bus. each bus master requests the bus by means of a bus request signal. the bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. the selected bus master then takes possession of the bus and begins its operation. 7.11.2 operation the bus arbiter detects the bus masters ? bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. if there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. when a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. the order of priority of the bus masters is as follows: (high) dmac > dtc > cpu (low) an internal bus access by an internal bus master, external bus release, and refresh can be executed in parallel. in the event of simultaneous external bus release request, refresh request, and internal bus master external access request generation, the order of priority is as follows: when cbrm = 1 (high) refresh > external bus release > external access by internal bus master (low) when cbrm = 0 (high) refresh > external bus release (low) (high) external bus release > external access by internal bus master (low)
section 7 bus controller rev. 3.00 jan 11, 2005 page 212 of 1220 rej09b0186-0300o 7.11.3 bus transfer timing even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. there are specific times at which each bus master can relinquish the bus. (1) cpu the cpu is the lowest-priority bus master, and if a bus request is received from the dtc, the bus arbiter transfers the bus to the bus master that issued the request. the timing for transfer of the bus is as follows: ? the bus is transferred at a break between bus cycles. however, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. see appendix a.5, bus states during instruction execution, for t imings at which the bus is not transferred. ? if the cpu is in sleep mode, it transfers the bus immediately. (2) dtc the dtc sends the bus arbiter a request for the bus when an activation request is generated. the dtc can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). it does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). (3) dmac when a start request occurs, the dmac requests the bus arbiter for bus privileges. the dmac releases bus privileges on completion of one transmission in short address mode, normal mode external requests, and cycle steal mode. the dmac releases the bus on completion of the transmission of one block in block transmission mode, or after a transmission in burst mode.
section 7 bus controller rev. 3.00 jan 11, 2005 page 213 of 1220 rej09b0186-0300o 7.12 resets and the bus controller in a power-on reset, the h8s/2643 group, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. the bus controller registers and internal states are retained at a manual reset. the current external bus cycle is executed to completion. the wait input is ignored. write data is not retained. also, because the dmac is initialized at a manual reset, dack and tend outputs are disabled and function as i/o ports controlled by ddr and dr.
section 7 bus controller rev. 3.00 jan 11, 2005 page 214 of 1220 rej09b0186-0300o
section 8 dma controller rev. 3.00 jan 11, 2005 page 215 of 1220 rej09b0186-0300o section 8 dma controller 8.1 overview the h8s/2643 group has a built-in dma controller (dmac) which can carry out data transfer on up to 4 channels. 8.1.1 features the features of the dmac are listed below. ? choice of short address mode or full address mode short address mode ? maximum of 4 channels can be used ? choice of dual address mode or single address mode ? in dual address mode, one of the two addresses, transfer source and transfer destination, is specified as 24 bits and the other as16 bits ? in single address mode, transfer source or transfer destination address only is specified as 24 bits ? in single address mode, transfer can be performed in one bus cycle ? choice of sequential mode, idle mode, or repeat mode for dual address mode and single address mode full address mode ? maximum of 2 channels can be used ? transfer source and transfer destination address specified as 24 bits ? choice of normal mode or block transfer mode ? 16-mbyte address space can be specified directly ? byte or word can be set as the transfer unit ? activation sources: internal interrupt, external request, auto-request (depending on transfer mode) ? six 16-bit timer-pulse unit (tpu) compare match/input capture interrupts ? serial communication interface (sci0, sci1) transmit-data-empty interrupt, reception complete interrupt ? a/d converter conversion end interrupt ? external request ? auto-request
section 8 dma controller rev. 3.00 jan 11, 2005 page 216 of 1220 rej09b0186-0300o ? module stop mode can be set ? the initial setting enables dmac registers to be accessed. dmac operation is halted by setting module stop mode 8.1.2 block diagram a block diagram of the dmac is shown in figure 8.1. internal address bus address buffer processor internal interrupts tgi0a tgi1a tgi2a tgi3a tgi4a tgi5a txi0 rxi0 txi1 rxi1 adi external pins dreq0 dreq1 tend0 tend1 dack0 dack1 interrupt signals dend0a dend0b dend1a dend1b control logic dmawer dmacr1b dmacr1a dmacr0b dmacr0a dmatcr dmabcr data buffer internal data bus mar0a ioar0a etcr0a mar0b ioar0b etcr0b mar1a ioar1a etcr1a mar1b ioar1b etcr1b legend: dma write enable register dma terminal control register dma band control register (for all channels) dma control register memory address register i/o address register executive transfer counter register channel 0 channel 1 channel 0a channel 0b channel 1a channel 1b module data bus dmawer: dmatcr: dmabcr: dmacr: mar: ioar: etcr: figure 8.1 block diagram of dmac
section 8 dma controller rev. 3.00 jan 11, 2005 page 217 of 1220 rej09b0186-0300o 8.1.3 overview of functions tables 8.1 (a) and (b) summarize dmac functions in short address mode and full address mode, respectively. table 8.1 (a) overview of dmac functions (short address mode) address register bit length transfer mode transfer source source destination dual address mode ? sequential mode ? 1-byte or 1-word transfer executed for one transfer request ? memory address incremented/decremented by 1 or 2 ? 1 to 65536 transfers ? idle mode ? 1-byte or 1-word transfer executed for one transfer request ? memory address fixed ? 1 to 65536 transfers ? repeat mode ? 1-byte or 1-word transfer executed for one transfer request ? memory address incremented/ decremented by 1 or 2 ? after specified number of transfers (1 to 256), initial state is restored and operation continues ? tpu channel 0 to 5 compare match/input capture a interrupt ? sci transmit-data- empty interrupt ? sci reception complete interrupt ? a/d converter conversion end interrupt ? external request 24/16 16/24 single address mode ? 1-byte or 1-word transfer executed for one transfer request ? transfer in 1 bus cycle using dack pin in place of address specifying i/o ? specifiable for sequential, idle, and repeat modes ? external request 24/ dack dack /24
section 8 dma controller rev. 3.00 jan 11, 2005 page 218 of 1220 rej09b0186-0300o table 8.1 (b) overview of dmac functions (full address mode) address register bit length transfer mode transfer source source destination ? normal mode auto-request ? transfer request retained internally ? transfers continue for the specified number of times (1 to 65536) ? choice of burst or cycle steal transfer ? auto-request 24 24 external request ? 1-byte or 1-word transfer executed for one transfer request ? 1 to 65536 transfers ? external request ? block transfer mode ? specified block size transfer executed for one transfer request ? 1 to 65536 transfers ? either source or destination specifiable as block area ? block size: 1 to 256 bytes or words ? tpu channel 0 to 5 compare match/input capture a interrupt ? sci transmit-data- empty interrupt ? sci reception complete interrupt ? external request ? a/d converter conversion end interrupt 24 24
section 8 dma controller rev. 3.00 jan 11, 2005 page 219 of 1220 rej09b0186-0300o 8.1.4 pin configuration table 8.2 summarizes the dmac pins. in short address mode, external request transfer, single address transfer, and transfer end output are not performed for channel a. the dma transfer acknowledge function is used in channel b single address mode in short address mode. when the dreq pin is used, do not designate the corresponding port for output. with regard to the dack pins, setting single address transfer automatically sets the corresponding port to output, functioning as a dack pin. with regard to the tend pins, whether or not the corresponding port is used as a tend pin can be specified by means of a register setting. table 8.2 dmac pins channel pin name symbol i/o function 0 dma request 0 dreq0 input dmac channel 0 external request dma transfer acknowledge 0 dack0 output dmac channel 0 single address transfer acknowledge dma transfer end 0 tend0 output dmac channel 0 transfer end 1 dma request 1 dreq1 input dmac channel 1 external request dma transfer acknowledge 1 dack1 output dmac channel 1 single address transfer acknowledge dma transfer end 1 tend1 output dmac channel 1 transfer end
section 8 dma controller rev. 3.00 jan 11, 2005 page 220 of 1220 rej09b0186-0300o 8.1.5 register configuration table 8.3 summarizes the dmac registers. table 8.3 dmac registers channel name abbreviation r/w initial value address * bus width 0 memory address register 0a mar0a r/w undefined h'fee0 16 bits i/o address register 0a ioar0a r/w undefined h'fee4 16 bits transfer count register 0a etcr0a r/w undefined h'fee6 16 bits memory address register 0b mar0b r/w undefined h'fee8 16 bits i/o address register 0b ioar0b r/w undefined h'feec 16 bits transfer count register 0b etcr0b r/w undefined h'feee 16 bits 1 memory address register 1a mar1a r/w undefined h'fef0 16 bits i/o address register 1a ioar1a r/w undefined h'fef4 16 bits transfer count register 1a etcr1a r/w undefined h'fef6 16 bits memory address register 1b mar1b r/w undefined h'fef8 16 bits i/o address register 1b ioar1b r/w undefined h'fefc 16 bits transfer count register 1b etcr1b r/w undefined h'fefe 16 bits 0, 1 dma write enable register dmawer r/w h'00 h'ff60 8 bits dma terminal control register dmatcr r/w h'00 h'ff61 8 bits dma control register 0a dmacr0a r/w h'00 h'ff62 16 bits dma control register 0b dmacr0b r/w h'00 h'ff63 16 bits dma control register 1a dmacr1a r/w h'00 h'ff64 16 bits dma control register 1b dmacr1b r/w h'00 h'ff65 16 bits dma band control register dmabcr r/w h'0000 h'ff66 16 bits module stop control register a mstpcra r/w h'3f h'fde8 8 bits note: * lower 16 bits of the address.
section 8 dma controller rev. 3.00 jan 11, 2005 page 221 of 1220 rej09b0186-0300o 8.2 register descriptions (1) (short address mode) short address mode transfer can be performed for channels a and b independently. short address mode transfer is specified for each channel by clearing the fae bit in dmabcr to 0, as shown in table 8.4. short address mode or full address mode can be selected for channels 1 and 0 independently by means of bits fae1 and fae0. table 8.4 short address mode and full address mode (for 1 channel: example of channel 0) fae0 description 0 short address mode specified (channels a and b operate independently) channel 0a mar0a specifies transfer source/transfer destination address specifies transfer destination/transfer source address specifies number of transfers specifies transfer size, mode, activation source, etc. specifies transfer source/transfer destination address specifies transfer destination/transfer source address specifies number of transfers specifies transfer size, mode, activation source, etc. ioar0a etcr0a dmacr0a channel 0b mar0b ioar0b etcr0b dmacr0b 1 full address mode specified (channels a and b operate in combination) channel 0 mar0a specifies transfer source address specifies transfer destination address not used not used specifies number of transfers specifies number of transfers (used in block transfer mode only) specifies transfer size, mode, activation source, etc. ioar0a etcr0a dmacr0a mar0b ioar0b etcr0b dmacr0b
section 8 dma controller rev. 3.00 jan 11, 2005 page 222 of 1220 rej09b0186-0300o 8.2.1 memory address register (mar) bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mar :???????? initial value:00000000 ******** r/w : ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w bit :1514131211109876543210 mar : initial value : **************** r/w : r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w * : undefined mar is a 32-bit readable/writable register that specifies the transfer source address or destination address. the upper 8 bits of mar are reserved: they are always read as 0, and cannot be modified. whether mar functions as the source address register or as the destination address register can be selected by means of the dtdir bit in dmacr. mar is incremented or decremented each time a byte or word transfer is executed, so that the address specified by mar is constantly updated. for details, see section 8.2.4, dma control register (dmacr). mar is not initialized by a reset or in standby mode.
section 8 dma controller rev. 3.00 jan 11, 2005 page 223 of 1220 rej09b0186-0300o 8.2.2 i/o address register (ioar) bit :1514131211109876543210 ioar : initial value : **************** r/w : r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w * : undefined ioar is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer source address or destination address. the upper 8 bits of the transfer address are automatically set to h'ff. whether ioar functions as the source address register or as the destination address register can be selected by means of the dtdir bit in dmacr. ioar is invalid in single address mode. ioar is not incremented or decremented each time a transfer is executed, so that the address specified by ioar is fixed. ioar is not initialized by a reset or in standby mode. 8.2.3 execute transfer count register (etcr) etcr is a 16-bit readable/writable register that specifies the number of transfers. the setting of this register is different for sequential mode and idle mode on the one hand, and for repeat mode on the other. (1) sequential mode and idle mode transfer counter bit :1514131211109876543210 etcr : initial value : **************** r/w : r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w * : undefined
section 8 dma controller rev. 3.00 jan 11, 2005 page 224 of 1220 rej09b0186-0300o in sequential mode and idle mode, etcr functions as a 16-bit transfer counter (with a count range of 1 to 65,536). etcr is decremented by 1 each time a transfer is performed, and when the count reaches h'0000, the dte bit in dmabcr is cleared, and transfer ends. (2) repeat mode transfer number storage bit : 15 14 13 12 11 10 9 8 etcrh : initial value : ******** r/w : r/w r/w r/w r/w r/w r/w r/w r/w transfer counter bit:76543210 etcrl : initial value : ******** r/w : r/w r/w r/w r/w r/w r/w r/w r/w * : undefined in repeat mode, etcr functions as transfer counter etcrl (with a count range of 1 to 256) and transfer number storage register etcrh. etcrl is decremented by 1 each time a transfer is performed, and when the count reaches h'00, etcrl is loaded with the value in etcrh. at this point, mar is automatically restored to the value it had when the count was started. the dte bit in dmabcr is not cleared, and so transfers can be performed repeatedly until the dte bit is cleared by the user. etcr is not initialized by a reset or in standby mode. 8.2.4 dma control register (dmacr) bit:76543210 dmacr : dtsz dtid rpe dtdir dtf3 dtf2 dtf1 dtf0 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w dmacr is an 8.bit readable/writable register that controls the operation of each dmac channel. dmacr is initialized to h'00 by a reset, and in standby mode.
section 8 dma controller rev. 3.00 jan 11, 2005 page 225 of 1220 rej09b0186-0300o bit 7?data transfer size (dtsz): selects the size of data to be transferred at one time. bit 7 dtsz description 0 byte-size transfer (initial value) 1 word-size transfer bit 6?data transfer increment/decrement (dtid): selects incrementing or decrementing of mar every data transfer in sequential mode or repeat mode. in idle mode, mar is neither incremented nor decremented. bit 6 dtid description 0 mar is incremented after a data transfer (initial value) ? when dtsz = 0, mar is incremented by 1 after a transfer ? when dtsz = 1, mar is incremented by 2 after a transfer 1 mar is decremented after a data transfer ? when dtsz = 0, mar is decremented by 1 after a transfer ? when dtsz = 1, mar is decremented by 2 after a transfer bit 5?repeat enable (rpe): used in combination with the dtie bit in dmabcr to select the mode (sequential, idle, or repeat) in which transfer is to be performed. bit 5 dmabcr rpe dtie description 0 0 transfer in sequential mode (no transfer end interrupt) (initial value) 1 transfer in sequential mode (with transfer end interrupt) 1 0 transfer in repeat mode (no transfer end interrupt) 1 transfer in idle mode (with transfer end interrupt) for details of operation in sequential, idle, and repeat mode, see section 8.5.2, sequential mode, section 8.5.3, idle mode, and section 8.5.4, repeat mode.
section 8 dma controller rev. 3.00 jan 11, 2005 page 226 of 1220 rej09b0186-0300o bit 4?data transfer direction (dtdir): used in combination with the sae bit in dmabcr to specify the data transfer direction (source or destination). the function of this bit is therefore different in dual address mode and single address mode. dmabcr bit 4 sae dtdir description 00 transfer with mar as source address and ioar as destination address (initial value) 1 transfer with ioar as source address and mar as destination address 1 0 transfer with mar as source address and dack pin as write strobe 1 transfer with dack pin as read strobe and mar as destination address bits 3 to 0?data transfer factor (dtf3 to dtf0): these bits select the data transfer factor (activation source). there are some differences in activation sources for channel a and for channel b.
section 8 dma controller rev. 3.00 jan 11, 2005 page 227 of 1220 rej09b0186-0300o channel a bit 3 bit 2 bit 1 bit 0 dtf3 dtf2 dtf1 dtf0 description 0 0 0 0 ? (initial value) 1 activated by a/d converter conversion end interrupt 10? 1? 1 0 0 activated by sci channel 0 transmit-data-empty interrupt 1 activated by sci channel 0 reception complete interrupt 1 0 activated by sci channel 1 transmit-data-empty interrupt 1 activated by sci channel 1 reception complete interrupt 1000 activated by tpu channel 0 compare match/input capture a interrupt 1 activated by tpu channel 1 compare match/input capture a interrupt 1 0 activated by tpu channel 2 compare match/input capture a interrupt 1 activated by tpu channel 3 compare match/input capture a interrupt 1 0 0 activated by tpu channel 4 compare match/input capture a interrupt 1 activated by tpu channel 5 compare match/input capture a interrupt 10? 1?
section 8 dma controller rev. 3.00 jan 11, 2005 page 228 of 1220 rej09b0186-0300o channel b bit 3 bit 2 bit 1 bit 0 dtf3 dtf2 dtf1 dtf0 description 0 0 0 0 ? (initial value) 1 activated by a/d converter conversion end interrupt 1 0 activated by dreq pin falling edge input * 1 activated by dreq pin low-level input 1 0 0 activated by sci channel 0 transmit-data-empty interrupt 1 activated by sci channel 0 reception complete interrupt 1 0 activated by sci channel 1 transmit-data-empty interrupt 1 activated by sci channel 1 reception complete interrupt 1000 activated by tpu channel 0 compare match/input capture a interrupt 1 activated by tpu channel 1 compare match/input capture a interrupt 1 0 activated by tpu channel 2 compare match/input capture a interrupt 1 activated by tpu channel 3 compare match/input capture a interrupt 1 0 0 activated by tpu channel 4 compare match/input capture a interrupt 1 activated by tpu channel 5 compare match/input capture a interrupt 10? 1? note: * detected as a low level in the first transfer after transfer is enabled. the same factor can be selected for more than one channel. in this case, activation starts with the highest-priority channel according to the relative channel priorities. for relative channel priorities, see section 8.5.13, dmac multi-channel operation.
section 8 dma controller rev. 3.00 jan 11, 2005 page 229 of 1220 rej09b0186-0300o 8.2.5 dma band control register (dmabcr) bit : 15 14 13 12 11 10 9 8 dmabcrh : fae1 fae0 sae1 sae0 dta1b dta1a dta0b dta0a initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 dmabcrl : dte1b dte1a dte0b dte0a dtie1b dtie1a dtie0b dtie0a initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w dmabcr is a 16-bit readable/writable register that controls the operation of each dmac channel. dmabcr is initialized to h'0000 by a reset, and in standby mode. bit 15?full address enable 1 (fae1): specifies whether channel 1 is to be used in short address mode or full address mode. in short address mode, channels 1a and 1b are used as independent channels. bit 15 fae1 description 0 short address mode (initial value) 1 full address mode bit 14?full address enable 0 (fae0): specifies whether channel 0 is to be used in short address mode or full address mode. in short address mode, channels 0a and 0b are used as independent channels. bit 14 fae0 description 0 short address mode (initial value) 1 full address mode
section 8 dma controller rev. 3.00 jan 11, 2005 page 230 of 1220 rej09b0186-0300o bit 13?single address enable 1 (sae1): specifies whether channel 1b is to be used for transfer in dual address mode or single address mode. bit 13 sae1 description 0 transfer in dual address mode (initial value) 1 transfer in single address mode this bit is invalid in full address mode. bit 12?single address enable 0 (sae0): specifies whether channel 0b is to be used for transfer in dual address mode or single address mode. bit 12 sae0 description 0 transfer in dual address mode (initial value) 1 transfer in single address mode this bit is invalid in full address mode. bits 11 to 8?data transfer acknowledge (dta): these bits enable or disable clearing, when dma transfer is performed, of the internal interrupt source selected by the data transfer factor setting. when dte = 1 and dta = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by dma transfer. when dte = 1 and dta = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the cpu or dtc. when dte = 1 and dta = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the cpu or dtc in parallel. in this case, the interrupt source should be cleared by the cpu or dtc transfer. when dte = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the cpu or dtc regardless of the dta bit setting. bit 11?data transfer acknowledge 1b (dta1b): enables or disables clearing, when dma transfer is performed, of the internal interrupt source selected by the channel 1b data transfer factor setting.
section 8 dma controller rev. 3.00 jan 11, 2005 page 231 of 1220 rej09b0186-0300o bit 11 dta1b description 0 clearing of selected internal interrupt source at time of dma transfer is disabled (initial value) 1 clearing of selected internal interrupt source at time of dma transfer is enabled bit 10?data transfer acknowledge 1a (dta1a): enables or disables clearing, when dma transfer is performed, of the internal interrupt source selected by the channel 1a data transfer factor setting. bit 10 dta1a description 0 clearing of selected internal interrupt source at time of dma transfer is disabled (initial value) 1 clearing of selected internal interrupt source at time of dma transfer is enabled bit 9?data transfer acknowledge 0b (dta0b): enables or disables clearing, when dma transfer is performed, of the internal interrupt source selected by the channel 0b data transfer factor setting. bit 9 dta0b description 0 clearing of selected internal interrupt source at time of dma transfer is disabled (initial value) 1 clearing of selected internal interrupt source at time of dma transfer is enabled bit 8?data transfer acknowledge 0a (dta0a): enables or disables clearing, when dma transfer is performed, of the internal interrupt source selected by the channel 0a data transfer factor setting. bit 8 dta0a description 0 clearing of selected internal interrupt source at time of dma transfer is disabled (initial value) 1 clearing of selected internal interrupt source at time of dma transfer is enabled bits 7 to 4?data transfer enable (dte): when dte = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. if the activation source is
section 8 dma controller rev. 3.00 jan 11, 2005 page 232 of 1220 rej09b0186-0300o an internal interrupt, an interrupt request is issued to the cpu or dtc. if the dtie bit is set to 1 when dte = 0, the dmac regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the cpu or dtc. the conditions for the dte bit being cleared to 0 are as follows: ? when initialization is performed ? when the specified number of transfers have been completed in a transfer mode other than repeat mode ? when 0 is written to the dte bit to forcibly abort the transfer, or for a similar reason when dte = 1, data transfer is enabled and the dmac waits for a request by the activation source selected by the data transfer factor setting. when a request is issued by the activation source, dma transfer is executed. the condition for the dte bit being set to 1 is as follows: ? when 1 is written to the dte bit after the dte bit is read as 0 bit 7?data transfer enable 1b (dte1b): enables or disables data transfer on channel 1b. bit 7 dte1b description 0 data transfer disabled (initial value) 1 data transfer enabled bit 6?data transfer enable 1a (dte1a): enables or disables data transfer on channel 1a. bit 6 dte1a description 0 data transfer disabled (initial value) 1 data transfer enabled bit 5?data transfer enable 0b (dte0b): enables or disables data transfer on channel 0b. bit 5 dte0b description 0 data transfer disabled (initial value) 1 data transfer enabled
section 8 dma controller rev. 3.00 jan 11, 2005 page 233 of 1220 rej09b0186-0300o bit 4?data transfer enable 0a (dte0a): enables or disables data transfer on channel 0a. bit 4 dte0a description 0 data transfer disabled (initial value) 1 data transfer enabled bits 3 to 0?data transfer end interrupt enable (dtie): these bits enable or disable an interrupt to the cpu or dtc when transfer ends. if the dtie bit is set to 1 when dte = 0, the dmac regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the cpu or dtc. a transfer end interrupt can be canceled either by clearing the dtie bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the dte bit to 1. bit 3?data transfer end interrupt enable 1b (dtie1b): enables or disables the channel 1b transfer end interrupt. bit 3 dtie1b description 0 transfer end interrupt disabled (initial value) 1 transfer end interrupt enabled bit 2?data transfer end interrupt enable 1a (dtie1a): enables or disables the channel 1a transfer end interrupt. bit 2 dtie1a description 0 transfer end interrupt disabled (initial value) 1 transfer end interrupt enabled
section 8 dma controller rev. 3.00 jan 11, 2005 page 234 of 1220 rej09b0186-0300o bit 1?data transfer end interrupt enable 0b (dtie0b): enables or disables the channel 0b transfer end interrupt. bit 1 dtie0b description 0 transfer end interrupt disabled (initial value) 1 transfer end interrupt enabled bit 0?data transfer end interrupt enable 0a (dtie0a): enables or disables the channel 0a transfer end interrupt. bit 0 dtie0a description 0 transfer end interrupt disabled (initial value) 1 transfer end interrupt enabled 8.3 register descriptions (2) (full address mode) full address mode transfer is performed with channels a and b together. for details of full address mode setting, see table 8.4. 8.3.1 memory address register (mar) bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mar :???????? initial value:00000000 ******** r/w : ? ? ? ? ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w bit :1514131211109876543210 mar : initial value : **************** r/w : r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w * : undefined mar is a 32-bit readable/writable register; mara functions as the transfer source address register, and marb as the destination address register.
section 8 dma controller rev. 3.00 jan 11, 2005 page 235 of 1220 rej09b0186-0300o mar is composed of two 16-bit registers, marh and marl. the upper 8 bits of marh are reserved: they are always read as 0, and cannot be modified. mar is incremented or decremented each time a byte or word transfer is executed, so that the source or destination memory address can be updated automatically. for details, see section 8.3.4, dma control register (dmacr). mar is not initialized by a reset or in standby mode. 8.3.2 i/o address register (ioar) ioar is not used in full address transfer. 8.3.3 execute transfer count register (etcr) etcr is a 16-bit readable/writable register that specifies the number of transfers. the function of this register is different in normal mode and in block transfer mode. etcr is not initialized by a reset or in standby mode. (1) normal mode etcra transfer counter bit :1514131211109876543210 etcr : initial value : **************** r/w : r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w * : undefined in normal mode, etcra functions as a 16-bit transfer counter. etcra is decremented by 1 each time a transfer is performed, and transfer ends when the count reaches h'0000. etcrb is not used at this time. etcrb etcrb is not used in normal mode.
section 8 dma controller rev. 3.00 jan 11, 2005 page 236 of 1220 rej09b0186-0300o (2) block transfer mode etcra holds block size bit : 15 14 13 12 11 10 9 8 etcrah : initial value : ******** r/w : r/w r/w r/w r/w r/w r/w r/w r/w block size counter bit:76543210 etcral : initial value : ******** r/w : r/w r/w r/w r/w r/w r/w r/w r/w * : undefined etcrb block transfer counter bit :1514131211109876543210 etcrb : initial value : **************** r/w : r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w in block transfer mode, etcral functions as an 8-bit block size counter and etcrah holds the block size. etcral is decremented each time a 1-byte or 1-word transfer is performed, and when the count reaches h'00, etcral is loaded with the value in etcrah. so by setting the block size in etcrah and etcral, it is possible to repeatedly transfer blocks consisting of any desired number of bytes or words. etcrb functions in block transfer mode, as a 16-bit block transfer counter. etcrb is decremented by 1 each time a block is transferred, and transfer ends when the count reaches h'0000.
section 8 dma controller rev. 3.00 jan 11, 2005 page 237 of 1220 rej09b0186-0300o 8.3.4 dma control register (dmacr) dmacr is a 16-bit readable/writable register that controls the operation of each dmac channel. in full address mode, dmacra and dmacrb have different functions. dmacr is initialized to h'0000 by a reset, and in standby mode. dmacra bit : 15 14 13 12 11 10 9 8 dmacra : dtsz said saide blkdir blke ? ? ? initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w dmacrb bit:76543210 dmacrb : ? daid daide ? dtf3 dtf2 dtf1 dtf0 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w bit 15?data transfer size (dtsz): selects the size of data to be transferred at one time. bit 15 dtsz description 0 byte-size transfer (initial value) 1 word-size transfer bit 14?source address increment/decrement (said) bit 13?source address increment/decrement enable (saide): these bits specify whether source address register mara is to be incremented, decremented, or left unchanged, when data transfer is performed.
section 8 dma controller rev. 3.00 jan 11, 2005 page 238 of 1220 rej09b0186-0300o bit 14 bit 13 said saide description 0 0 mara is fixed (initial value) 1 mara is incremented after a data transfer ? when dtsz = 0, mara is incremented by 1 after a transfer ? when dtsz = 1, mara is incremented by 2 after a transfer 1 0 mara is fixed 1 mara is decremented after a data transfer ? when dtsz = 0, mara is decremented by 1 after a transfer ? when dtsz = 1, mara is decremented by 2 after a transfer bit 12?block direction (blkdir) bit 11?block enable (blke): these bits specify whether normal mode or block transfer mode is to be used. if block transfer mode is specified, the blkdir bit specifies whether the source side or the destination side is to be the block area. bit 12 bit 11 blkdir blke description 0 0 transfer in normal mode (initial value) 1 transfer in block transfer mode, destination side is block area 1 0 transfer in normal mode 1 transfer in block transfer mode, source side is block area for operation in normal mode and block transfer mode, see section 8.5, operation.
section 8 dma controller rev. 3.00 jan 11, 2005 page 239 of 1220 rej09b0186-0300o bits 10 to 7?reserved: can be read or written to. bit 6?destination address increment/decrement (daid) bit 5?destination address increment/decrement enable (daide): these bits specify whether destination address register marb is to be incremented, decremented, or left unchanged, when data transfer is performed. bit 6 bit 5 daid daide description 0 0 marb is fixed (initial value) 1 marb is incremented after a data transfer ? when dtsz = 0, marb is incremented by 1 after a transfer ? when dtsz = 1, marb is incremented by 2 after a transfer 1 0 marb is fixed 1 marb is decremented after a data transfer ? when dtsz = 0, marb is decremented by 1 after a transfer ? when dtsz = 1, marb is decremented by 2 after a transfer bit 4?reserved: can be read or written to. bits 3 to 0?data transfer factor (dtf3 to dtf0): these bits select the data transfer factor (activation source). the factors that can be specified differ between normal mode and block transfer mode. ? normal mode bit 3 bit 2 bit 1 bit 0 dtf3 dtf2 dtf1 dtf0 description 0 0 0 0 ? (initial value) 1? 1 0 activated by dreq pin falling edge input 1 activated by dreq pin low-level input 10 * ? 1 0 auto-request (cycle steal) 1 auto-request (burst) 1 *** ? * : don't care
section 8 dma controller rev. 3.00 jan 11, 2005 page 240 of 1220 rej09b0186-0300o ? block transfer mode bit 3 bit 2 bit 1 bit 0 dtf3 dtf2 dtf1 dtf0 description 0 0 0 0 ? (initial value) 1 activated by a/d converter conversion end interrupt 1 0 activated by dreq pin falling edge input * 1 activated by dreq pin low-level input 1 0 0 activated by sci channel 0 transmit-data-empty interrupt 1 activated by sci channel 0 reception complete interrupt 1 0 activated by sci channel 1 transmit-data-empty interrupt 1 activated by sci channel 1 reception complete interrupt 1000 activated by tpu channel 0 compare match/input capture a interrupt 1 activated by tpu channel 1 compare match/input capture a interrupt 1 0 activated by tpu channel 2 compare match/input capture a interrupt 1 activated by tpu channel 3 compare match/input capture a interrupt 1 0 0 activated by tpu channel 4 compare match/input capture a interrupt 1 activated by tpu channel 5 compare match/input capture a interrupt 10? 1? note: * detected as a low level in the first transfer after transfer is enabled. the same factor can be selected for more than one channel. in this case, activation starts with the highest-priority channel according to the relative channel priorities. for relative channel priorities, see section 8.5.13, dmac multi-channel operation.
section 8 dma controller rev. 3.00 jan 11, 2005 page 241 of 1220 rej09b0186-0300o 8.3.5 dma band control register (dmabcr) bit : 15 14 13 12 11 10 9 8 dmabcrh : fae1 fae0 ? ? dta1 ? dta0 ? initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 dmabcrl : dtme1 dte1 dtme0 dte0 dtie1b dtie1a dtie0b dtie0a initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w dmabcr is a 16-bit readable/writable register that controls the operation of each dmac channel. dmabcr is initialized to h'0000 by a reset, and in standby mode. bit 15?full address enable 1 (fae1): specifies whether channel 1 is to be used in short address mode or full address mode. in full address mode, channels 1a and 1b are used together as a single channel. bit 15 fae1 description 0 short address mode (initial value) 1 full address mode bit 14?full address enable 0 (fae0): specifies whether channel 0 is to be used in short address mode or full address mode. in full address mode, channels 0a and 0b are used together as a single channel. bit 14 fae0 description 0 short address mode (initial value) 1 full address mode
section 8 dma controller rev. 3.00 jan 11, 2005 page 242 of 1220 rej09b0186-0300o bits 13 and 12?reserved: can be read or written to. bits 11 and 9?data transfer acknowledge (dta): these bits enable or disable clearing, when dma transfer is performed, of the internal interrupt source selected by the data transfer factor setting. when dte = 1 and dta = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by dma transfer. when dte = 1 and dta = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the cpu or dtc. when the dte = 1 and the dta = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the cpu or dtc in parallel. in this case, the interrupt source should be cleared by the cpu or dtc transfer. when the dte = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the cpu or dtc regardless of the dta bit setting. the state of the dtme bit does not affect the above operations. bit 11?data transfer acknowledge 1 (dta1): enables or disables clearing, when dma transfer is performed, of the internal interrupt source selected by the channel 1 data transfer factor setting. bit 11 dta1 description 0 clearing of selected internal interrupt source at time of dma transfer is disabled (initial value) 1 clearing of selected internal interrupt source at time of dma transfer is enabled bit 9?data transfer acknowledge 0 (dta0): enables or disables clearing, when dma transfer is performed, of the internal interrupt source selected by the channel 0 data transfer factor setting. bit 9 dta0 description 0 clearing of selected internal interrupt source at time of dma transfer is disabled (initial value) 1 clearing of selected internal interrupt source at time of dma transfer is enabled
section 8 dma controller rev. 3.00 jan 11, 2005 page 243 of 1220 rej09b0186-0300o bits 10 and 8?reserved: can be read or written to. bits 7 and 5?data transfer master enable (dtme): together with the dte bit, these bits control enabling or disabling of data transfer on the relevant channel. when both the dtme bit and the dte bit are set to 1, transfer is enabled for the channel. if the relevant channel is in the middle of a burst mode transfer when an nmi interrupt is generated, the dtme bit is cleared, the transfer is interrupted, and bus mastership passes to the cpu. when the dtme bit is subsequently set to 1 again, the interrupted transfer is resumed. in block transfer mode, however, the dtme bit is not cleared by an nmi interrupt, and transfer is not interrupted. the conditions for the dtme bit being cleared to 0 are as follows: ? when initialization is performed ? when nmi is input in burst mode ? when 0 is written to the dtme bit the condition for dtme being set to 1 is as follows: ? when 1 is written to dtme after dtme is read as 0 bit 7?data transfer master enable 1 (dtme1): enables or disables data transfer on channel 1. bit 7 dtme1 description 0 data transfer disabled. in burst mode, cleared to 0 by an nmi interrupt (initial value) 1 data transfer enabled bit 5?data transfer master enable 0 (dtme0): enables or disables data transfer on channel 0. bit 5 dtme0 description 0 data transfer disabled. in normal mode, cleared to 0 by an nmi interrupt (initial value) 1 data transfer enabled
section 8 dma controller rev. 3.00 jan 11, 2005 page 244 of 1220 rej09b0186-0300o bits 6 and 4?data transfer enable (dte): when dte = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. if the activation source is an internal interrupt, an interrupt request is issued to the cpu or dtc. if the dtie bit is set to 1 when dte = 0, the dmac regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the cpu. the conditions for the dte bit being cleared to 0 are as follows: ? when initialization is performed ? when the specified number of transfers have been completed ? when 0 is written to the dte bit to forcibly abort the transfer, or for a similar reason when dte = 1 and dtme = 1, data transfer is enabled and the dmac waits for a request by the activation source selected by the data transfer factor setting. when a request is issued by the activation source, dma transfer is executed. the condition for the dte bit being set to 1 is as follows: ? when 1 is written to the dte bit after the dte bit is read as 0 bit 6?data transfer enable 1 (dte1): enables or disables data transfer on channel 1. bit 6 dte1 description 0 data transfer disabled (initial value) 1 data transfer enabled bit 4?data transfer enable 0 (dte0): enables or disables data transfer on channel 0. bit 4 dte0 description 0 data transfer disabled (initial value) 1 data transfer enabled bits 3 and 1?data transfer interrupt enable b (dtieb): these bits enable or disable an interrupt to the cpu or dtc when transfer is interrupted. if the dtieb bit is set to 1 when dtme = 0, the dmac regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the cpu or dtc. a transfer break interrupt can be canceled either by clearing the dtieb bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the dtme bit to 1.
section 8 dma controller rev. 3.00 jan 11, 2005 page 245 of 1220 rej09b0186-0300o bit 3?data transfer interrupt enable 1b (dtie1b): enables or disables the channel 1 transfer break interrupt. bit 3 dtie1b description 0 transfer break interrupt disabled (initial value) 1 transfer break interrupt enabled bit 1?data transfer interrupt enable 0b (dtie0b): enables or disables the channel 0 transfer break interrupt. bit 1 dtie0b description 0 transfer break interrupt disabled (initial value) 1 transfer break interrupt enabled bits 2 and 0?data transfer end interrupt enable a (dtiea): these bits enable or disable an interrupt to the cpu or dtc when transfer ends. if dtiea bit is set to 1 when dte = 0, the dmac regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the cpu or dtc. a transfer end interrupt can be canceled either by clearing the dtiea bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the dte bit to 1. bit 2?data transfer end interrupt enable 1a (dtie1a): enables or disables the channel 1 transfer end interrupt. bit 2 dtie1a description 0 transfer end interrupt disabled (initial value) 1 transfer end interrupt enabled
section 8 dma controller rev. 3.00 jan 11, 2005 page 246 of 1220 rej09b0186-0300o bit 0?data transfer end interrupt enable 0a (dtie0a): enables or disables the channel 0 transfer end interrupt. bit 0 dtie0a description 0 transfer end interrupt disabled (initial value) 1 transfer end interrupt enabled 8.4 register descriptions (3) 8.4.1 dma write enable register (dmawer) the dmac can activate the dtc with a transfer end interrupt, rewrite the channel on which the transfer ended using a dtc chain transfer, and reactivate the dtc. dmawer applies restrictions so that only specific bits of dmacr for the specific channel and also dmatcr and dmabcr can be changed to prevent inadvertent changes being made to registers other than those for the channel concerned. the restrictions applied by dmawer are valid for the dtc. figure 8.2 shows the transfer areas for activating the dtc with a channel 0a transfer end interrupt, and reactivating channel 0a. the address register and count register area is re-set by the first dtc transfer, then the control register area is re-set by the second dtc chain transfer. when re-setting the control register area, perform masking by setting bits in dmawer to prevent modification of the contents of the other channels.
section 8 dma controller rev. 3.00 jan 11, 2005 page 247 of 1220 rej09b0186-0300o dtc mar0a ioar0a etcr0a mar0b ioar0b etcr0b mar1a ioar1a etcr1a mar1b ioar1b etcr1b dmatcr dmacr0b dmacr1b dmawer dmacr0a dmacr1a dmabcr second transfer area using chain transfer first transfer area figure 8.2 areas for register re-setting by dtc (example: channel 0a) bit:76543210 dmawer : ???? we1b we1a we0b we0a initial value:00000000 r/w : ???? r/w r/w r/w r/w dmawer is an 8-bit readable/writable register that controls enabling or disabling of writes to the dmacr, dmabcr, and dmatcr by the dtc. dmawer is initialized to h'00 by a reset, and in standby mode. bits 7 to 4?reserved: these bits are always read as 0 and cannot be modified.
section 8 dma controller rev. 3.00 jan 11, 2005 page 248 of 1220 rej09b0186-0300o bit 3?write enable 1b (we1b): enables or disables writes to all bits in dmacr1b, bits 11, 7, and 3 in dmabcr, and bit 5 in dmatcr by the dtc. bit 3 we1b description 0 writes to all bits in dmacr1b, bits 11, 7, and 3 in dmabcr, and bit 5 in dmatcr are disabled (initial value) 1 writes to all bits in dmacr1b, bits 11, 7, and 3 in dmabcr, and bit 5 in dmatcr are enabled bit 2?write enable 1a (we1a): enables or disables writes to all bits in dmacr1a, and bits 10, 6, and 2 in dmabcr by the dtc. bit 2 we1a description 0 writes to all bits in dmacr1a, and bits 10, 6, and 2 in dmabcr are disabled (initial value) 1 writes to all bits in dmacr1a, and bits 10, 6, and 2 in dmabcr are enabled bit 1?write enable 0b (we0b): enables or disables writes to all bits in dmacr0b, bits 9, 5, and 1 in dmabcr, and bit 4 in dmatcr. bit 1 we0b description 0 writes to all bits in dmacr0b, bits 9, 5, and 1 in dmabcr, and bit 4 in dmatcr are disabled (initial value) 1 writes to all bits in dmacr0b, bits 9, 5, and 1 in dmabcr, and bit 4 in dmatcr are enabled bit 0?write enable 0a (we0a): enables or disables writes to all bits in dmacr0a, and bits 8, 4, and 0 in dmabcr. bit 0 we0a description 0 writes to all bits in dmacr0a, and bits 8, 4, and 0 in dmabcr are disabled (initial value) 1 writes to all bits in dmacr0a, and bits 8, 4, and 0 in dmabcr are enabled
section 8 dma controller rev. 3.00 jan 11, 2005 page 249 of 1220 rej09b0186-0300o writes by the dtc to bits 15 to 12 (fae and sae) in dmabcr are invalid regardless of the dmawer settings. these bits should be changed, if necessary, by cpu processing. in writes by the dtc to bits 7 to 4 (dte) in dmabcr, 1 can be written without first reading 0. to reactivate a channel set to full address mode, write 1 to both write enable a and write enable b for the channel to be reactivated. mar, ioar, and etcr are always write-enabled regardless of the dmawer settings. when modifying these registers, the channel for which the modification is to be made should be halted. 8.4.2 dma terminal control register (dmatcr) bit:76543210 dmatcr : ?? tee1 tee0 ???? initial value:00000000 r/w : ?? r/w r/w ???? dmatcr is an 8-bit readable/writable register that controls enabling or disabling of dmac transfer end pin output. a port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. dmatcr is initialized to h'00 by a reset, and in standby mode. bits 7 and 6?reserved: these bits are always read as 0 and cannot be modified. bit 5?transfer end enable 1 (tee1): enables or disables transfer end pin 1 ( tend1 ) output. bit 5 tee1 description 0 tend1 pin output disabled (initial value) 1 tend1 pin output enabled bit 4?transfer end enable 0 (tee0): enables or disables transfer end pin 0 ( tend0 ) output. bit 4 tee0 description 0 tend0 pin output disabled (initial value) 1 tend0 pin output enabled
section 8 dma controller rev. 3.00 jan 11, 2005 page 250 of 1220 rej09b0186-0300o the tend pins are assigned only to channel b in short address mode. the transfer end signal indicates the transfer cycle in which the transfer counter reached 0, regardless of the transfer source. an exception is block transfer mode, in which the transfer end signal indicates the transfer cycle in which the block counter reached 0. bits 3 to 0?reserved: these bits are always read as 0 and cannot be modified. 8.4.3 module stop control register (mstpcr) bit:76543210 mstpa7 mstpa6 mstpa5 mstpa4 mstpa3 mstpa2 mstpa1 mstpa0 initial value:00111111 r/w : r/w r/w r/w r/w r/w r/w r/w r/w mstpcra is an 8-bit readable/writable register that performs module stop mode control. when the mstpa7 bit in mstpcr is set to 1, the dmac operation stops at the end of the bus cycle and a transition is made to module stop mode. for details, see section 24.5, module stop mode. mstpcra is initialized to h'3f by a reset and in hardware standby mode. it is not initialized by a manual reset and in software standby mode. bit 7?module stop (mstp7): specifies the dmac module stop mode. bits 7 mstpa7 description 0 dmac module stop mode cleared (initial value) 1 dmac module stop mode set
section 8 dma controller rev. 3.00 jan 11, 2005 page 251 of 1220 rej09b0186-0300o 8.5 operation 8.5.1 transfer modes table 8.5 lists the dmac modes. table 8.5 dmac transfer modes transfer mode transfer source remarks short address mode dual address mode (1) sequential mode (2) idle mode (3) repeat mode ? tpu channel 0 to 5 compare match/input capture a interrupt ? sci transmit-data- empty interrupt ? sci reception complete interrupt ? a/d converter conversion end interrupt ? external request ? up to 4 channels can operate independently ? external request applies to channel b only ? single address mode applies to channel b only ? modes (1), (2), and (3) can also be specified for single address mode (4) single address mode full address mode (5) normal mode ? external request ? auto-request (6) block transfer mode ? tpu channel 0 to 5 compare match/input capture a interrupt ? sci transmit-data- empty interrupt ? sci reception complete interrupt ? a/d converter conversion end interrupt ? external request ? max. 2-channel operation, combining channels a and b ? with auto-request, burst mode transfer or cycle steal transfer can be selected
section 8 dma controller rev. 3.00 jan 11, 2005 page 252 of 1220 rej09b0186-0300o operation in each mode is summarized below. (1) sequential mode in response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. an interrupt request can be sent to the cpu or dtc when the specified number of transfers have been completed. one address is specified as 24 bits, and the other as 16 bits. the transfer direction is programmable. (2) idle mode in response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. an interrupt request can be sent to the cpu or dtc when the specified number of transfers have been completed. one address is specified as 24 bits, and the other as 16 bits. the transfer source address and transfer destination address are fixed. the transfer direction is programmable. (3) repeat mode in response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. when the specified number of transfers have been completed, the addresses and transfer counter are restored to their original settings, and operation is continued. no interrupt request is sent to the cpu or dtc. one address is specified as 24 bits, and the other as 16 bits. the transfer direction is programmable. (4) single address mode in response to a single transfer request, the specified number of transfers are carried out between external memory and an external device, one byte or one word at a time. unlike dual address mode, source and destination accesses are performed in parallel. therefore, either the source or the destination is an external device which can be accessed with a strobe alone, using the dack pin. one address is specified as 24 bits, and for the other, the pin is set automatically. the transfer direction is programmable. modes (1), (2) and (3) can also be specified for single address mode. (5) normal mode ? auto-request by means of register settings only, the dmac is activated, and transfer continues until the specified number of transfers have been completed. an interrupt request can be sent to the cpu or dtc when transfer is completed. both addresses are specified as 24 bits. ? cycle steal mode: the bus is released to another bus master every byte or word transfer.
section 8 dma controller rev. 3.00 jan 11, 2005 page 253 of 1220 rej09b0186-0300o ? burst mode: the bus is held and transfer continued until the specified number of transfers have been completed. ? external request in response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. an interrupt request can be sent to the cpu or dtc when the specified number of transfers have been completed. both addresses are specified as 24 bits. (6) block transfer mode in response to a single transfer request, a block transfer of the specified block size is carried out. this is repeated the specified number of times, once each time there is a transfer request. at the end of each single block transfer, one address is restored to its original setting. an interrupt request can be sent to the cpu or dtc when the specified number of block transfers have been completed. both addresses are specified as 24 bits. 8.5.2 sequential mode sequential mode can be specified by clearing the rpe bit in dmacr to 0. in sequential mode, mar is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in etcr. one address is specified by mar, and the other by ioar. the transfer direction can be specified by the dtdir bit in dmacr. table 8.6 summarizes register functions in sequential mode.
section 8 dma controller rev. 3.00 jan 11, 2005 page 254 of 1220 rej09b0186-0300o table 8.6 register functions in sequential mode function register dtdir = 0 dtdir = 1 initial setting operation 23 0 mar source address register destination address register start address of transfer destination or transfer source incremented/ decremented every transfer 23 0 ioar 15 h'ff destination address register source address register start address of transfer source or transfer destination fixed 0 15 etcr transfer counter number of transfers decremented every transfer; transfer ends when count reaches h'0000 legend: mar: memory address register ioar: i/o address register etcr: transfer count register dtdir: data transfer direction bit mar specifies the start address of the transfer source or transfer destination as 24 bits. mar is incremented or decremented by 1 or 2 each time a byte or word is transferred. ioar specifies the lower 16 bits of the other address. the 8 bits above ioar have a value of h'ff.
section 8 dma controller rev. 3.00 jan 11, 2005 page 255 of 1220 rej09b0186-0300o figure 8.3 illustrates operation in sequential mode. address t address b transfer ioar 1 byte or word transfer performed in response to 1 transfer request legend: address t = l address b = l + ( ? 1) dtid (2 dtsz (n ? 1)) where : l = value set in mar n = value set in etcr figure 8.3 operation in sequential mode the number of transfers is specified as 16 bits in etcr. etcr is decremented by 1 each time a transfer is executed, and when its value reaches h'0000, the dte bit is cleared and transfer ends. if the dtie bit is set to 1 at this time, an interrupt request is sent to the cpu or dtc. the maximum number of transfers, when h'0000 is set in etcr, is 65,536. transfer requests (activation sources) consist of a/d converter conversion end interrupts, external requests, sci transmission complete and reception complete interrupts, and tpu channel 0 to 5 compare match/input capture a interrupts. external requests can be set for channel b only. figure 8.4 shows an example of the setting procedure for sequential mode.
section 8 dma controller rev. 3.00 jan 11, 2005 page 256 of 1220 rej09b0186-0300o sequential mode setting set dmabcrh set transfer source and transfer destination addresses set number of transfers set dmacr read dmabcrl set dmabcrl sequential mode [1] [2] [3] [4] [5] [6] [1] set each bit in dmabcrh. clear the fae bit to 0 to select short address mode. specify enabling or disabling of internal interrupt clearing with the dta bit. [2] set the transfer source address and transfer destination address in mar and ioar. [3] set the number of transfers in etcr. [4] set each bit in dmacr. set the transfer data size with the dtsz bit. specify whether mar is to be incremented or decremented with the dtid bit. clear the rpe bit to 0 to select sequential mode. specify the transfer direction with the dtdir bit. select the activation source with bits dtf3 to dtf0. [5] read the dte bit in dmabcrl as 0. [6] set each bit in dmabcrl. specify enabling or disabling of transfer end interrupts with the dtie bit. set the dte bit to 1 to enable transfer. figure 8.4 example of sequential mode setting procedure
section 8 dma controller rev. 3.00 jan 11, 2005 page 257 of 1220 rej09b0186-0300o 8.5.3 idle mode idle mode can be specified by setting the rpe bit and dtie bit in dmacr to 1. in idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in etcr. one address is specified by mar, and the other by ioar. the transfer direction can be specified by the dtdir bit in dmacr. table 8.7 summarizes register functions in idle mode. table 8.7 register functions in idle mode function register dtdir = 0 dtdir = 1 initial setting operation 23 0 mar source address register destination address register start address of transfer destination or transfer source fixed 23 0 ioar 15 h'ff destination address register source address register start address of transfer source or transfer destination fixed 0 15 etcr transfer counter number of transfers decremented every transfer; transfer ends when count reaches h'0000 legend: mar: memory address register ioar: i/o address register etcr: transfer count register dtdir: data transfer direction bit mar specifies the start address of the transfer source or transfer destination as 24 bits. mar is neither incremented nor decremented each time a byte or word is transferred. ioar specifies the lower 16 bits of the other address. the 8 bits above ioar have a value of h'ff.
section 8 dma controller rev. 3.00 jan 11, 2005 page 258 of 1220 rej09b0186-0300o figure 8.5 illustrates operation in idle mode. transfer ioar 1 byte or word transfer performed in response to 1 transfer request mar figure 8.5 operation in idle mode the number of transfers is specified as 16 bits in etcr. etcr is decremented by 1 each time a transfer is executed, and when its value reaches h'0000, the dte bit is cleared and transfer ends. if the dtie bit is set to 1 at this time, an interrupt request is sent to the cpu or dtc. the maximum number of transfers, when h'0000 is set in etcr, is 65,536. transfer requests (activation sources) consist of a/d converter conversion end interrupts, external requests, sci transmission complete and reception complete interrupts, and tpu channel 0 to 5 compare match/input capture a interrupts. external requests can be set for channel b only. when the dmac is used in single address mode, only channel b can be set.
section 8 dma controller rev. 3.00 jan 11, 2005 page 259 of 1220 rej09b0186-0300o figure 8.6 shows an example of the setting procedure for idle mode. idle mode setting set dmabcrh set transfer source and transfer destination addresses set number of transfers set dmacr read dmabcrl set dmabcrl idle mode [1] [2] [3] [4] [5] [6] [1] set each bit in dmabcrh. clear the fae bit to 0 to select short address mode. specify enabling or disabling of internal interrupt clearing with the dta bit. [2] set the transfer source address and transfer destination address in mar and ioar. [3] set the number of transfers in etcr. [4] set each bit in dmacr. set the transfer data size with the dtsz bit. specify whether mar is to be incremented or decremented with the dtid bit. set the rpe bit to 1. specify the transfer direction with the dtdir bit. select the activation source with bits dtf3 to dtf0. [5] read the dte bit in dmabcrl as 0. [6] set each bit in dmabcrl. set the dtie bit to 1. set the dte bit to 1 to enable transfer. figure 8.6 example of idle mode setting procedure
section 8 dma controller rev. 3.00 jan 11, 2005 page 260 of 1220 rej09b0186-0300o 8.5.4 repeat mode repeat mode can be specified by setting the rpe bit in dmacr to 1, and clearing the dtie bit to 0. in repeat mode, mar is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in etcr. on completion of the specified number of transfers, mar and etcrl are automatically restored to their original settings and operation continues. one address is specified by mar, and the other by ioar. the transfer direction can be specified by the dtdir bit in dmacr. table 8.8 summarizes register functions in repeat mode. table 8.8 register functions in repeat mode function register dtdir = 0 dtdir = 1 initial setting operation 23 0 mar source address register destination address register start address of transfer destination or transfer source incremented/ decremented every transfer. initial setting is restored when value reaches h'0000 23 0 ioar 15 h'ff destination address register source address register start address of transfer source or transfer destination fixed 0 etcrh 7 0 etcrl 7 holds number of transfers transfer counter number of transfers number of transfers fixed decremented every transfer. loaded with etcrh value when count reaches h'00 legend: mar: memory address register ioar: i/o address register etcr: transfer count register dtdir: data transfer direction bit
section 8 dma controller rev. 3.00 jan 11, 2005 page 261 of 1220 rej09b0186-0300o mar specifies the start address of the transfer source or transfer destination as 24 bits. mar is incremented or decremented by 1 or 2 each time a byte or word is transferred. ioar specifies the lower 16 bits of the other address. the 8 bits above ioar have a value of h'ff. the number of transfers is specified as 8 bits by etcrh and etcrl. the maximum number of transfers, when h'00 is set in both etcrh and etcrl, is 256. in repeat mode, etcrl functions as the transfer counter, and etcrh is used to hold the number of transfers. etcrl is decremented by 1 each time a transfer is executed, and when its value reaches h'00, it is loaded with the value in etcrh. at the same time, the value set in mar is restored in accordance with the values of the dtsz and dtid bits in dmacr. the mar restoration operation is as shown below. mar = mar ? (?1) dtid 2 dtsz etcrh the same value should be set in etcrh and etcrl. in repeat mode, operation continues until the dte bit is cleared. to end the transfer operation, therefore, you should clear the dte bit to 0. a transfer end interrupt request is not sent to the cpu or dtc. by setting the dte bit to 1 again after it has been cleared, the operation can be restarted from the transfer after that terminated when the dte bit was cleared.
section 8 dma controller rev. 3.00 jan 11, 2005 page 262 of 1220 rej09b0186-0300o figure 8.7 illustrates operation in repeat mode. address t address b transfer ioar 1 byte or word transfer performed in response to 1 transfer request legend: address t = l address b = l + ( ? 1) dtid (2 dtsz (n ? 1)) where : l = value set in mar n = value set in etcr figure 8.7 operation in repeat mode transfer requests (activation sources) consist of a/d converter conversion end interrupts, external requests, sci transmission complete and reception complete interrupts, and tpu channel 0 to 5 compare match/input capture a interrupts. external requests can be set for channel b only.
section 8 dma controller rev. 3.00 jan 11, 2005 page 263 of 1220 rej09b0186-0300o figure 8.8 shows an example of the setting procedure for repeat mode. repeat mode setting set dmabcrh set transfer source and transfer destination addresses set number of transfers set dmacr read dmabcrl set dmabcrl repeat mode [1] [2] [3] [4] [5] [6] [1] set each bit in dmabcrh. clear the fae bit to 0 to select short address mode. specify enabling or disabling of internal interrupt clearing with the dta bit. [2] set the transfer source address and transfer destination address in mar and ioar. [3] set the number of transfers in both etcrh and etcrl. [4] set each bit in dmacr. set the transfer data size with the dtsz bit. specify whether mar is to be incremented or decremented with the dtid bit. set the rpe bit to 1. specify the transfer direction with the dtdir bit. select the activation source with bits dtf3 to dtf0. [5] read the dte bit in dmabcrl as 0. [6] set each bit in dmabcrl. clear the dtie bit to 0. set the dte bit to 1 to enable transfer. figure 8.8 example of repeat mode setting procedure
section 8 dma controller rev. 3.00 jan 11, 2005 page 264 of 1220 rej09b0186-0300o 8.5.5 single address mode single address mode can only be specified for channel b. this mode can be specified by setting the sae bit in dmabcr to 1 in short address mode. one address is specified by mar, and the other is set automatically to the data transfer acknowledge pin ( dack ). the transfer direction can be specified by the dtdir in dmacr. table 8.9 summarizes register functions in single address mode. table 8.9 register functions in single address mode function register dtdir = 0 dtdir = 1 initial setting operation 23 0 mar source address register destination address register start address of transfer destination or transfer source * dack pin write strobe read strobe (set automatically by sae bit; ioar is invalid) strobe for external device 0 15 etcr transfer counter number of transfers * legend: mar: memory address register ioar: i/o address register etcr: transfer count register dtdir: data transfer direction bit dack : data transfer acknowledge note: * see the operation descriptions in sections 8.5.2, sequential mode, 8.5.3, idle mode, and 8.5.4, repeat mode. mar specifies the start address of the transfer source or transfer destination as 24 bits. ioar is invalid; in its place the strobe for external devices ( dack ) is output.
section 8 dma controller rev. 3.00 jan 11, 2005 page 265 of 1220 rej09b0186-0300o figure 8.9 illustrates operation in single address mode (when sequential mode is specified). address t address b transfer dac k 1 byte or word transfer performed in response to 1 transfer request legend: address t = l address b = l + ( ? 1) dtid (2 dtsz (n ? 1)) where : l = value set in mar n = value set in etcr figure 8.9 operation in single address mode (when sequential mode is specified)
section 8 dma controller rev. 3.00 jan 11, 2005 page 266 of 1220 rej09b0186-0300o figure 8.10 shows an example of the setting procedure for single address mode (when sequential mode is specified). single address mode setting set dmabcrh set transfer source and transfer destination addresses set number of transfers set dmacr read dmabcrl set dmabcrl single address mode [1] [2] [3] [4] [5] [6] [1] set each bit in dmabcrh. clear the fae bit to 0 to select short address mode. set the sae bit to 1 to select single address mode. specify enabling or disabling of internal interrupt clearing with the dta bit. [2] set the transfer source address/transfer destination address in mar. [3] set the number of transfers in etcr. [4] set each bit in dmacr. set the transfer data size with the dtsz bit. specify whether mar is to be incremented or decremented with the dtid bit. clear the rpe bit to 0 to select sequential mode. specify the transfer direction with the dtdir bit. select the activation source with bits dtf3 to dtf0. [5] read the dte bit in dmabcrl as 0. [6] set each bit in dmabcrl. specify enabling or disabling of transfer end interrupts with the dtie bit. set the dte bit to 1 to enable transfer. figure 8.10 example of single address mode setting procedure (when sequential mode is specified)
section 8 dma controller rev. 3.00 jan 11, 2005 page 267 of 1220 rej09b0186-0300o 8.5.6 normal mode in normal mode, transfer is performed with channels a and b used in combination. normal mode can be specified by setting the fae bit in dmabcr to 1 and clearing the blke bit in dmacra to 0. in normal mode, mar is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in etcra. the transfer source is specified by mara, and the transfer destination by marb. table 8.10 summarizes register functions in normal mode. table 8.10 register functions in normal mode register function initial setting operation 23 0 mara source address register start address of transfer source incremented/decremented every transfer, or fixed 23 0 marb destination address register start address of transfer destination incremented/decremented every transfer, or fixed 0 15 etcra transfer counter number of transfers decremented every transfer; transfer ends when count reaches h'0000 legend: mara: memory address register a marb: memory address register b etcra: transfer count register a mara and marb specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. mar can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. incrementing, decrementing, or holding a fixed value can be set separately for mara and marb. the number of transfers is specified by etcra as 16 bits. etcra is decremented each time a transfer is performed, and when its value reaches h'0000 the dte bit is cleared and transfer ends. if the dtie bit is set to 1 at this time, an interrupt request is sent to the cpu or dtc. the maximum number of transfers, when h'0000 is set in etcra, is 65,536.
section 8 dma controller rev. 3.00 jan 11, 2005 page 268 of 1220 rej09b0186-0300o figure 8.11 illustrates operation in normal mode. address t a address b a transfer address t b legend: address address address address where : address b b = l a = l b = l a + saide ( ? 1) said (2 dtsz (n ? 1)) = l b + daide ( ? 1) daid (2 dtsz (n ? 1)) = value set in mara = value set in marb = value set in etcra t a t b b a b b l a l b n figure 8.11 operation in normal mode transfer requests (activation sources) are external requests and auto-requests. with auto-request, the dmac is only activated by register setting, and the specified number of transfers are performed automatically. with auto-request, cycle steal mode or burst mode can be selected. in cycle steal mode, the bus is released to another bus master each time a transfer is performed. in burst mode, the bus is held continuously until transfer ends.
section 8 dma controller rev. 3.00 jan 11, 2005 page 269 of 1220 rej09b0186-0300o for setting details, see section 8.3.4, dma controller register (dmacr). figure 8.12 shows an example of the setting procedure for normal mode. normal mode setting set dmabcrh set transfer source and transfer destination addresses set number of transfers set dmacr read dmabcrl set dmabcrl normal mode [1] [2] [3] [4] [5] [6] [1] set each bit in dmabcrh. set the fae bit to 1 to select full address mode. specify enabling or disabling of internal interrupt clearing with the dta bit. [2] set the transfer source address in mara, and the transfer destination address in marb. [3] set the number of transfers in etcra. [4] set each bit in dmacra and dmacrb. set the transfer data size with the dtsz bit. specify whether mara is to be incremented, decremented, or fixed, with the said and saide bits. clear the blke bit to 0 to select normal mode. specify whether marb is to be incremented, decremented, or fixed, with the daid and daide bits. select the activation source with bits dtf3 to dtf0. [5] read dte = 0 and dtme = 0 in dmabcrl. [6] set each bit in dmabcrl. specify enabling or disabling of transfer end interrupts with the dtie bit. set both the dtme bit and the dte bit to 1 to enable transfer. figure 8.12 example of normal mode setting procedure
section 8 dma controller rev. 3.00 jan 11, 2005 page 270 of 1220 rej09b0186-0300o 8.5.7 block transfer mode in block transfer mode, transfer is performed with channels a and b used in combination. block transfer mode can be specified by setting the fae bit in dmabcr and the blke bit in dmacra to 1. in block transfer mode, a transfer of the specified block size is carried out in response to a single transfer request, and this is executed the specified number of times. the transfer source is specified by mara, and the transfer destination by marb. either the transfer source or the transfer destination can be selected as a block area (an area composed of a number of bytes or words). table 8.11 summarizes register functions in block transfer mode. table 8.11 register functions in block transfer mode register function initial setting operation 23 0 mara source address register start address of transfer source incremented/decremented every transfer, or fixed 23 0 marb destination address register start address of transfer destination incremented/decremented every transfer, or fixed 0 etcrah 7 0 etcral 7 holds block size block size counter block size block size fixed decremented every transfer; etcrh value copied when count reaches h'00 15 0 etcrb block transfer counter number of block transfers decremented every block transfer; transfer ends when count reaches h'0000 legend: mara: memory address register a marb: memory address register b etcra: transfer count register a etcrb: transfer count register b mara and marb specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. mar can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed.
section 8 dma controller rev. 3.00 jan 11, 2005 page 271 of 1220 rej09b0186-0300o incrementing, decrementing, or holding a fixed value can be set separately for mara and marb. whether a block is to be designated for mara or for marb is specified by the blkdir bit in dmacra. to specify the number of transfers, if m is the size of one block (where m = 1 to 256) and n transfers are to be performed (where n = 1 to 65,536), m is set in both etcrah and etcral, and n in etcrb. figure 8.13 illustrates operation in block transfer mode when marb is designated as a block area. address t a address b a transfer address t b address b b 1st block 2nd block nth block block area consecutive transfer of m bytes or words is performed in response to one request legend: address address address address where : = l a = l b = l a + saide ( ? 1) said (2 dtsz (m n ? 1)) = l b + daide ( ? 1) daid (2 dtsz (n ? 1)) = value set in mara = value set in marb = value set in etcrb = value set in etcrah and etcral t a t b b a b b l a l b n m figure 8.13 operation in block transfer mode (blkdir = 0)
section 8 dma controller rev. 3.00 jan 11, 2005 page 272 of 1220 rej09b0186-0300o figure 8.14 illustrates operation in block transfer mode when mara is designated as a block area. address t b address b b transfer address t a address b a 1st block 2nd block nth block block area consecutive transfer of m bytes or words is performed in response to one request legend: address address address address where : = l a = l b = l a + saide ( ? 1) said (2 dtsz (n ? 1)) = l b + daide ( ? 1) daid (2 dtsz (m n ? 1)) = value set in mara = value set in marb = value set in etcrb = value set in etcrah and etcral t a t b b a b b l a l b n m figure 8.14 operation in block transfer mode (blkdir = 1)
section 8 dma controller rev. 3.00 jan 11, 2005 page 273 of 1220 rej09b0186-0300o etcral is decremented by 1 each time a byte or word transfer is performed. in response to a single transfer request, burst transfer is performed until the value in etcral reaches h'00. etcral is then loaded with the value in etcrah. at this time, the value in the mar register for which a block designation has been given by the blkdir bit in dmacra is restored in accordance with the dtsz, said/daid, and saide/daide bits in dmacr. etcrb is decremented by 1 every block transfer, and when the count reaches h'0000 the dte bit is cleared and transfer ends. if the dtie bit is set to 1 at this point, an interrupt request is sent to the cpu or dtc. figure 8.15 shows the operation flow in block transfer mode.
section 8 dma controller rev. 3.00 jan 11, 2005 page 274 of 1220 rej09b0186-0300o acquire bus etcral = etcral ? 1 transfer request? etcral = h'00 release bus blkdir = 0 etcral = etcrah etcrb = etcrb ? 1 etcrb = h'0000 start (dte = dtme = 1) read address specified by mara mara = mara + saide ( ? 1) said 2 dtsz write to address specified by marb marb = marb + daide ( ? 1) daid 2 dtsz marb = marb ? daide ( ? 1) daid 2 dtsz etcrah mara = mara ? saide ( ? 1) said 2 dtsz etcrah no yes no yes no yes no yes clear dte bit to 0 to end transfer figure 8.15 operation flow in block transfer mode
section 8 dma controller rev. 3.00 jan 11, 2005 page 275 of 1220 rej09b0186-0300o transfer requests (activation sources) consist of a/d converter conversion end interrupts, external requests, sci transmission complete and reception complete interrupts, and tpu channel 0 to 5 compare match/input capture a interrupts. for details, see section 8.3.4, dma control register (dmacr). figure 8.16 shows an example of the setting procedure for block transfer mode. block transfer mode setting set dmabcrh set transfer source and transfer destination addresses set number of transfers set dmacr read dmabcrl set dmabcrl block transfer mode [1] [2] [3] [4] [5] [6] [1] set each bit in dmabcrh. set the fae bit to 1 to select full address mode. specify enabling or disabling of internal interrupt clearing with the dta bit. [2] set the transfer source address in mara, and the transfer destination address in marb. [3] set the block size in both etcrah and etcral. set the number of transfers in etcrb. [4] set each bit in dmacra and dmacrb. set the transfer data size with the dtsz bit. specify whether mara is to be incremented, decremented, or fixed, with the said and saide bits. set the blke bit to 1 to select block transfer mode. specify whether the transfer source or the transfer destination is a block area with the blkdir bit. specify whether marb is to be incremented, decremented, or fixed, with the daid and daide bits. select the activation source with bits dtf3 to dtf0. [5] read dte = 0 and dtme = 0 in dmabcrl. [6] set each bit in dmabcrl. specify enabling or disabling of transfer end interrupts to the cpu with the dtie bit. set both the dtme bit and the dte bit to 1 to enable transfer. figure 8.16 example of block transfer mode setting procedure
section 8 dma controller rev. 3.00 jan 11, 2005 page 276 of 1220 rej09b0186-0300o 8.5.8 dmac activation sources dmac activation sources consist of internal interrupts, external requests, and auto-requests. the activation sources that can be specified depend on the transfer mode and the channel, as shown in table 8.12. table 8.12 dmac activation sources short address mode full address mode activation source channels 0a and 1a channels 0b and 1b normal mode block transfer mode adi o o o txi0 o o o rxi0 o o o txi1 o o o rxi1 o o o tgi0a o o o tgi1a o o o tgi2a o o o tgi3a o o o tgi4a o o o internal interrupts tgi5a o o o dreq pin falling edge input ooo external requests dreq pin low-level input ooo auto-request o legend: o : can be specified : cannot be specified (1) activation by internal interrupt an interrupt request selected as a dmac activation source can be sent simultaneously to the cpu and dtc. for details, see section 5, interrupt controller. with activation by an internal interrupt, the dmac accepts the request independently of the interrupt controller. consequently, interrupt controller priority settings are not accepted.
section 8 dma controller rev. 3.00 jan 11, 2005 page 277 of 1220 rej09b0186-0300o if the dmac is activated by a cpu interrupt source or an interrupt source that is not used as a dtc activation source (dta = 1), the interrupt source flag is cleared automatically by the dma transfer. with adi, txi, and rxi interrupts, however, the interrupt source flag is not cleared unless the prescribed register is accessed in a dma transfer. if the same interrupt is used as an activation source for more than one channel, the interrupt request flag is cleared when the highest- priority channel is activated first. transfer requests for other channels are held pending in the dmac, and activation is carried out in order of priority. when dte = 0, such as after completion of a transfer, a request from the selected activation source is not sent to the dmac, regardless of the dta bit. in this case, the relevant interrupt request is sent to the cpu or dtc. in case of overlap with a cpu interrupt source or dtc activation source (dta = 0), the interrupt request flag is not cleared by the dmac. (2) activation by external request if an external request ( dreq pin) is specified as an activation source, the relevant port should be set to input mode in advance. level sensing or edge sensing can be used for external requests. external request operation in normal mode (short address mode or full address mode) is described below. when edge sensing is selected, a 1-byte or 1-word transfer is executed each time a high-to-low transition is detected on the dreq pin. the next transfer may not be performed if the next edge is input before transfer is completed. when level sensing is selected, the dmac stands by for a transfer request while the dreq pin is held high. while the dreq pin is held low, transfers continue in succession, with the bus being released each time a byte or word is transferred. if the dreq pin goes high in the middle of a transfer, the transfer is interrupted and the dmac stands by for a transfer request. (3) activation by auto-request auto-request activation is performed by register setting only, and transfer continues to the end. with auto-request activation, cycle steal mode or burst mode can be selected. in cycle steal mode, the dmac releases the bus to another bus master each time a byte or word is transferred. dma and cpu cycles usually alternate.
section 8 dma controller rev. 3.00 jan 11, 2005 page 278 of 1220 rej09b0186-0300o in burst mode, the dmac keeps possession of the bus until the end of the transfer, and transfer is performed continuously. (4) single address mode the dmac can operate in dual address mode in which read cycles and write cycles are separate cycles, or single address mode in which read and write cycles are executed in parallel. in dual address mode, transfer is performed with the source address and destination address specified separately. in single address mode, on the other hand, transfer is performed between external space in which either the transfer source or the transfer destination is specified by an address, and an external device for which selection is performed by means of the dack strobe, without regard to the address. figure 8.17 shows the data bus in single address mode. external memory external device (read) (write) rd hwr , lwr a23 to a0 h8s/2643 d15 to d0 (high impedance) dack address bus data bus figure 8.17 data bus in single address mode when using the dmac for single address mode reading, transfer is performed from external memory to the external device, and the dack pin functions as a write strobe for the external device. when using the dmac for single address mode writing, transfer is performed from the external device to external memory, and the dack pin functions as a read strobe for the external device. since there is no directional control for the external device, one or other of the above single directions should be used.
section 8 dma controller rev. 3.00 jan 11, 2005 page 279 of 1220 rej09b0186-0300o bus cycles in single address mode are in accordance with the settings of the bus controller for the external memory area. on the external device side, dack is output in synchronization with the address strobe. for details of bus cycles, see section 8.5.11, dmac bus cycles (single address mode). do not specify internal space for transfer addresses in single address mode. 8.5.9 basic dmac bus cycles an example of the basic dmac bus cycle timing is shown in figure 8.18. in this example, word- size transfer is performed from 16-bit , 2-state access space to 8-bit, 3-state access space. when the bus is transferred from the cpu to the dmac, a source address read and destination address write are performed. the bus is not released in response to another bus request, etc., between these read and write operations. as with cpu cycles, dma cycles conform to the bus controller settings. address bus dmac cycle (1-word transfer) rd lwr hwr source address destination address cpu cycle cpu cycle t 1 t 2 t 3 t 1 t 2 t 3 t 1 t 2 figure 8.18 example of dma transfer bus timing the address is not output to the external address bus in an access to on-chip memory or an internal i/o register.
section 8 dma controller rev. 3.00 jan 11, 2005 page 280 of 1220 rej09b0186-0300o 8.5.10 dmac bus cycles (dual address mode) (1) short address mode figure 8.19 shows a transfer example in which tend output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal i/o space. dma read address bus rd lwr tend hwr bus release last transfer cycle dma write dma dead dma read dma write dma read dma write bus release bus release bus release figure 8.19 example of short address mode transfer a one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. while the bus is released one or more bus cycles are inserted by the cpu or dtc. in the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state dma dead cycle is inserted after the dma write cycle. in repeat mode, when tend output is enabled, tend output goes low in the transfer cycle in which the transfer counter reaches 0.
section 8 dma controller rev. 3.00 jan 11, 2005 page 281 of 1220 rej09b0186-0300o (2) full address mode (cycle steal mode) figure 8.20 shows a transfer example in which tend output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. dma read address bus rd lwr tend hwr bus release last transfer cycle dma write dma read dma write dma read dma write dma dead bus release bus release bus release figure 8.20 example of full address mode (cycle steal) transfer a one-byte or one-word transfer is performed, and after the transfer the bus is released. while the bus is released one bus cycle is inserted by the cpu or dtc. in the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state dma dead cycle is inserted after the dma write cycle.
section 8 dma controller rev. 3.00 jan 11, 2005 page 282 of 1220 rej09b0186-0300o (3) full address mode (burst mode) figure 8.21 shows a transfer example in which tend output is enabled and word-size full address mode transfer (burst mode) is performed from external 16-bit, 2-state access space to external 16- bit, 2-state access space. dma read address bus rd lwr tend hwr bus release dma write dma dead dma read dma write dma read dma write bus release burst transfer last transfer cycle figure 8.21 example of full address mode (burst mode) transfer in burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. in the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state dma dead cycle is inserted after the dma write cycle. if a request from another higher-priority channel is generated after burst transfer starts, that channel has to wait until the burst transfer ends. if an nmi is generated while a channel designated for burst transfer is in the transfer enabled state, the dtme bit is cleared and the channel is placed in the transfer disabled state. if burst transfer has already been activated inside the dmac, the bus is released on completion of a one-byte or one-word transfer within the burst transfer, and burst transfer is suspended. if the last transfer cycle of the burst transfer has already been activated inside the dmac, execution continues to the end of the transfer even if the dtme bit is cleared.
section 8 dma controller rev. 3.00 jan 11, 2005 page 283 of 1220 rej09b0186-0300o (4) full address mode (block transfer mode) figure 8.22 shows a transfer example in which tend output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space. dma read address bus rd lwr tend hwr bus release block transfer last block transfer dma write dma read dma write dma dead dma read dma write dma read dma write dma dead bus release bus release figure 8.22 example of full address mode (block transfer mode) transfer a one-block transfer is performed for one transfer request, and after the transfer the bus is released. while the bus is released, one or more bus cycles are inserted by the cpu or dtc. in the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a one- state dma dead cycle is inserted after the dma write cycle. one block is transmitted wit hout interruption. nmi generation does not affect block transfer operation.
section 8 dma controller rev. 3.00 jan 11, 2005 page 284 of 1220 rej09b0186-0300o (5) dreq pin falling edge activation timing set the dta bit for the channel for which the dreq pin is selected to 1. figure 8.23 shows an example of dreq pin falling edge activated normal mode transfer. [1] [2] [5] [3] [6] [4] [7] note: in write data buffer mode, bus breaks from [ 2 ] to [ 7 ] ma y be hidden, and not visible. acceptance after transfer enabling; the dreq pin low level is sampled on the rising edge of , and the request is held. the request is cleared at the next bus break, and activation is started in the dmac. start of dma cycle; dreq pin high level sampling on the rising edge of starts. when the dreq pin high level has been sampled, acceptance is resumed after the write cycle is completed. (as in [1], the dreq pin low level is sampled on the rising edge of , and the request is held.) dma read address bus dreq idle write idle bus release dma control channel write idle transfer source request minimum of 2 cycles [1] [3] [2] [4] [6] [5] [7] acceptance resumes acceptance resumes dma write bus release dma read dma write bus release request minimum of 2 cycles transfer destination transfer source transfer destination request clear period request clear period read read figure 8.23 example of dreq pin falling edge activated normal mode transfer dreq pin sampling is performed every cycle, with the rising edge of the next cycle after the end of the dmabcr write cycle for setting the transfer enabled state as the starting point. when the dreq pin low level is sampled while acceptance by means of the dreq pin is possible, the request is held in the dmac. then, when activation is initiated in the dmac, the request is cleared, and dreq pin high level sampling for edge detection is started. if dreq pin high level sampling has been completed by the time the dma write cycle ends, acceptance resumes after the end of the write cycle, dreq pin low level sampling is performed again, and this operation is repeated until the transfer ends.
section 8 dma controller rev. 3.00 jan 11, 2005 page 285 of 1220 rej09b0186-0300o figure 8.24 shows an example of dreq pin falling edge activated block transfer mode transfer. [1] [2] [5] [3] [6] [4] [7] note: in write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. acceptance after transfer enabling; the dreq pin low level is sampled on the rising edge of , and the request is held. the request is cleared at the next bus break, and activation is started in the dmac. start of dma cycle; dreq pin high level sampling on the rising edge of starts. when the dreq pin high level has been sampled, acceptance is resumed after the dead cycle is completed. (as in [1], the dreq pin low level is sampled on the rising edge of , and the request is held.) dma read address bus dreq idle write bus release dma control channel write transfer source request minimun of 2 cycles [1] [3] [2] [4] [6] [5] [7] acceptance resumes dma dead 1 block transfer idle dead dead dma write bus release dma read dma write dma dead bus release transfer source transfer destination request clear period minimun of 2 cycles request acceptance resumes 1 block transfer request clear period read read transfer destination idle figure 8.24 example of dreq pin falling edge activated block transfer mode transfer dreq pin sampling is performed every cycle, with the rising edge of the next cycle after the end of the dmabcr write cycle for setting the transfer enabled state as the starting point. when the dreq pin low level is sampled while acceptance by means of the dreq pin is possible, the request is held in the dmac. then, when activation is initiated in the dmac, the request is cleared, and dreq pin high level sampling for edge detection is started. if dreq pin high level sampling has been completed by the time the dma dead cycle ends, acceptance resumes after the end of the dead cycle, dreq pin low level sampling is performed again, and this operation is repeated until the transfer ends.
section 8 dma controller rev. 3.00 jan 11, 2005 page 286 of 1220 rej09b0186-0300o (6) dreq level activation timing (normal mode) set the dta bit for the channel for which the dreq pin is selected to 1. figure 8.25 shows an example of dreq level activated normal mode transfer. [1] [2] [5] [3] [6] [4] [7] note: in write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. acceptance after transfer enabling; the dreq pin low level is sampled on the rising edge of , and the request is held. the request is cleared at the next bus break, and activation is started in the dmac. the dma cycle is started. acceptance is resumed after the write cycle is completed. (as in [1], the dreq pin low level is sampled on the rising edge of , and the request is held.) dma read dma write address bus dreq idle write idle bus release dma control channel write idle transfer source bus release dma read dma write bus release request minimum of 2 cycles [1] [3] [2] minimum of 2 cycles [4] [6] [5] [7] acceptance resumes acceptance resumes transfer destination transfer source transfer destination request read request clear period read request clear period figure 8.25 example of dreq level activated normal mode transfer dreq pin sampling is performed every cycle, with the rising edge of the next cycle after the end of the dmabcr write cycle for setting the transfer enabled state as the starting point. when the dreq pin low level is sampled while acceptance by means of the dreq pin is possible, the request is held in the dmac. then, when activation is initiated in the dmac, the request is cleared. after the end of the write cycle, acceptance resumes, dreq pin low level sampling is performed again, and this operation is repeated until the transfer ends.
section 8 dma controller rev. 3.00 jan 11, 2005 page 287 of 1220 rej09b0186-0300o figure 8.26 shows an example of dreq level activated block transfer mode transfer. [1] [2] [5] [3] [6] [4] [7] note: in write data buffer mode, bus breaks from [ 2 ] to [ 7 ] ma y be hidden, and not visible. acceptance after transfer enabling; the dreq pin low level is sampled on the rising edge of , and the request is held. the request is cleared at the next bus break, and activation is started in the dmac. the dma cycle is started. acceptance is resumed after the dead cycle is completed. (as in [1], the dreq pin low level is sampled on the rising edge of , and the request is held.) dma read dma right address bus dreq idle write bus release dma control channel write transfer source request [1] [3] [2] [4] [6] [5] [7] acceptance resumes dma dead bus release dma read dma right dma dead bus release 1 block transfer idle dead dead 1 block transfer acceptance resumes request minimum of 2 cycles transfer destination transfer source transfer destination minimum of 2 cycles read request clear period read request clear period idle figure 8.26 example of dreq level activated block transfer mode transfer dreq pin sampling is performed every cycle, with the rising edge of the next cycle after the end of the dmabcr write cycle for setting the transfer enabled state as the starting point. when the dreq pin low level is sampled while acceptance by means of the dreq pin is possible, the request is held in the dmac. then, when activation is initiated in the dmac, the request is cleared. after the end of the dead cycle, acceptance resumes, dreq pin low level sampling is performed again, and this operation is repeated until the transfer ends.
section 8 dma controller rev. 3.00 jan 11, 2005 page 288 of 1220 rej09b0186-0300o 8.5.11 dmac bus cycles (single address mode) (1) single address mode (read) figure 8.27 shows a transfer example in which tend output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. dma read address bus dma dead rd dack tend bus release dma read dma read dma read bus release bus release bus release bus releas e last transfer c y cle figure 8.27 example of single address mode (byte read) transfer
section 8 dma controller rev. 3.00 jan 11, 2005 page 289 of 1220 rej09b0186-0300o figure 8.28 shows a transfer example in which tend output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. dma read address bus dma read dma read dma dead rd tend dack bus release bus release bus release bus release last transfer cycle figure 8.28 example of single address mode (word read) transfer a one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. while the bus is released, one or more bus cycles are inserted by the cpu or dtc. in the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state dma dead cycle is inserted after the dma write cycle.
section 8 dma controller rev. 3.00 jan 11, 2005 page 290 of 1220 rej09b0186-0300o (2) single address mode (write) figure 8.29 shows a transfer example in which tend output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. dma write address bus dma dead hwr dack tend bus release lwr dma write dma write dma write bus release bus release bus release bus release last transfer cycle figure 8.29 example of single address mode (byte write) transfer
section 8 dma controller rev. 3.00 jan 11, 2005 page 291 of 1220 rej09b0186-0300o figure 8.30 shows a transfer example in which tend output is enabled and word-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. dma write address bus dma write dma write dma dead hwr tend dack bus release lwr bus release bus release bus release last transfer cycle figure 8.30 example of single address mode (word write) transfer a one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. while the bus is released one or more bus cycles are inserted by the cpu or dtc. in the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state dma dead cycle is inserted after the dma write cycle.
section 8 dma controller rev. 3.00 jan 11, 2005 page 292 of 1220 rej09b0186-0300o (3) dreq pin falling edge activation timing set the dta bit for the channel for which the dreq pin is selected to 1. figure 8.31 shows an example of dreq pin falling edge activated single address mode transfer. dreq bus release dma single dma single address bus dma control channel [2] dack transfer source/ destination idle idle idle single single [1] [3] [5] [4] [6] [7] acceptance resumes acceptance resumes bus release bus release transfer source/ destination request request minimum of 2 cycles minimum of 2 cycles request clear period request clear period [1] [2] [5] [3] [6] [4] [7] acceptance after transfer enabling; the dreq pin low level is sampled on the rising edge of , and the request is held. the request is cleared at the next bus break, and activation is started in the dmac. start of dma cycle; dreq pin high level sampling on the rising edge of starts. when the dreq pin high level has been sampled, acceptance is resumed after the single cycle is completed. (as in [1], the dreq pin low level is sampled on the rising edge of , and the request is held.) note: in write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. figure 8.31 example of dreq pin falling edge activated single address mode transfer dreq pin sampling is performed every cycle, with the rising edge of the next cycle after the end of the dmabcr write cycle for setting the transfer enabled state as the starting point. when the dreq pin low level is sampled while acceptance by means of the dreq pin is possible, the request is held in the dmac. then, when activation is initiated in the dmac, the request is cleared, and dreq pin high level sampling for edge detection is started. if dreq pin high level sampling has been completed by the time the dma single cycle ends, acceptance resumes after the end of the single cycle, dreq pin low level sampling is performed again, and this operation is repeated until the transfer ends.
section 8 dma controller rev. 3.00 jan 11, 2005 page 293 of 1220 rej09b0186-0300o (4) dreq pin low level activation timing set the dta bit for the channel for which the dreq pin is selected to 1. figure 8.32 shows an example of dreq pin low level activated single address mode transfer. dreq bus release dma single address bus dma control channel [2] dack transfer source/ destination idle idle idle single single [1] [3] [5] [4] [6] [7] acceptance resumes acceptance resumes bus release dma single bus release transfer source/ destination request request minimum of 2 cycles minimum of 2 cycles request clear period request clear period [1] [2] [5] [3] [6] [4] [7] acceptance after transfer enabling; the dreq pin low level is sampled on the rising edge of , and the request is held. the request is cleared at the next bus break, and activation is started in the dmac. the dmac cycle is started. acceptance is resumed after the single cycle is completed. (as in [1], the dreq pin low level is sampled on the rising edge of , and the request is held.) note: in write data buffer mode, bus breaks from [ 2 ] to [ 7 ] ma y be hidden, and not visible. figure 8.32 example of dreq pin low level activated single address mode transfer dreq pin sampling is performed every cycle, with the rising edge of the next cycle after the end of the dmabcr write cycle for setting the transfer enabled state as the starting point. when the dreq pin low level is sampled while acceptance by means of the dreq pin is possible, the request is held in the dmac. then, when activation is initiated in the dmac, the request is cleared. after the end of the single cycle, acceptance resumes, dreq pin low level sampling is performed again, and this operation is repeated until the transfer ends.
section 8 dma controller rev. 3.00 jan 11, 2005 page 294 of 1220 rej09b0186-0300o 8.5.12 write data buffer function dmac internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved. when the wdbe bit of bcrl in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal i/o registers) are executed in parallel. internal accesses are independent of the bus master, and dmac dead cycles are regarded as internal accesses. a low level can always be output from the tend pin if the bus cycle in which a low level is to be output is an external bus cycle. however, a low level is not output from the tend pin if the bus cycle in which a low level is to be output from the tend pin is an internal bus cycle, and an external write cycle is executed in parallel with this cycle. figure 8.33 shows an example of burst mode transfer from on-chip ram to external memory using the write data buffer function. internal address internal read signal hwr , lwr tend external address dma read dma write dma read dma write dma read dma write dma read dma write dma dead figure 8.33 example of dual address transfer using write data buffer function figure 8.34 shows an example of single address transfer using the write data buffer function. in this example, the cpu program area is in on-chip memory.
section 8 dma controller rev. 3.00 jan 11, 2005 page 295 of 1220 rej09b0186-0300o internal address internal read signal rd dack external address dma read dma single cpu read dma single cpu read figure 8.34 example of single address transfer using write data buffer function when the write data buffer function is activated, the dmac recognizes that the bus cycle concerned has ended, and starts the next operation. therefore, dreq pin sampling is started one state after the start of the dma write cycle or single address transfer. 8.5.13 dmac multi-channel operation the dmac channel priority order is: channel 0 > channel 1, and channel a > channel b. table 8.13 summarizes the priority order for dmac channels. table 8.13 dmac channel priority order short address mode full address mode priority channel 0a channel 0 high channel 0b channel 1a channel 1 channel 1b low
section 8 dma controller rev. 3.00 jan 11, 2005 page 296 of 1220 rej09b0186-0300o if transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released the dmac selects the highest-priority channel from among those issuing a request according to the priority order shown in table 8.13. during burst transfer, or when one block is being transferred in block transfer, the channel will not be changed until the end of the transfer. figure 8.35 shows a transfer example in which transfer requests are issued simultaneously for channels 0a, 0b, and 1. dma read dma write dma read dma write dma read dma write dma read address bus rd hwr lwr dma control channel 0a channel 0b channel 1 idle write idle read write idle read write read request clear request hold request hold request clear request clear bus release channel 0a transfer bus release channel 0b transfer channel 1 transfer bus release request hold read selection non- selection selection figure 8.35 example of multi-channel transfer
section 8 dma controller rev. 3.00 jan 11, 2005 page 297 of 1220 rej09b0186-0300o 8.5.14 relation between external bus requests, refresh cycles, the dtc, and the dmac there can be no break between a dma cycle read and a dma cycle write. this means that a refresh cycle, external bus release cycle, or dtc cycle is not generated between the external read and external write in a dma cycle. in the case of successive read and write cycles, such as in burst transfer or block transfer, a refresh or external bus released state may be inserted after a write cycle. since the dtc has a lower priority than the dmac, the dtc does not operate until the dmac releases the bus. when dma cycle reads or writes are accesses to on-chip memory or internal i/o registers, these dma cycles can be executed at the same time as refresh cycles or external bus release. however, simultaneous operation may not be possible when a write buffer is used.
section 8 dma controller rev. 3.00 jan 11, 2005 page 298 of 1220 rej09b0186-0300o 8.5.15 nmi interrupts and dmac when an nmi interrupt is requested, burst mode transfer in full address mode is interrupted. an nmi interrupt does not affect the operation of the dmac in other modes. in full address mode, transfer is enabled for a channel when both the dte bit and the dtme bit are set to 1. with burst mode setting, the dtme bit is cleared when an nmi interrupt is requested. if the dtme bit is cleared during burst mode transfer, the dmac discontinues transfer on completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the cpu. the channel on which transfer was interrupted can be restarted by setting the dtme bit to 1 again. figure 8.36 shows the procedure for continuing transfer when it has been interrupted by an nmi interrupt on a channel designated for burst mode transfer. resumption of transfer on interrupted channel set dtme bit to 1 transfer continues [1] [2] dte = 1 dtme = 0 transfer ends no yes [1] [2] check that dte = 1 and dtme = 0 in dmabcrl. write 1 to the dtme bit. figure 8.36 example of procedure for continuing transfer on channel interrupted by nmi interrupt
section 8 dma controller rev. 3.00 jan 11, 2005 page 299 of 1220 rej09b0186-0300o 8.5.16 forced termination of dmac operation if the dte bit for the channel currently operating is cleared to 0, the dmac stops on completion of the 1-byte or 1-word transfer in progress. dmac operation resumes when the dte bit is set to 1 again. in full address mode, the same applies to the dtme bit. figure 8.37 shows the procedure for forcibly terminating dmac operation by software. forced termination of dmac clear dte bit to 0 forced termination [1] [1] clear the dte bit in dmabcrl to 0. if you want to prevent interrupt generation after forced termination of dmac operation, clear the dtie bit to 0 at the same time. figure 8.37 example of procedure for forcibly terminating dmac operation
section 8 dma controller rev. 3.00 jan 11, 2005 page 300 of 1220 rej09b0186-0300o 8.5.17 clearing full address mode figure 8.38 shows the procedure for releasing and initializing a channel designated for full address mode. after full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. clearing full address mode stop the channel initialize dmacr clear fae bit to 0 initialization; operation halted [1] [2] [3] [1] clear both the dte bit and the dtme bit in dmabcrl to 0; or wait until the transfer ends and the dte bit is cleared to 0, then clear the dtme bit to 0. also clear the corresponding dtie bit to 0 at the same time. [2] clear all bits in dmacra and dmacrb to 0. [3] clear the fae bit in dmabcrh to 0. figure 8.38 example of procedure for clearing full address mode
section 8 dma controller rev. 3.00 jan 11, 2005 page 301 of 1220 rej09b0186-0300o 8.6 interrupts the sources of interrupts generated by the dmac are transfer end and transfer break. table 8.14 shows the interrupt sources and their priority order. table 8.14 interrupt source priority order interrupt source interrupt name short address mode full address mode interrupt priority order dend0a interrupt due to end of transfer on channel 0a interrupt due to end of transfer on channel 0 high dend0b interrupt due to end of transfer on channel 0b interrupt due to break in transfer on channel 0 dend1a interrupt due to end of transfer on channel 1a interrupt due to end of transfer on channel 1 dend1b interrupt due to end of transfer on channel 1b interrupt due to break in transfer on channel 1 low enabling or disabling of each interrupt source is set by means of the dtie bit for the corresponding channel in dmabcr, and interrupts from each source are sent to the interrupt controller independently. the relative priority of transfer end interrupts on each channel is decided by the interrupt controller, as shown in table 8.14. figure 8.39 shows a block diagram of a transfer end/transfer break interrupt. an interrupt is always generated when the dtie bit is set to 1 while dte bit is cleared to 0. dte/ dtme dtie transfer end/transfe r break interrupt figure 8.39 block diagram of transfer end/transfer break interrupt in full address mode, a transfer break interrupt is generated when the dtme bit is cleared to 0 while dtieb bit is set to 1. in both short address mode and full address mode, dmabcr should be set so as to prevent the occurrence of a combination that constitutes a condition for interrupt generation during setting.
section 8 dma controller rev. 3.00 jan 11, 2005 page 302 of 1220 rej09b0186-0300o 8.7 usage notes (1) dmac register access during operation except for forced termination, the operating (including transfer waiting state) channel setting should not be changed. the operating channel setting should only be changed when transfer is disabled. also, the dmac register should not be written to in a dma transfer. dmac register reads during operation (including the transfer waiting state) are described below. (a) dmac control starts one cycle before the bus cycle, with output of the internal address. consequently, mar is updated in the bus cycle before dmac transfer. figure 8.40 shows an example of the update t iming for dmac registers in dual address transfer mode. [1] transfer source address register mar operation (incremented/decremented/fixed) transfer counter etcr operation (decremented) block size counter etcr operation (decremented in block transfer mode) [2] transfer destination address register mar operation (incremented/decremented/fixed) [2'] transfer destination address register mar operation (incremented/decremented/fixed) block transfer counter etcr operation (decremented, in last transfer cycle of a block in block transfer mode) [3] transfer address register mar restore operation (in block or repeat transfer mode) transfer counter etcr restore (in repeat transfer mode) block size counter etcr restore (in block transfer mode) notes: 1. in single address transfer mode, the update timing is the same as [1]. 2. the mar operation is post-incrementin g /decrementin g of the dma internal address value. [3] [2]' [2] [1] [1] dma transfer cycle dma read dma read dma write dma write dma dead dma internal address dma control dma register operation dma last transfer cycle transfer destination transfer destination transfer source transfer source idle idle idle read read dead write write figure 8.40 dmac register update timing
section 8 dma controller rev. 3.00 jan 11, 2005 page 303 of 1220 rej09b0186-0300o (b) if a dmac transfer cycle occurs immediately after a dmac register read cycle, the dmac register is read as shown in figure 8.41. [2] [1] note: the lower word of mar is the updated value after the operation in [1]. cpu longword read dma transfer cycle mar upper word read mar lower word read dma read dma write dma internal address dma control dma register operation transfe source transfer destination idle read write idle figure 8.41 contention between dmac register update and cpu read (2) module stop when the mstpa7 bit in mstpcr is set to 1, the dmac clock stops, and the module stop state is entered. however, 1 cannot be written to the mstpa7 bit if any of the dmac channels is enabled. this setting should therefore be made when dmac operation is stopped. when the dmac clock stops, dmac register accesses can no longer be made. since the following dmac register settings are valid even in the module stop state, they should be invalidated, if necessary, before a module stop. ? transfer end/suspend interrupt (dte = 0 and dtie = 1) ? tend pin enable (tee = 1) ? dack pin enable (fae = 0 and sae = 1) (3) medium-speed mode when the dta bit is 0, internal interrupt signals specified as dmac transfer sources are edge- detected. in medium-speed mode, the dmac operates on a medium-speed clock, while on-chip supporting modules operate on a high-speed clock. consequently, if the period in which the relevant interrupt source is cleared by the cpu, dtc, or another dmac channel, and the next interrupt is generated, is less than one state with respect to the dmac clock (bus master clock), edge detection may not be possible and the interrupt may be ignored.
section 8 dma controller rev. 3.00 jan 11, 2005 page 304 of 1220 rej09b0186-0300o also, in medium-speed mode, dreq pin sampling is performed on the rising edge of the medium- speed clock. (4) write data buffer function when the wdbe bit of bcrl in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal i/o registers) are executed in parallel. (a) write data buffer function and dmac register setting if the setting of is changed during execution of an external access by means of the write data buffer function, the external access may not be performed normally. the register that controls external accesses should only be manipulated when external reads, etc., are used with dmac operation disabled, and the operation is not performed in parallel with external access. (b) write data buffer function and dmac operation timing the dmac can start its next operation during external access using the write data buffer function. consequently, the dreq pin sampling timing, tend output timing, etc., are different from the case in which the write data buffer function is disabled. also, internal bus cycles maybe hidden, and not visible. (c) write data buffer function and tend output a low level is not output from the tend pin if the bus cycle in which a low level is to be output from the tend pin is an internal bus cycle, and an external write cycle is executed in parallel with this cycle. note, for example, that a low level may not be output from the tend pin if the write data buffer function is used when data transfer is performed between an internal i/o register and on-chip memory. if at least one of the dmac transfer addresses is an external address, a low level is output from the tend pin.
section 8 dma controller rev. 3.00 jan 11, 2005 page 305 of 1220 rej09b0186-0300o figure 8.42 shows an example in which a low level is not output at the tend pin. internal address internal read signal external address hwr , lwr internal write signal tend not output dma read external write b y cpu, etc. dma write figure 8.42 example in which low level is not output at tend pin (5) activation by falling edge on dreq pin dreq pin falling edge detection is performed in synchronization with dmac internal operations. the operation is as follows: [1] activation request wait state: waits for detection of a low level on the dreq pin, and switches to [2]. [2] transfer wait state: waits for dmac data transfer to become possible, and switches to [3]. [3] activation request disabled state: waits for detection of a high level on the dreq pin, and switches to [1]. after dmac transfer is enabled, a transition is made to [1]. thus, initial activation after transfer is enabled is performed by detection of a low level. (6) activation source acceptance at the start of activation source acceptance, a low level is detected in both dreq pin falling edge sensing and low level sensing. similarly, in the case of an internal interrupt, the interrupt request is
section 8 dma controller rev. 3.00 jan 11, 2005 page 306 of 1220 rej09b0186-0300o detected. therefore, a request is accepted from an internal interrupt or dreq pin low level that occurs before execution of the dmabcrl write to enable transfer. when the dmac is activated, take any necessary steps to prevent an internal interrupt or dreq pin low level remaining from the end of the previous transfer, etc. (7) internal interrupt after end of transfer when the dte bit is cleared to 0 by the end of transfer or an abort, the selected internal interrupt request will be sent to the cpu or dtc even if dta is set to 1. also, if internal dmac activation has already been initiated when operation is aborted, the transfer is executed but flag clearing is not performed for the selected internal interrupt even if dta is set to 1. an internal interrupt request following the end of transfer or an abort should be handled by the cpu as necessary. (8) channel re-setting to reactivate a number of channels when multiple channels are enabled, use exclusive handling of transfer end interrupts, and perform dmabcr control bit operations exclusively. note, in particular, that in cases where multiple interrupts are generated between reading and writing of dmabcr, and a dmabcr operation is performed during new interrupt handling, the dmabcr write data in the original interrupt handling routine will be incorrect, and the write may invalidate the results of the operations by the multiple interrupts. ensure that overlapping dmabcr operations are not performed by multiple interrupts, and that there is no separation between read and write operations by the use of a bit-manipulation instruction. also, when the dte and dtme bits are cleared by the dmac or are written with 0, they must first be read while cleared to 0 before the cpu can write a 1 to them.
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 307 of 1220 rej09b0186-0300o section 9 data transfer controller (dtc) 9.1 overview the h8s/2643 group includes a data transfer controller (dtc). the dtc can be activated by an interrupt or software, to transfer data. 9.1.1 features the features of the dtc are: ? transfer possible over any number of channels ? transfer information is stored in memory ? one activation source can trigger a number of data transfers (chain transfer) ? wide range of transfer modes ? normal, repeat, and block transfer modes available ? incrementing, decrementing, and fixing of source and destination addresses can be selected ? direct specification of 16-mbyte address space possible ? 24-bit transfer source and destination addresses can be specified ? transfer can be set in byte or word units ? a cpu interrupt can be requested for the interrupt that activated the dtc ? an interrupt request can be issued to the cpu after one data transfer ends ? an interrupt request can be issued to the cpu after the specified data transfers have completely ended ? activation by software is possible ? module stop mode can be set ? the initial setting enables dtc registers to be accessed. dtc operation is halted by setting module stop mode.
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 308 of 1220 rej09b0186-0300o 9.1.2 block diagram figure 9.1 shows a block diagram of the dtc. the dtc?s register information is stored in the on-chip ram*. a 32-bit bus connects the dtc to the on-chip ram (1 kbyte), enabling 32-bit/1-state reading and writing of the dtc register information. note: * when the dtc is used, the rame bit in syscr must be set to 1. interrupt request interrupt controller dtc internal address bus dtc service request control logic register information mra mrb cra crb dar sar cpu interrupt request on-chip ram internal data bus legend: mra, mrb: cra, crb: sar: dar dtcera to dtcerf, dtceri: dtvecr: dtcera to dtcerf, dtceri dtvecr dtc mode registers a and b dtc transfer count registers a and b dtc source address register dtc destination address register dtc enable registers a to f and i dtc vector re g ister figure 9.1 block diagram of dtc
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 309 of 1220 rej09b0186-0300o 9.1.3 register configuration table 9.1 summarizes the dtc registers. table 9.1 dtc registers name abbreviation r/w initial value address * 1 dtc mode register a mra ? * 2 undefined ? * 3 dtc mode register b mrb ? * 2 undefined ? * 3 dtc source address register sar ? * 2 undefined ? * 3 dtc destination address register dar ? * 2 undefined ? * 3 dtc transfer count register a cra ? * 2 undefined ? * 3 dtc transfer count register b crb ? * 2 undefined ? * 3 dtc enable registers dtcer r/w h'00 h'fe16 to h'fe1e dtc vector register dtvecr r/w h'00 h'fe1f module stop control register mstpcra r/w h'3f h'fde8 notes: 1. lower 16 bits of the address. 2. registers within the dtc cannot be read or written to directly. 3. register information is located in on-chip ram addresses h'ebc0 to h'efbf. it cannot be located in external memory space. when the dtc is used, do not clear the rame bit in syscr to 0.
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 310 of 1220 rej09b0186-0300o 9.2 register descriptions 9.2.1 dtc mode register a (mra) 7 sm1 6 sm0 5 dm1 4 dm0 3 md1 0 sz 2 md0 1 dts bit initial value : : ? unde- fined r/w : ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined mra is an 8-bit register that controls the dtc operating mode. bits 7 and 6?source address mode 1 and 0 (sm1, sm0): these bits specify whether sar is to be incremented, decremented, or left fixed after a data transfer. bit 7 bit 6 sm1 sm0 description 0 ? sar is fixed 10 sar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) 1 sar is decremented after a transfer (by ? 1 when sz = 0; by ? 2 when sz = 1) bits 5 and 4?destination address mode 1 and 0 (dm1, dm0): these bits specify whether dar is to be incremented, decremented, or left fixed after a data transfer. bit 5 bit 4 dm1 dm0 description 0 ? dar is fixed 1 0 dar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) 1 dar is decremented after a transfer (by ? 1 when sz = 0; by ? 2 when sz = 1)
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 311 of 1220 rej09b0186-0300o bits 3 and 2?dtc mode (md1, md0): these bits specify the dtc transfer mode. bit 3 bit 2 md1 md0 description 0 0 normal mode 1 repeat mode 1 0 block transfer mode 1 ? bit 1?dtc transfer mode select (dts): specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. bit 1 dts description 0 destination side is repeat area or block area 1 source side is repeat area or block area bit 0?dtc data transfer size (sz): specifies the size of data to be transferred. bit 0 sz description 0 byte-size transfer 1 word-size transfer
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 312 of 1220 rej09b0186-0300o 9.2.2 dtc mode register b (mrb) 7 chne 6 disel 5 ? 4 ? 3 ? 0 ? 2 ? 1 ? bit initial value : : r/w : ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined mrb is an 8-bit register that controls the dtc operating mode. bit 7?dtc chain transfer enable (chne): specifies chain transfer. with chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. in data transfer with chne set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of dtcer is not performed. bit 7 chne description 0 end of dtc data transfer (activation waiting state is entered) 1 dtc chain transfer (new register information is read, then data is transferred) bit 6?dtc interrupt select (disel): specifies whether interrupt requests to the cpu are disabled or enabled after a data transfer. bit 6 disel description 0 after a data transfer ends, the cpu interrupt is disabled unless the transfer counter is 0 (the dtc clears the interrupt source flag of the activating interrupt to 0) 1 after a data transfer ends, the cpu interrupt is enabled (the dtc does not clear the interrupt source flag of the activating interrupt to 0) bits 5 to 0?reserved: these bits have no effect on dtc operation in the h8s/2643 group, and should always be written with 0.
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 313 of 1220 rej09b0186-0300o 9.2.3 dtc source address register (sar) 23 22 21 20 19 43210 bit initial value : : ? unde- fined r/w : ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined sar is a 24-bit register that designates the source address of data to be transferred by the dtc. for word-size transfer, specify an even source address. 9.2.4 dtc destination address register (dar) 23 22 21 20 19 43210 bit initial value : : ? unde- fined r/w : ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined dar is a 24-bit register that designates the destination address of data to be transferred by the dtc. for word-size transfer, specify an even destination address. 9.2.5 dtc transfer count register a (cra) 15 14 13 12 11109876543210 crah cral bit initial value : : ? unde- fined r/w : ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined ? unde- fined cra is a 16-bit register that designates the number of times data is to be transferred by the dtc. in normal mode, the entire cra functions as a 16-bit transfer counter (1 to 65,536). it is decremented by 1 every time data is transferred, and transfer ends when the count reaches h'0000. in repeat mode or block transfer mode, the cra is divided into two parts: the upper 8 bits (crah) and the lower 8 bits (cral). crah holds the number of transfers while cral functions as an 8-bit transfer counter (1 to 256). cral is decremented by 1 every time data is
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 314 of 1220 rej09b0186-0300o transferred, and the contents of crah are sent when the count reaches h'00. this operation is repeated. 9.2.6 dtc transfer count register b (crb) 15 14 13 12 11109876543210 bit initial value : : ? ? ? ? ?? ? ? ?? ? ? ?? ? ? unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined r/w : crb is a 16-bit register that designates the number of times data is to be transferred by the dtc in block transfer mode. it functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches h'0000. 9.2.7 dtc enable register (dtcer) 7 dtce7 0 r/w 6 dtce6 0 r/w 5 dtce5 0 r/w 4 dtce4 0 r/w 3 dtce3 0 r/w 0 dtce0 0 r/w 2 dtce2 0 r/w 1 dtce1 0 r/w bit initial value r/w : : : the dtc enable register comprises seven 8-bit readable/writable registers, dtcera to dtcerf and dtceri, with bits corresponding to the interrupt sources that can control enabling and disabling of dtc activation. these bits enable or disable dtc service for the corresponding interrupt sources. the dtc enable register is initialized to h'00 by a reset and in hardware standby mode.
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 315 of 1220 rej09b0186-0300o bit n?dtc activation enable (dtcen) bit n dtcen description 0 dtc activation by this interrupt is disabled (initial value ) [clearing conditions] ? when the disel bit is 1 and the data transfer has ended ? when the specified number of transfers have ended 1 dtc activation by this interrupt is enabled [holding condition] ? when the disel bit is 0 and the specified number of transfers have not ended (n = 7 to 0) a dtce bit can be set for each interrupt source that can activate the dtc. the correspondence between interrupt sources and dtce bits is shown in table 9.4, together with the vector number generated for each interrupt controller. for dtce bit setting, use bit manipulation instructions such as bset and bclr for reading and writing. if all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. 9.2.8 dtc vector register (dtvecr) 7 swdte 0 r/(w) * 1 6 dtvec6 0 r/w * 2 5 dtvec5 0 r/w * 2 4 dtvec4 0 r/w * 2 3 dtvec3 0 r/w * 2 0 dtvec0 0 r/w * 2 2 dtvec2 0 r/w * 2 1 dtvec1 0 r/w * 2 notes: 1. only 1 can be written to the swdte bit. 2. bits dtvec6 to dtvec0 can be written to when swdte = 0. bit initial value r/w : : : dtvecr is an 8-bit readable/writable register that enables or disables dtc activation by software, and sets a vector number for the software activation interrupt. dtvecr is initialized to h'00 by a reset and in hardware standby mode.
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 316 of 1220 rej09b0186-0300o bit 7?dtc software activation enable (swdte): enables or disables dtc activation by software. bit 7 swdte description 0 dtc software activation is disabled (initial value ) [clearing conditions] ? when the disel bit is 0 and the specified number of transfers have not ended ? when 0s written to the disel bit after a software-activated data transfer end interrupt (swdtend) request has been sent to the cpu 1 dtc software activation is enabled [holding conditions] ? when the disel bit is 1 and data transfer has ended ? when the specified number of transfers have ended ? during data transfer due to software activation bits 6 to 0?dtc software activation vectors 6 to 0 (dtvec6 to dtvec0): these bits specify a vector number for dtc software activation. the vector address is expressed as h'0400 + ((vector number) << 1). <<1 indicates a one-bit left- shift. for example, when dtvec6 to dtvec0 = h'10, the vector address is h'0420. 9.2.9 module stop control register a (mstpcra) 7 mstpa7 0 r/w bit : initial value : r/w : 6 mstpa6 0 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w 0 mstpa0 1 r/w mstpcra is an 8-bit readable/writable register that performs module stop mode control. when the mstpa6 bit in mstpcra is set to 1, the dtc operation stops at the end of the bus cycle and a transition is made to module stop mode. however, 1 cannot be written in the mstpa6 bit while the dtc is operating. for details, see section 24.5, module stop mode. mstpcra is initialized to h'3f by a reset and in hardware standby mode. it is not initialized in software standby mode.
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 317 of 1220 rej09b0186-0300o bit 6?module stop (mstpa6): specifies the dtc module stop mode. bit 6 mstpa6 description 0 dtc module stop mode cleared (initial value ) 1 dtc module stop mode set
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 318 of 1220 rej09b0186-0300o 9.3 operation 9.3.1 overview when activated, the dtc reads register information that is already stored in memory and transfers data on the basis of that register information. after the data transfer, it writes updated register information back to memory. pre-storage of register information in memory makes it possible to transfer data over any required number of channels. setting the chne bit to 1 makes it possible to perform a number of transfers with a single activation. figure 9.2 shows a flowchart of dtc operation. start read dtc vector next transfer read register information data transfer write register information clear an activation flag chne = 1 end no no yes yes transfer counter = 0 or disel = 1 clear dtcer interrupt exception handling figure 9.2 flowchart of dtc operation
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 319 of 1220 rej09b0186-0300o the dtc transfer mode can be normal mode, repeat mode, or block transfer mode. the 24-bit sar designates the dtc transfer source address and the 24-bit dar designates the transfer destination address. after each transfer, sar and dar are independently incremented, decremented, or left fixed. table 9.2 outlines the functions of the dtc. table 9.2 dtc functions address registers transfer mode activation source transfer source transfer destination ? normal mode ? one transfer request transfers one byte or one word ? memory addresses are incremented or decremented by 1 or 2 ? up to 65,536 transfers possible ? repeat mode ? one transfer request transfers one byte or one word ? memory addresses are incremented or decremented by 1 or 2 ? after the specified number of transfers (1 to 256), the initial state resumes and operation continues ? block transfer mode ? one transfer request transfers a block of the specified size ? block size is from 1 to 256 bytes or words ? up to 65,536 transfers possible ? a block area can be designated at either the source or destination ? irq ? tpu tgi ? 8-bit timer cmi ? sci txi or rxi ? a/d converter adi ? dmac dend ? software 24 bits 24 bits
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 320 of 1220 rej09b0186-0300o 9.3.2 activation sources the dtc operates when activated by an interrupt or by a write to dtvecr by software. an interrupt request can be directed to the cpu or dtc, as designated by the corresponding dtcer bit. an interrupt becomes a dtc activation source when the corresponding bit is set to 1, and a cpu interrupt source when the bit is cleared to 0. at the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding dtcer bit is cleared. table 9.3 shows activation source and dtcer clearance. the activation source flag, in the case of rxi0, for example, is the rdrf flag of sci0. table 9.3 activation source and dtcer clearance activation source when the disel bit is 0 and the specified number of transfers have not ended when the disel bit is 1, or when the specified number of transfers have ended software activation the swdte bit is cleared to 0 the swdte bit remains set to 1 an interrupt is issued to the cpu interrupt activation the corresponding dtcer bit remains set to 1 the activation source flag is cleared to 0 the corresponding dtcer bit is cleared to 0 the activation source flag remains set to 1 a request is issued to the cpu for the activation source interrupt figure 9.3 shows a block diagram of activation source control. for details see section 5, interrupt controller.
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 321 of 1220 rej09b0186-0300o on-chip supporting module irq interrupt dtvecr selection circuit interrupt controller cpu dtc dtcer clear controller select interrupt request source flag cleared clear clear request interrupt mask figure 9.3 block diagram of dtc activation source control when an interrupt has been designated a dtc activation source, existing cpu mask level and interrupt controller priorities have no effect. if there is more than one activation source at the same time, the dtc operates in accordance with the default priorities. 9.3.3 dtc vector table figure 9.4 shows the correspondence between dtc vector addresses and register information. table 9.4 shows the correspondence between activation and vector addresses. when the dtc is activated by software, the vector address is obtained from: h'0400 + (dtvecr[6:0] << 1) (where << 1 indicates a 1-bit left shift). for example, if dtvecr is h'10, the vector address is h'0420. the dtc reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. the register information can be placed at predetermined addresses in the on-chip ram. the start address of the register information should be an integral multiple of four. the configuration of the vector address is the same in both normal* and advanced modes, a 2-byte unit being used in both cases. these two bytes specify the lower bits of the address in the on-chip ram. note: * not available in the h8s/2643 group.
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 322 of 1220 rej09b0186-0300o register information start address register information chain transfer dtc vector address figure 9.4 correspondence between dtc vector address and register information
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 323 of 1220 rej09b0186-0300o table 9.4 interrupt sources, dtc vector addresses, and corresponding dtces interrupt source origin of interrupt source vector number vector address dtce * priority write to dtvecr software dtvecr h'0400+ (dtvecr [6:0] <<1) ? high irq0 external pin 16 h'0420 dtcea7 irq1 17 h'0422 dtcea6 irq2 18 h'0424 dtcea5 irq3 19 h'0426 dtcea4 irq4 20 h'0428 dtcea3 irq5 21 h'042a dtcea2 irq6 22 h'042c dtcea1 irq7 23 h'042e dtcea0 adi (a/d conversion end) a/d 28 h'0438 dtceb6 tgi0a (gr0a compare match/ input capture) tpu channel 0 32 h'0440 dtceb5 tgi0b (gr0b compare match/ input capture) 33 h'0442 dtceb4 tgi0c (gr0c compare match/ input capture) 34 h'0444 dtceb3 tgi0d (gr0d compare match/ input capture) 35 h'0446 dtceb2 tgi1a (gr1a compare match/ input capture) tpu channel 1 40 h'0450 dtceb1 tgi1b (gr1b compare match/ input capture) 41 h'0452 dtceb0 tgi2a (gr2a compare match/ input capture) tpu channel 2 44 h'0458 dtcec7 tgi2b (gr2b compare match/ input capture) 45 h'045a dtcec6 low
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 324 of 1220 rej09b0186-0300o interrupt source origin of interrupt source vector number vector address dtce * priority tgi3a (gr3a compare match/ input capture) tpu channel 3 48 h'0460 dtcec5 high tgi3b (gr3b compare match/ input capture) 49 h'0462 dtcec4 tgi3c (gr3c compare match/ input capture) 50 h'0464 dtcec3 tgi3d (gr3d compare match/ input capture) 51 h'0466 dtcec2 tgi4a (gr4a compare match/ input capture) tpu channel 4 56 h'0470 dtcec1 tgi4b (gr4b compare match/ input capture) 57 h'0472 dtcec0 tgi5a (gr5a compare match/ input capture) tpu channel 5 60 h'0478 dtced5 tgi5b (gr5b compare match/ input capture) 61 h'047a dtced4 cmia0 (compare match a0) 64 h'0480 dtced3 cmib0 (compare match b0) 8-bit timer channel 0 65 h'0482 dtced2 cmia1 (compare match a1) 68 h'0488 dtced1 cmib1 (compare match b1) 8-bit timer channel 1 69 h'048a dtced0 dend0a (channel 0/channel 0a transfer end) dmac 72 h'0490 dtcee7 dend0b (channel 0b transfer end) 73 h'0492 dtcee6 dend1a (channel 1/channel 1a transfer end) 74 h'0494 dtcee5 dend1b (channel 1b transfer end) 75 h'0496 dtcee4 rxi0 (reception complete 0) 81 h'04a2 dtcee3 txi0 (transmit data empty 0) sci channel 0 82 h'04a4 dtcee2 rxi1 (reception complete 1) 85 h'04aa dtcee1 txi1 (transmit data empty 1) sci channel 1 86 h'04ac dtcee0 rxi2 (reception complete 2) 89 h'04b2 dtcef7 txi2 (transmit data empty 2) sci channel 2 90 h'04b4 dtcef6 low
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 325 of 1220 rej09b0186-0300o interrupt source origin of interrupt source vector number vector address dtce * priority cmia2 (compare match a2) 92 h'04b8 dtcef5 high cmib2 (compare match b2) 8-bit timer channel 2 93 h'04ba dtcef4 cmia3 (compare match a3) 96 h'04c0 dtcef3 cmib3 (compare match b3) 8-bit timer channel 3 97 h'04c2 dtcef2 iici0 (1-byte transmit/reception complete) iic channel 0 (option) 100 h'04c8 dtcef1 iici1 (1-byte transmit/reception complete) iic channel 1 (option) 102 h'04cc dtcef0 rxi3 (reception complete 3) sci channel 3 121 h'04f2 dtcei7 txi3 (transmit data empty 3) 122 h'04f4 dtcei6 rxi4 (reception complete 4) sci channel 4 125 h'04fa dtcei5 txi4 (transmit data empty 4) 126 h'04fc dtcei4 low note: * dtce bits with no corresponding interrupt are reserved, and should be written with 0.
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 326 of 1220 rej09b0186-0300o 9.3.4 location of register information in address space figure 9.5 shows how the register information should be located in the address space. locate the mra, sar, mrb, dar, cra, and crb registers, in that order, from the start address of the register information (contents of the vector address). in the case of chain transfer, register information should be located in consecutive areas. locate the register information in the on-chip ram (addresses: h'ffebc0 to h'ffefbf). register information start address chain transfer register information for 2nd transfer in chain transfer mra sar mrb dar cra crb 4 bytes lower address cra crb register information mra 0123 sar mrb dar figure 9.5 location of register information in address space
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 327 of 1220 rej09b0186-0300o 9.3.5 normal mode in normal mode, one operation transfers one byte or one word of data. from 1 to 65,536 transfers can be specified. once the specified number of transfers have ended, a cpu interrupt can be requested. table 9.5 lists the register information in normal mode and figure 9.6 shows memory mapping in normal mode. table 9.5 register information in normal mode name abbreviation function dtc source address register sar designates source address dtc destination address register dar designates destination address dtc transfer count register a cra designates transfer count dtc transfer count register b crb not used transfer sar da r figure 9.6 memory mapping in normal mode
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 328 of 1220 rej09b0186-0300o 9.3.6 repeat mode in repeat mode, one operation transfers one byte or one word of data. from 1 to 256 transfers can be specified. once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. in repeat mode the transfer counter value does not reach h'00, and therefore cpu interrupts cannot be requested when disel = 0. table 9.6 lists the register information in repeat mode and figure 9.7 shows memory mapping in repeat mode. table 9.6 register information in repeat mode name abbreviation function dtc source address register sar designates source address dtc destination address register dar designates destination address dtc transfer count register ah crah holds number of transfers dtc transfer count register al cral designates transfer count dtc transfer count register b crb not used transfer sar or dar dar or sar repeat area figure 9.7 memory mapping in repeat mode
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 329 of 1220 rej09b0186-0300o 9.3.7 block transfer mode in block transfer mode, one operation transfers one block of data. either the transfer source or the transfer destination is designated as a block area. the block size is 1 to 256. when the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. the other address register is then incremented, decremented, or left fixed. from 1 to 65,536 transfers can be specified. once the specified number of transfers have ended, a cpu interrupt is requested. table 9.7 lists the register information in block transfer mode and figure 9.8 shows memory mapping in block transfer mode. table 9.7 register information in block transfer mode name abbreviation function dtc source address register sar designates source address dtc destination address register dar designates destination address dtc transfer count register ah crah holds block size dtc transfer count register al cral designates block size count dtc transfer count register b crb transfer count
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 330 of 1220 rej09b0186-0300o transfer sar or dar dar or sar block area first block nth block figure 9.8 memory mapping in block transfer mode
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 331 of 1220 rej09b0186-0300o 9.3.8 chain transfer setting the chne bit to 1 enables a number of data transfers to be performed consectutively in response to a single transfer request. sar, dar, cra, crb, mra, and mrb, which define data transfers, can be set independently. figure 9.9 shows the memory map for chain transfer. source source destination destination dtc vector address register information start address register information chne = 1 register information chne = 0 figure 9.9 chain transfer memory map in the case of transfer with chne set to 1, an interrupt request to the cpu is not generated at the end of the specified number of transfers or by setting of the disel bit to 1, and the interrupt source flag for the activation source is not affected.
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 332 of 1220 rej09b0186-0300o 9.3.9 operation timing figures 9.10 to 9.12 show an example of dtc operation t iming. dtc activation request dtc request address vector read transfer information read transfer information write data transfer read write figure 9.10 dtc operation timing (example in normal mode or repeat mode) read write read write data transfer transfer information write transfer information read vector read dtc activation request dtc request address figure 9.11 dtc operation timing (example of block transfer mode, with block size of 2)
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 333 of 1220 rej09b0186-0300o read write read write address dtc activation request dtc request data transfer data transfer transfer information write transfer information write transfer information read transfer information read vector read figure 9.12 dtc operation timing (example of chain transfer) 9.3.10 number of dtc execution states table 9.8 lists execution statuses for a single dtc data transfer, and table 9.9 shows the number of states required for each execution status. table 9.8 dtc execution statuses mode vector read i register information read/write j data read k data write l internal operations m normal 1 6 1 1 3 repeat 1 6 1 1 3 block transfer 1 6 n n 3 n: block size (initial setting of crah and cral)
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 334 of 1220 rej09b0186-0300o table 9.9 number of states required for each execution status object to be accessed on- chip ram on- chip rom on-chip i/o registers external devices bus width 32 16 8 16 8 16 access states 1 1 2 2 2 3 2 3 vector read s i ? 1 ?? 4 6 + 2m 2 3 + m execution status register information read/write s j 1 ??????? byte data read s k 112223 + m23 + m word data read s k 114246 + 2m23 + m byte data write s l 112223 + m23 + m word data write s l 114246 + 2m23 + m internal operation s m 1 m: number of wait states inserted external device access the number of execution states is calculated from the formula below. note that means the sum of all transfers activated by one activation event (the number in which the chne bit is set to 1, plus 1). number of execution states = i s i + (j s j + k s k + l s l ) + m s m for example, when the dtc vector address table is located in on-chip rom, normal mode is set, and data is transferred from the on-chip rom to an internal i/o register, the time required for the dtc operation is 13 states. the time from activation to the end of the data write is 10 states. 9.3.11 procedures for using dtc (1) activation by interrupt the procedure for using the dtc with interrupt activation is as follows: [1] set the mra, mrb, sar, dar, cra, and crb register information in the on-chip ram. [2] set the start address of the register information in the dtc vector address. [3] set the corresponding bit in dtcer to 1. [4] set the enable bits for the interrupt sources to be used as the activation sources to 1. the dtc is activated when an interrupt used as an activation source is generated.
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 335 of 1220 rej09b0186-0300o [5] after the end of one data transfer, or after the specified number of data transfers have ended, the dtce bit is cleared to 0 and a cpu interrupt is requested. if the dtc is to continue transferring data, set the dtce bit to 1. (2) activation by software the procedure for using the dtc with software activation is as follows: [1] set the mra, mrb, sar, dar, cra, and crb register information in the on-chip ram. [2] set the start address of the register information in the dtc vector address. [3] check that the swdte bit is 0. [4] write 1 to swdte bit and the vector number to dtvecr. [5] check the vector number written to dtvecr. [6] after the end of one data transfer, if the disel bit is 0 and a cpu interrupt is not requested, the swdte bit is cleared to 0. if the dtc is to continue transferring data, set the swdte bit to 1. when the disel bit is 1, or after the specified number of data transfers have ended, the swdte bit is held at 1 and a cpu interrupt is requested. 9.3.12 examples of use of the dtc (1) normal mode an example is shown in which the dtc is used to receive 128 bytes of data via the sci. [1] set mra to fixed source address (sm1 = sm0 = 0), incrementing destination address (dm1 = 1, dm0 = 0), normal mode (md1 = md0 = 0), and byte size (sz = 0). the dts bit can have any value. set mrb for one data transfer by one interrupt (chne = 0, disel = 0). set the sci rdr address in sar, the start address of the ram area where the data will be r eceived in dar, and 128 (h'0080) in cra. crb can be set to any value. [2] set the start address of the register information at the dtc vector address. [3] set the corresponding bit in dtcer to 1. [4] set the sci to the appropriate receive mode. set the rie bit in scr to 1 to enable the reception complete (rxi) interrupt. since the generation of a receive error during the sci reception operation will disable subsequent reception, the cpu s hould be enabled to accept receive error interrupts. [5] each time reception of one byte of data ends on the sci, the rdrf flag in ssr is set to 1, an rxi interrupt is generated, and the dtc is activated. the receive data is transferred from rdr to ram by the dtc. dar is incremented and cra is decremented. the rdrf flag is automatically cleared to 0.
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 336 of 1220 rej09b0186-0300o [6] when cra becomes 0 after the 128 data transfers have ended, the rdrf flag is held at 1, the dtce bit is cleared to 0, and an rxi interrupt request is sent to the cpu. the interrupt handling routine should perform wrap-up processing. (2) chain transfer an example of dtc chain transfer is shown in which pulse output is performed using the ppg. chain transfer can be used to perform pulse output data transfer and ppg output trigger cycle updating. repeat mode transfer to the ppg ? s ndr is performed in the first half of the chain transfer, and normal mode transfer to the tpu ? s tgr in the second half. this is because clearing of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the chain transfer (transfer when chne = 0). [1] perform settings for transfer to the ppg ? s ndr. set mra to source address incrementing (sm1 = 1, sm0 = 0), fixed destination address (dm1 = dm0 = 0), repeat mode (md1 = 0, md0 = 1), and word size (sz = 1). set the source side as a repeat area (dts = 1). set mrb to chain mode (chne = 1, disel = 0). set the data table start address in sar, the ndrh address in dar, and the data table size in crah and cral. crb can be set to any value. [2] perform settings for transfer to the tpu ? s tgr. set mra to source address incrementing (sm1 = 1, sm0 = 0), fixed destination address (dm1 = dm0 = 0), normal mode (md1 = md0 = 0), and word size (sz = 1). set the data table start address in sar, the tgra address in dar, and the data table size in cra. crb can be set to any value. [3] locate the tpu transfer register information consecutively after the ndr transfer register information. [4] set the start address of the ndr transfer register information to the dtc vector address. [5] set the bit corresponding to tgia in dtcer to 1. [6] set tgra as an output compare register (output disabled) with tior, and enable the tgia interrupt with tier. [7] set the initial output value in podr, and the next output value in ndr. set bits in ddr and nder for which output is to be performed to 1. using pcr, select the tpu compare match to be used as the output trigger. [8] set the cst bit in tstr to 1, and start the tcnt count operation. [9] each time a tgra compare match occurs, the next output value is transferred to ndr and the set value of the next output trigger period is transferred to tgra. the activation source tgfa flag is cleared. [10]when the specified number of transfers are completed (the tpu transfer cra value is 0), the tgfa flag is held at 1, the dtce bit is cleared to 0, and a tgia interrupt request is sent to the cpu. termination processing should be performed in the interrupt handling routine.
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 337 of 1220 rej09b0186-0300o (3) software activation an example is shown in which the dtc is used to transfer a block of 128 bytes of data by means of software activation. the transfer source address is h'1000 and the destination address is h'2000. the vector number is h'60, so the vector address is h'04c0. [1] set mra to incrementing source address (sm1 = 1, sm0 = 0), incrementing destination address (dm1 = 1, dm0 = 0), block transfer mode (md1 = 1, md0 = 0), and byte size (sz = 0). the dts bit can have any value. set mrb for one block transfer by one interrupt (chne = 0). set the transfer source address (h'1000) in sar, the destination address (h'2000) in dar, and 128 (h'8080) in cra. set 1 (h'0001) in crb. [2] set the start address of the register information at the dtc vector address (h'04c0). [3] check that the swdte bit in dtvecr is 0. check that there is currently no transfer activated by software. [4] write 1 to the swdte bit and the vector number (h'60) to dtvecr. the write data is h'e0. [5] read dtvecr again and check that it is set to the vector number (h'60). if it is not, this indicates that the write failed. this is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. to activate this transfer, go back to step 3. [6] if the write was successful, the dtc is activated and a block of 128 bytes of data is transferred. [7] after the transfer, an swdtend interrupt occurs. the interrupt handling routine should clear the swdte bit to 0 and perform other wrap-up processing.
section 9 data transfer controller (dtc) rev. 3.00 jan 11, 2005 page 338 of 1220 rej09b0186-0300o 9.4 interrupts an interrupt request is issued to the cpu when the dtc finishes the specified number of data transfers, or a data transfer for which the disel bit was set to 1. in the case of interrupt activation, the interrupt set as the activation source is generated. these interrupts to the cpu are subject to cpu mask level and interrupt controller priority level control. in the case of activation by software, a software activated data transfer end interrupt (swdtend) is generated. when the disel bit is 1 and one data transfer has ended, or the specified number of transfers have ended, after data transfer ends, the swdte bit is held at 1 and an swdtend interrupt is generated. the interrupt handling routine should clear the swdte bit to 0. when the dtc is activated by software, an swdtend interrupt is not generated during a data transfer wait or during data transfer even if the swdte bit is set to 1. 9.5 usage notes (1) module stop when the mstpa6 bit in mstpcra is set to 1, the dtc clock stops, and the dtc enters the module stop state. however, 1 cannot be written in the mstpa6 bit while the dtc is operating. (2) on-chip ram the mra, mrb, sar, dar, cra, and crb registers are all located in on-chip ram. when the dtc is used, the rame bit in syscr must not be cleared to 0. (3) dmac transfer end interrupt when the dtc is activated with a dmac transfer end interrupt, the dmac's dte bit is not controlled by the dtc regardless of the transfer counter and disel bit, and write data takes precedence. (4) dtce bit setting for dtce bit setting, use bit manipulation instructions such as bset and bclr. if all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 339 of 1220 rej09b0186-0300o section 10 i/o ports 10.1 overview the h8s/2643 group has 13 i/o ports (ports 1, 2, 3, 5, 7, 8 and a to g), and two input-only port (ports 4 and 9). table 10.1 summarizes the port functions. the pins of each port also have other functions. each i/o port includes a data direction register (ddr) that controls input/output, a data register (dr) that stores output data, and a port register (port) used to read the pin states. the input-only ports do not have a dr or ddr register. ports a to e have a built-in pull-up mos function, and in addition to dr and ddr, have a mos input pull-up control register (pcr) to control the on/off state of mos input pull-up. ports 3, and a to c include an open-drain control register (odr) that controls the on/off state of the output buffer pmos. when ports 70 to 73 and a to g are used as the output pins for expanded bus control signals, they can drive one ttl load plus a 50 pf capacitance load. those ports in other cases, and ports 1 to 3, 5, 74 to 77, and 8, can drive one ttl load and a 30 pf capacitance load. all i/o ports can drive darlington transistors when set to output. see appendix c, i/o port block diagrams, for a block diagram of each port.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 340 of 1220 rej09b0186-0300o table 10.1 port functions port description pins mode 4 mode 5 mode 6 mode 7 port 1 ? 8-bit i/o port ? schmitt- triggered input ( irq1 , irq0 ) p17/po15/tiocb2/ pwm3/tclkd p16/po14/tioca2/ pwm2/ irq1 p15/po13/tiocb1/ tclkc p14/po12/tioca1/ irq0 p13/po11/tiocd0/ tclkb p12/po10/tiocc0/ tclka p11/po9/tiocb0 p10/po8/tioca0 8-bit i/o port also functioning as tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, tiocb2), ppg output pins (po15 to po8), interrupt input pins ( irq0 , irq1 ), and 14-bit pwm output pins (pwm2, pwm3) port 2 ? 8-bit i/o port ? schmitt- triggered input (p27 to p20) p27/po7/tiocb5 p26/po6/tioca5 p25/po5/tiocb4 p24/po4/tioca4 p23/po3/tiocd3 p22/po2/tiocc3 p21/po1/tiocb3 p20/po0/tioca3 8-bit i/o port also functioning as tpu i/o pins (tioca3, tiocb3, tiocc3, tiocd3, tioca4, tiocb4, tioca5, tiocb5) and ppg output pins (po7 to po0) port 3 ? 8-bit i/o port ? open-drain output capability ? schmitt- triggered input ( irq5 , irq4 , scl0, sda0, scl1, sda1) p37 /txd4 p36/rxd4 p35/sck1/sck4/ scl0/ irq5 p34 /rxd1/sda0 p33 /txd1/scl1 p32 /sck0/sda1/ irq4 p31 /rxd0/irrxd p30 /txd0/irtxd 8-bit i/o port also functioning as sci (channel 0, 1, and 4) i/o pins (txd0, rxd0, sck0, irtxd, irrxd, txd1, rxd1, sck1, txd4, rxd4, sck4), interrupt input pins ( irq4 , irq5 ), and iic (channel 0 and 1) i/o pins (scl0, sda0, scl1, sda1)
section 10 i/o ports rev. 3.00 jan 11, 2005 page 341 of 1220 rej09b0186-0300o port description pins mode 4 mode 5 mode 6 mode 7 port 4 ? 8-bit input port p47 /an7/da1 p46 /an6/da0 p45 /an5 p44 /an4 p43 /an3 p42 /an2 p41 /an1 p40/an0 8-bit input port also functioning as a/d converter analog inputs (an7 to an0) and d/a converter analog outputs (da1, da0) port 5 ? 3-bit i/o port p52/sck2 p51/rxd2 p50/txd2 3-bit i/o port also functioning as sci (channel 2) i/o pins (txd2, rxd2, sck2) port 7 ? 8-bit i/o port p77/txd3 p76/rxd3 p75/tmo3/sck3 p74/tmo2/ mres p73/tmo1/ cs7 p72/tmo0/ cs6 p71/tmri23/tmci23/ cs5 p70/tmri01/tmci01/ cs4 8-bit i/o port also functioning as 8-bit timer i/o pins (tmri01, tmci01, tmri23, tmci23, tmo0, tmo1, tmo2, tmo3), bus control output pins ( cs4 to cs7 ), sci i/o pins (sck3, rxd3, txd3), and the manual reset input pin ( mres ) 8-bit i/o port also function- ing as 8-bit timer i/o pins (tmri01, tmci01, tmri23, tmci23, tmo0, tmo1, tmo2, tmo3), sci i/o pins (sck3, rxd3, txd3), and the manual reset input pin ( mres ) port 8 ? 7-bit i/o port p86 p85/ dack1 p84/ dack0 p83/ tend1 p82/ tend0 p81/ dreq1 p80/ dreq0 7-bit i/o port also functioning as dmac i/o pins ( dreq0 , tend0 , dreq1 , tend1 , dack1 , dack0 )
section 10 i/o ports rev. 3.00 jan 11, 2005 page 342 of 1220 rej09b0186-0300o port description pins mode 4 mode 5 mode 6 mode 7 port 9 ? 8-bit input port p97/an15/da3 p96/an14/da2 p95/an13 p94/an12 p93/an11 p92/an10 p91/an9 p90/an8 8-bit input port also functioning as a/d converter analog inputs (an15 to an8) and d/a converter analog outputs (da3, da2) port a ? 8-bit i/o port ? built-in mos input pull-up ? open-drain output capability pa7/a23 pa6/a22 pa5/a21 pa4/a20 pa3/a19 pa2/a18 pa1/a17 pa0/a16 8-bit i/o port also functioning as address outputs (a23 to a16) 8-bit i/o port port b ? 8-bit i/o port ? built-in mos input pull-up ? open-drain output capability pb7/a15 pb6/a14 pb5/a13 pb4/a12 pb3/a11 pb2/a10 pb1/a9 pb0/a8 8-bit i/o port also functioning as address outputs (a15 to a8) 8-bit i/o port
section 10 i/o ports rev. 3.00 jan 11, 2005 page 343 of 1220 rej09b0186-0300o port description pins mode 4 mode 5 mode 6 mode 7 port c ? 8-bit i/o port ? built-in mos input pull-up ? open-drain output capability pc7/a7/pwm1 pc6/a6/pwm0 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0 /a0 8-bit i/o port also functioning as 14-bit pwm (channel 1 and 0) output pins (pwm1, pwm0) and address outputs (a7 to a0) 8-bit i/o port also function- ing as 14-bit pwm (channel 1 and 0) output pins (pwm1, pwm0) port d ? 8-bit i/o port ? built-in mos input pull-up pd7 /d15 pd6/d14 pd5/d13 pd4/d12 pd3/d11 pd2/d10 pd1/d9 pd0 /d8 data bus input/output 8-bit i/o port port e ? 8-bit i/o port ? built-in mos input pull-up pe7/d7 pe6/d6 pe5/d5 pe4/d4 pe3/d3 pe2/d2 pe1/d1 pe0 /d0 in 8-bit-bus mode: i/o port in 16-bit-bus mode: data bus input/output 8-bit i/o port
section 10 i/o ports rev. 3.00 jan 11, 2005 page 344 of 1220 rej09b0186-0300o port description pins mode 4 mode 5 mode 6 mode 7 port f pf7 / when ddr = 0: input port when ddr = 1 (after reset): output when ddr = 0 (after reset): input port when ddr = 1: output ? 8-bit i/o port ? schmitt- triggered input ( irq3 , irq2 ) pf6 / as / lcas pf5 / rd pf4 / hwr pf3/ lwr / adtrg / irq3 rd , hwr , lwr outputs adtrg , irq3 input when lcass = 0: as output when rmts2 to rmts0 = b'001 to b'011, cw2 = 0, and lcass = 1: lcas output i/o port adtrg , irq3 input pf2/ lcas / wait / breqo when waite = 0 and breqoe = 0 (after reset): i/o port when waite = 1 and breqoe = 0: wait input when waite = 0 and breqoe = 1: breqo input when rmts2 to rmts0 = b'001 to b'011, cw2 = 0, and lcass = 0: lcas output i/o port pf1/ back /buzz pf0/ breq / irq2 when brle = 0 (after reset): i/o port when brle = 1: breq input, back output buzz output, irq2 input buzz output irq2 input i/o port port g pg4 / cs0 when ddr = 0 * 1 : input port when ddr = 1 * 2 : cs0 output i/o port pg3 / cs1 pg2 / cs2 pg1 / cs3 / oe / irq7 when ddr = 0 (after reset): input port when ddr = 1: cs1 , cs2 , cs3 outputs oe output, irq7 input i/o port, irq7 input ? 5-bit i/o port ? schmitt- triggered input ( irq7 , irq6 ) pg0 / cas / irq6 dram space set: cas output otherwise (after reset): i/o port irq6 input i/o port, irq6 input notes: 1. after a reset in mode 6 2. after a reset in mode 4 or 5
section 10 i/o ports rev. 3.00 jan 11, 2005 page 345 of 1220 rej09b0186-0300o 10.2 port 1 10.2.1 overview port 1 is an 8-bit i/o port. port 1 pins also function as ppg output pins (po15 to po8), tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, and tiocb2), 14-bit pwm output pins (pwm2, pwm3), and external interrupt pins ( irq0 and irq1 ). port 1 pin functions are the same in all operating modes. figure 10.1 shows the port 1 pin configuration. p17 (i/o) / po15 (output) / tiocb2 (i/o) / pwm3 (output) / tclkd (input) p16 (i/o) / po14 (output) / tioca2 (i/o) / pwm2 (output) / irq1 (input) p15 (i/o) / po13 (output) / tiocb1 (i/o) / tclkc (input) p14 (i/o) / po12 (output) / tioca1 (i/o) / irq0 (input) p13 (i/o) / po11 (output) / tiocd0 (i/o) / tclkb (input) p12 (i/o) / po10 (output) / tiocc0 (i/o) / tclka (input) p11 (i/o) / po9 (output) / tiocb0 (i/o) p10 (i/o) / po8 (output) / tioca0 (i/o) port 1 port 1 pins pin functions in modes 4 to 7 figure 10.1 port 1 pin functions
section 10 i/o ports rev. 3.00 jan 11, 2005 page 346 of 1220 rej09b0186-0300o 10.2.2 register configuration table 10.2 shows the port 1 register configuration. table 10.2 port 1 registers name abbreviation r/w initial value address * port 1 data direction register p1ddr w h'00 h'fe30 port 1 data register p1dr r/w h'00 h'ff00 port 1 register port1 r undefined h'ffb0 note: * lower 16 bits of the address. (1) port 1 data direction register (p1ddr) bit:76543210 p17ddr p16ddr p15ddr p14ddr p13ddr p12ddr p11ddr p10ddr initial value:00000000 r/w:wwwwwwww p1ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. p1ddr cannot be read; if it is, an undefined value will be read. setting a p1ddr bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p1ddr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode. because ppg and tpu are initialized by a manual reset, pin states are determined by p1ddr and p1dr. (2) port 1 data register (p1dr) bit:76543210 p17dr p16dr p15dr p14dr p13dr p12dr p11dr p10dr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w p1dr is an 8-bit readable/writable register that stores output data for the port 1 pins (p17 to p10). p1dr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 347 of 1220 rej09b0186-0300o (3) port 1 register (port1) bit:76543210 p17 p16 p15 p14 p13 p12 p11 p10 initial value : ? * ? * ? * ? * ? * ? * ? * ? * r/w:rrrrrrrr note: * determined by state of pins p17 to p10. port1 is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port 1 pins (p17 to p10) must always be performed on p1dr. if a port 1 read is performed while p1ddr bits are set to 1, the p1dr values are read. if a port 1 read is performed while p1ddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, port1 contents are determined by the pin states, as p1ddr and p1dr are initialized. port1 retains its prior state by a manual reset or in software standby mode.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 348 of 1220 rej09b0186-0300o 10.2.3 pin functions port 1 pins also function as ppg output pins (po15 to po8), tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, and tiocb2), external interrupt input pins ( irq0 and irq1 ), and 14-bit pwm output pins (pwm2 and pwm3). port 1 pin functions are shown in table 10.3. table 10.3 port 1 pin functions pin selection method and pin functions p17/po15/ tiocb2/pwm3/ tclkd the pin function is switched as shown below according to the combination of the tpu channel 2 setting (by bits md3 to md0 in tmdr2, bits iob3 to iob0 in tior2, and bits cclr1 and cclr0 in tcr2), bits tpsc2 to tpsc0 in tcr0 and tcr5, oeb bit in dacr3, bit nder15 in nderh, and bit p17ddr. tpu channel 2 setting table below (1) table below (2) oeb ? 0001 p17ddr ? 0 1 1 ? nder15 ? ? 0 1 ? pin function tiocb2 output p17 input p17 output po15 output pwm3 output tiocb2 input * 1 tclkd input * 2 notes: 1. tiocb2 input when md3 to md0 = b'0000 or b'01xx, and iob3 = 1. 2. tclkd input when the setting for either tcr0 or tcr5 is: tpsc2 to tpsc0 = b'111. tclkd input when channels 2 and 4 are set to phase counting mode. tpu channel 2 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000, b'01xx b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 ? b'xx00 other than b'xx00 cclr1, cclr0 ????other than b'10 b'10 output function ? output compare output ??pwm mode 2 output ? x: don?t care
section 10 i/o ports rev. 3.00 jan 11, 2005 page 349 of 1220 rej09b0186-0300o pin selection method and pin functions p16/po14/ tioca2/pwm2/ irq1 the pin function is switched as shown below according to the combination of the tpu channel 2 setting (by bits md3 to md0 in tmdr2, bits ioa3 to ioa0 in tior2, and bits cclr1 and cclr0 in tcr2), oea bit in dacr3, bit nder14 in nderh, and bit p16ddr. tpu channel 2 setting table below (1) table below (2) oea ? 0001 p16ddr ? 0 1 1 ? nder14 ? ? 0 1 ? pin function tioca2 output p16 input p16 output po14 output pwm2 output tioca2 input * 1 irq1 input tpu channel 2 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 ????other than b'01 b'01 output function ? output compare output ? pwm mode 1 output * 2 pwm mode 2 output ? x: don?t care notes: 1. tioca2 input when md3 to md0 = b'0000 or b'01xx, and ioa3 = 1. 2. tiocb2 output is disabled.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 350 of 1220 rej09b0186-0300o pin selection method and pin functions p15/po13/ tiocb1/tclkc the pin function is switched as shown below according to the combination of the tpu channel 1 setting (by bits md3 to md0 in tmdr1, bits iob3 to iob0 in tior1, and bits cclr1 and cclr0 in tcr1), bits tpsc2 to tpsc0 in tcr0, tcr2, tcr4, and tcr5, bit nder13 in nderh, and bit p15ddr. tpu channel 1 setting table below (1) table below (2) p15ddr ? 0 1 1 nder13 ? ? 0 1 pin function tiocb1 output p15 input p15 output po13 output tiocb1 input * 1 tclkc input * 2 notes: 1. tiocb1 input when md3 to md0 = b'0000 or b'01xx, and iob3 to iob0 = b'10xx. 2. tclkc input when the setting for either tcr0 or tcr2 is: tpsc2 to tpsc0 = b'110; or when the setting for either tcr4 or tcr5 is tpsc2 to tpsc0 = b'101. tclkc input when channels 2 and 4 are set to phase counting mode. tpu channel 1 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000, b'01xx b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 ? b'xx00 other than b'xx00 cclr1, cclr0 ???? other than b'10 b'10 output function ? output compare output ??pwm mode 2 output ? x: don?t care
section 10 i/o ports rev. 3.00 jan 11, 2005 page 351 of 1220 rej09b0186-0300o pin selection method and pin functions p14/po12/ tioca1/ irq0 the pin function is switched as shown below according to the combination of the tpu channel 1 setting (by bits md3 to md0 in tmdr1, bits ioa3 to ioa0 in tior1, and bits cclr1 and cclr0 in tcr1), bit nder12 in nderh, and bit p14ddr. tpu channel 1 setting table below (1) table below (2) p14ddr ? 0 1 1 nder12 ? ? 0 1 pin function tioca1 output p14 input p14 output po12 output tioca1 input * 1 irq0 input tpu channel 1 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr1, cclr0 ????other than b'01 b'01 output function ? output compare output ?pwm mode 1 output * 2 pwm mode 2 output ? x: don't care notes: 1. tioca1 input when md3 to md0 = b'0000 or b'01xx, and ioa3 to ioa0 = b'10xx. 2. tiocb1 output is disabled.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 352 of 1220 rej09b0186-0300o pin selection method and pin functions p13/po11/ tiocd0/tclkb the pin function is switched as shown below according to the combination of the tpu channel 0 setting (by bits md3 to md0 in tmdr0, bits iod3 to iod0 in tior0l, and bits cclr2 to cclr0 in tcr0), bits tpsc2 to tpsc0 in tcr0 to tcr2, bit nder11 in nderh, and bit p13ddr. tpu channel 0 setting table below (1) table below (2) p13ddr ? 0 1 1 nder11 ? ? 0 1 pin function tiocd0 output p13 input p13 output po11 output tiocd0 input * 1 tclkb input * 2 notes: 1. tiocd0 input when md3 to md0 = b'0000, and iod3 to iod0 = b'10xx. 2. tclkb input when the setting for tcr0 to tcr2 is: tpsc2 to tpsc0 = b'101. tclkb input when channels 1 and 5 are set to phase counting mode. tpu channel 0 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iod3 to iod0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 ? b'xx00 other than b'xx00 cclr2 to cclr0 ????other than b'110 b'110 output function ? output compare output ?? pwm mode 2 output ? x: don?t care
section 10 i/o ports rev. 3.00 jan 11, 2005 page 353 of 1220 rej09b0186-0300o pin selection method and pin functions p12/po10/ tiocc0/tclka the pin function is switched as shown below according to the combination of the tpu channel 0 setting (by bits md3 to md0 in tmdr0, bits ioc3 to ioc0 in tior0l, and bits cclr2 to cclr0 in tcr0), bits tpsc2 to tpsc0 in tcr0 to tcr5, bit nder10 in nderh, and bit p12ddr. tpu channel 0 setting table below (1) table below (2) p12ddr ? 0 1 1 nder10 ? ? 0 1 pin function tiocc0 output p12 input p12 output po10 output tiocc0 input * 1 tclka input * 2 tpu channel 0 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000 b'001x b'0010 b'0011 ioc3 to ioc0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 ????other than b'101 b'101 output function ? output compare output ?pwm mode 1 output * 3 pwm mode 2 output ? x: don?t care notes: 1. tiocc0 input when md3 to md0 = b'0000, and ioc3 to ioc0 = b'10xx. 2. tclka input when the setting for tcr0 to tcr5 is: tpsc2 to tpsc0 = b'100. tclka input when channels 1 and 5 are set to phase counting mode. 3. tiocd0 output is disabled. when bfa = 1 or bfb = 1 in tmdr0, output is disabled and setting (2) applies.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 354 of 1220 rej09b0186-0300o pin selection method and pin functions p11/po9/tiocb0 the pin function is switched as shown below according to the combination of the tpu channel 0 setting (by bits md3 to md0 in tmdr0, and bits iob3 to iob0 in tior0h), bit nder9 in nderh, and bit p11ddr. tpu channel 0 setting table below (1) table below (2) p11ddr ? 0 1 1 nder9 ? ? 0 1 pin function tiocb0 output p11 input p11 output po9 output tiocb0 input * note: * tiocb0 input when md3 to md0 = b'0000, and iob3 to iob0 = b'10xx. tpu channel 0 setting (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 ? b'xx00 other than b'xx00 cclr2 to cclr0 ???? other than b'010 b'010 output function ? output compare output ?? pwm mode 2 output ? x: don?t care
section 10 i/o ports rev. 3.00 jan 11, 2005 page 355 of 1220 rej09b0186-0300o pin selection method and pin functions p10/po8/tioca0 the pin function is switched as shown below according to the combination of the tpu channel 0 setting (by bits md3 to md0 in tmdr0, bits ioa3 to ioa0 in tior0h, and bits cclr2 to cclr0 in tcr0), bit nder8 in nderh, and bit p10ddr. tpu channel 0 setting table below (1) table below (2) p10ddr ? 0 1 1 nder8 ? ? 0 1 pin function tioca0 output p10 input p10 output po8 output tioca0 input * 1 tpu channel 0 setting (2) (1) (2) (1) (1) (2) md3 to md0 b'0000 b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 ???? other than b'001 b'001 output function ? output compare output ? pwm mode 1 output * 2 pwm mode 2 output ? x: don?t care notes: 1. tioca0 input when md3 to md0 = b'0000, and ioa3 to ioa0 = b'10xx. 2. tiocb0 output is disabled.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 356 of 1220 rej09b0186-0300o 10.3 port 2 10.3.1 overview port 2 is an 8-bit i/o port. port 2 pins also function as tpu i/o pins (tioca3, tiocb3, tiocc3, tiocd3, tioca4, tiocb4, tioca5, tiocb5) and ppg output pins (po7 to po0). port 2 pin functions are the same in all operating modes. the port 2 pin configuration is shown in figure 10.2. p27 p26 p25 p24 p23 p22 p21 p20 (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / / tiocb5 (i/o) / tioca5 (i/o) / tiocb4 (i/o) / tioca4 (i/o) / tiocd3 (i/o) / tiocc3 (i/o) / tiocb3 (i/o) / tioca3 (i/o) po7 (output) po6 (output) po5 (output) po4 (output) po3 (output) po2 (output) po1 (output) po0 (output) port 2 pins (functions in modes 4 to 7) port 2 figure 10.2 port 2 pin functions 10.3.2 register configuration table 10.4 shows the port 2 register configuration. table 10.4 port 2 register configuration name abbreviation r/w initial value address * port 2 data direction register p2ddr w h'00 h'fe31 port 2 data register p2dr r/w h'00 h'ff01 port 2 register port2 r h'00 h'ffb1 note: * lower 16 bits of the address.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 357 of 1220 rej09b0186-0300o (1) port 2 data direction register (p2ddr) bit:76543210 p27ddr p26ddr p25ddr p24ddr p23ddr p22ddr p21ddr p20ddr initial value:00000000 r/w:wwwwwwww p2ddr is an 8-bit write-only register that can select input or output for each pin in port 2. p2ddr cannot be read; if it is, an undefined value w ill be returned. a pin in port 2 becomes an output port if the corresponding p2ddr bit is set to 1, and an input port if the bit is cleared to 0. p2ddr is initialized to h'00 by a power-on reset and in hardware standby mode. it maintains its previous state in a manual reset and in software standby mode. ppg and tpu are initialized by a manual reset, so the pin states are determined by the specification of p2ddr and p2dr. (2) port 2 data register (p2dr) bit:76543210 p27dr p26dr p25dr p24dr p23dr p22dr p21dr p20dr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w p2dr is an 8-bit readable/writable register that stores output data for port 2 pins (p27 to p20). p2dr is initialized to h'00 by a power-on reset and in hardware standby mode. it maintains its previous state in a manual reset and in software standby mode.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 358 of 1220 rej09b0186-0300o (3) port 2 register (port2) bit:76543210 p27 p26 p25 p24 p23 p22 p21 p20 initial value : ? * ? * ? * ? * ? * ? * ? * ? * r/w:rrrrrrrr note: * determined by state of pins p27 to p20. port2 is an 8-bit read-only register that shows the pin states. writing of output data for the port 2 pins (p27 to p20) must always be performed on p2dr. if a port 2 read is performed while p2ddr bits are set to 1, the p2dr values are read. if a port 2 read is performed while p2ddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, port2 contents are determined by the pin states, as p2ddr and p2dr are initialized. port2 maintains its previous state in a manual reset and in software standby mode.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 359 of 1220 rej09b0186-0300o 10.3.3 pin functions port 2 pins also function as tpu i/o pins (tioca3, tiocb3, tiocc3, tiocd3, tioca4, tiocb4, tioca5, tiocb5) and ppg output pins (po7 to po0). port 2 pin functions are shown in table 10.5. table 10.5 port 2 pin functions pin selection method and pin functions p27/po7/tiocb5 the pin function is switched as shown below according to the combination of the tpu channel 5 settings (bits md3 to md0 in tmdr, bits iob3 to iob0 in tior5, and bits cclr1 and cclr0 in tcr5), bit nder7 in nderl, and bit p27ddr. tpu channel 5 settings (1) in table below (2) in table below p27ddr ? 011 nder7 ?? 01 pin function tiocb5 output p27 input p27 output po7 output tiocb5 input * note: * tiocb5 input when md3 to md0 = b'0000 and iob3 to iob0 = b'1xxx. tpu channel 5 settings (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iob3 to iob0 b'0000 b'1000 b'1xxx b'0001 to b'0011 b'0101 to b'0111 ? other than b'xx00 other than b'xx00 cclr1 to cclr0 ???? other than b'10 b'10 output function ? output compare output ?? pwm mode 2 output ? x: don ? t care
section 10 i/o ports rev. 3.00 jan 11, 2005 page 360 of 1220 rej09b0186-0300o pin selection method and pin functions p26/po6/tioca5 the pin function is switched as shown below according to the combination of the tpu channel 5 settings (bits md3 to md0 in tmdr, bits ioa3 to ioa0 in tior5, and bits cclr1 and cclr0 in tcr5), bit nder6 in nderl, and bit p26ddr. tpu channel 5 settings (1) in table below (2) in table below p26ddr ? 011 nder6 ?? 01 pin function tioca5 output p26 input p26 output po6 output tioca5 input * 1 tpu channel 5 settings (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr1 to cclr0 ???? other than b'01 b'01 output function ? output compare output ? pwm mode 1 output * 2 pwm mode 2 output ? x: don ? t care notes: 1. tioca5 input when md3 to md0 = b'0000 and ioa3 to ioa0 = b'1xxx. 2. tiocb5 output is disabled.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 361 of 1220 rej09b0186-0300o pin selection method and pin functions p25/po5/tiocb4 the pin function is switched as shown below according to the combination of the tpu channel 4 settings (bits md3 to md0 in tmdr, bits iob3 to iob0 in tior4, and bits cclr1 and cclr0 in tcr4), bit nder5 in nderl, and bit p25ddr. tpu channel 4 settings (1) in table below (2) in table below p25ddr ? 011 nder5 ?? 01 pin function tiocb4 output p25 input p25 output po5 output tiocb4 input * note: * tiocb4 input when md3 to md0 = b'0000 and iob3 to iob0 = b'10xx. tpu channel 4 settings (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 ? other than b'xx00 other than b'xx00 cclr1 to cclr0 ???? other than b'10 b'10 output function ? output compare output ?? pwm mode 2 output ? x: don ? t care
section 10 i/o ports rev. 3.00 jan 11, 2005 page 362 of 1220 rej09b0186-0300o pin selection method and pin functions p24/po4/tioca4 the pin function is switched as shown below according to the combination of the tpu channel 4 settings (bits md3 to md0 in tmdr, bits ioa3 to ioa0 in tior4, and bits cclr1 and cclr0 in tcr4), bit nder4 in nderl, and bit p24ddr. tpu channel 4 settings (1) in table below (2) in table below p24ddr ? 011 nder4 ?? 01 pin function tioca4 output p24 input p24 output po4 output tioca4 input * 1 tpu channel 4 settings (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr1 to cclr0 ???? other than b'01 b'01 output function ? output compare output ? pwm mode 1 output * 2 pwm mode 2 output ? x: don ? t care notes: 1. tioca4 input when md3 to md0 = b'0000 and ioa3 to ioa0 = b'10xx. 2. tiocb4 output is disabled.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 363 of 1220 rej09b0186-0300o pin selection method and pin functions p23/po3/tiocd3 the pin function is switched as shown below according to the combination of the tpu channel 3 settings (bits md3 to md0 in tmdr, bits iod3 to iod0 in tior3l, and bits cclr2 to cclr0 in tcr3), bit nder3 in nderl, and bit p23ddr. tpu channel 3 settings (1) in table below (2) in table below p23ddr ? 011 nder3 ?? 01 pin function tiocd3 output p23 input p23 output po3 output tiocd3 input * note: * tiocd3 input when md3 to md0 = b'0000 and iob3 to iob0 = b'10xx. tpu channel 3 settings (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iod3 to iod0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 ? other than b'xx00 other than b'xx00 cclr2 to cclr0 ???? other than b'110 b'110 output function ? output compare output ?? pwm mode 2 output ? x: don ? t care
section 10 i/o ports rev. 3.00 jan 11, 2005 page 364 of 1220 rej09b0186-0300o pin selection method and pin functions p22/po2/tiocc3 the pin function is switched as shown below according to the combination of the tpu channel 3 settings (bits md3 to md0 in tmdr, bits ioc3 to ioc0 in tior3l, and bits cclr2 to cclr0 in tcr3), bit nder2 in nderl, and bit p22ddr. tpu channel 3 settings (1) in table below (2) in table below p22ddr ? 011 nder2 ?? 01 pin function tiocc3 output p22 input p22 output po2 output tiocc3 input * 1 tpu channel 3 settings (2) (1) (2) (1) (1) (2) md3 to md0 b'0000 b'001x b'0010 b'0011 ioc3 to ioc0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr2 to cclr0 ???? other than b'101 b'101 output function ? output compare output ? pwm mode 1 output * 2 pwm mode 2 output ? x: don ? t care notes: 1. tiocc3 input when md3 to md0 = b'0000 and ioa3 to ioa0 = b'10xx. 2. tiocd3 output is disabled.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 365 of 1220 rej09b0186-0300o pin selection method and pin functions p21/po1/tiocb3 the pin function is switched as shown below according to the combination of the tpu channel 3 settings (bits md3 to md0 in tmdr, bits iob3 to iob0 in tior3h, and bits cclr2 to cclr0 in tcr3), bit nder1 in nderl, and bit p21ddr. tpu channel 3 settings (1) in table below (2) in table below p21ddr ? 011 nder1 ?? 01 pin function tiocb3 output p21 input p21 output po1 output tiocb3 input * note: * tiocb3 input when md3 to md0 = b'0000 and iob3 to iob0 = b'10xx. tpu channel 3 settings (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 ? other than b'xx00 other than b'xx00 cclr2 to cclr0 ???? other than b'010 b'010 output function ? output compare output ?? pwm mode 2 output ? x: don ? t care
section 10 i/o ports rev. 3.00 jan 11, 2005 page 366 of 1220 rej09b0186-0300o pin selection method and pin functions p20/po0/tioca3 the pin function is switched as shown below according to the combination of the tpu channel 3 settings (bits md3 to md0 in tmdr, bits ioa3 to ioa0 in tior3h, and bits cclr2 to cclr0 in tcr3), bit nder0 in nderl, and bit p20ddr. tpu channel 3 settings (1) in table below (2) in table below p20ddr ? 011 nder0 ?? 01 pin function tioca3 output p20 input p20 output po0 output tioca3 input * 1 tpu channel 3 settings (2) (1) (2) (1) (1) (2) md3 to md0 b'0000 b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr2 to cclr0 ???? other than b'001 b'001 output function ? output compare output ? pwm mode 1 output * 2 pwm mode 2 output ? x: don ? t care notes: 1. tioca3 input when md3 to md0 = b'0000 and ioa3 to ioa0 = b'10xx. 2. tiocb3 output is disabled.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 367 of 1220 rej09b0186-0300o 10.4 port 3 10.4.1 overview port 3 is an 8-bit i/o port. port 3 is a multi-purpose port for sci i/o pins (txd0, rxd0, sck0, irtxd, irrxd, txd1, rxd1, sck1, txd4, rxd4, sck4), external interrupt input pins ( irq4 , irq5 ) and iic i/o pins (scl0, sda0, scl1, sda1). all of the port 3 pin functions have the same operating mode. the configuration for each of the port 3 pins is shown in figure 10.3. p37 p36 p35 / sck4 (i/o) / scl0 (i/o) / irq5 (input) p34 p33 p32 p31 p30 (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / txd4 (output) rxd4 (input) sck1 (i/o) rxd1 (input) / sda0 (i/o) txd1 (input) / scl1 (i/o) sck0 (input / output) / sda1 (i/o) / irq4 (input) rxd0 (input) / irrxd (input) txd0 (output) / irtxd (output) port 3 pins port 3 figure 10.3 port 3 pin functions 10.4.2 register configuration table 10.6 shows the configuration of port 3 registers. table 10.6 port 3 register configuration name abbreviation r/w initial value address * port 3 data direction register p3ddr w h'00 h'fe32 port 3 data register p3dr r/w h'00 h'ff02 port 3 register port3 r undefined h'ffb2 port 3 open drain control register p3odr r/w h'00 h'fe46 note: * indicates the lower-place 16 bits.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 368 of 1220 rej09b0186-0300o (1) port 3 data direction register (p3ddr) 7 p37ddr 0 w bit : initial value : r/w : 6 p36ddr 0 w 5 p35ddr 0 w 4 p34ddr 0 w 3 p33ddr 0 w 2 p32ddr 0 w 1 p31ddr 0 w 0 p30ddr 0 w p3ddr is an 8-bit write-dedicated register, which specifies the i/o for each port 3 pin by bit. read is disenabled. if a read is carried out, undefined values are read out. by setting p3ddr to 1, the corresponding port 3 pins become output, and be clearing to 0 they become input. p3ddr is initialized to h'00 by a power-on reset and in hardware standby mode. the previous state is maintained by a manual reset and in software standby mode. sci and iic are initialized by a manual reset, so the pin states are determined by the specification of p3ddr and p3dr. (2) port 3 data register (p3dr) 7 p37dr 0 r/w bit : initial value : r/w : 6 p36dr 0 r/w 5 p35dr 0 r/w 4 p34dr 0 r/w 3 p33dr 0 r/w 2 p32dr 0 r/w 1 p31dr 0 r/w 0 p30dr 0 r/w p3dr is an 8-bit readable/writable register, which stores the output data of port 3 pins (p35 to p30). p3dr is initialized to h'00 by a power-on reset and in hardware standby mode. the previous state is maintained by a manual reset and in software standby mode.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 369 of 1220 rej09b0186-0300o (3) port 3 register (port3) 7 p37 ? * r bit : initial value : r/w : 6 p36 ? * r 5 p35 ? * r 4 p34 ? * r 3 p33 ? * r 2 p32 ? * r 1 p31 ? * r 0 p30 ? * r note: * determined by the state of pins p37 to p30. port3 is an 8-bit read-dedicated register, which reflects the state of pins. write is disenabled. always carry out writing off output data of port 3 pins (p37 to p30) to p3dr without fail. when p3ddr is set to 1, if port 3 is read, the values of p3dr are read. when p3ddr is cleared to 0, if port 3 is read, the states of pins are read out. p3ddr and p3dr are initialized by a power-on reset and in hardware standby mode, so port3 is determined by the state of the pins. the previous state is maintained by a manual reset and in software standby mode. (4) port 3 open drain control register (p3odr) 7 p37ddr 0 w bit : initial value : r/w : 6 p36ddr 0 w 5 p35ddr 0 w 4 p34ddr 0 w 3 p33ddr 0 w 2 p32ddr 0 w 1 p31ddr 0 w 0 p30ddr 0 w p3odr is an 8-bit readable/writable register, which controls the on/off of port 3 pins (p37 to p30). by setting p3odr to 1, the port 3 pins become an open drain out, and when cleared to 0 they become cmos output. p3odr is initialized to h'00 by a power-on reset and in hardware standby mode. the previous state is maintained by a manual reset and in software standby mode.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 370 of 1220 rej09b0186-0300o 10.4.3 pin functions the port 3 pins double as sci i/o input pins (txd0, rxd0, sck0, irtxd, irrxd, txd1, rxd1, sck1, txd4, rxd4, sck4), external interrupt input pins ( irq4 , irq5 ), and iic i/o pins (scl0, sda0, scl1, sda1). the functions of port 3 pins are shown in table 10.7. table 10.7 port 3 pin functions pin selection method and pin functions p37/txd4 switches as follows according to combinations of scr te bit of sci4 and the p37ddr bit. te 0 1 p37ddr 0 1 ? pin function p37 input pin p37 output pin * txd4 output pin note: * when p37odr = 1, it becomes nmos open drain output. p36/rxd4 switches as follows according to combinations of scr re bit of sci4 and the p36ddr bit. re 0 1 p36ddr 0 1 ? pin function p36 input pin p36 output pin * rxd4 input pin note: * when p36odr = 1, it becomes nmos open drain output.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 371 of 1220 rej09b0186-0300o pin selection method and pin functions p35/sck1/ sck4/scl0/ irq5 switches as follows according to combinations of iccr0 ice bit of iic0, smr c/ a bit of sci1 or sci4, scr cke0 and cke1 bits, and the p35ddr bit. when used as a scl0 i/o pin, always be sure to clear the following bits to 0: smr c/ a bits of sci1 or sci4, and scr cke0 and cke1 bits. do not set sck1 and sck4 to simultaneous output. the scl0 output format is nmos open drain output, enabling direct bus driving. ice 0 1 cke1 0 1 0 c/ a 01 ? 0 cke0 0 1 ?? 0 p35ddr 0 1 ???? pin function p35 input pin p35 output pin * sck1/ sck4 output pin * sck1/ sck4 output pin * sck1/ sck4 input pin scl0 i/o pin irq5 input note: * output type is nmos push-pull. when p35odr = 1, it becomes nmos open drain output. p34/rxd1/ sda0 switches as follows according to combinations of iccr0 ice bit of iic0, scr re bit of sci1, and the p34ddr bit. the sda0 output format becomes nmos open drain output, enabling direct bus driving. ice 0 1 re 0 1 ? p34ddr 0 1 ?? pin function p34 input pin p34 output pin * rxd1 input pin sda0 i/o pin note: * output type is nmos push-pull. when p34odr = 1, it becomes nmos open drain tray. p33/txd1/ scl1 switches as follows according to combinations of iccr1 ice bit of iic1, scr te bit of sci1 and the p33ddr bit. the scl1 output format becomes nmos open drain output, enabling direct bus driving. ice 0 1 te 0 1 ? p33ddr 0 1 ?? pin function p33 input pin p33 output pin * txd1 output pin * scl1 i/o pin * note: * when p33odr = 1, it becomes nmos open drain output.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 372 of 1220 rej09b0186-0300o pin selection method and pin functions p32/sck0/ sda1/ irq4 switches as follows according to combinations of iccr1 ice bit of iic1, smr c/ a bit of sci0, scr cke0 and cke1 bits, and the p32ddr bit. if using as an sda1 input pin, always set smr c/ a bit of sci0 and scr cke0 and cke1 bits to 0 without fail. the sda1 output format becomes nmos open drain output, enabling direct bus driving. ice 0 1 cke1 0 1 0 c/ a 01 ? 0 cke0 0 1 ?? 0 p32ddr 0 1 ???? pin function p32 input pin p32 output pin sck0 output pin * sck0 output pin * sck0 input pin sda1 i/o pin irq4 input note: * when p32odr = 1, it becomes nmos open drain output. p31/rxd0/ irrxd switches as follows according to combinations of scr re bit of sci0 and the p31ddr bit. re 0 1 p31ddr 0 1 ? pin function p31 input pin p31 output pin * rxd0/irrxd input pin note: * when p31odr = 1, it becomes nmos open drain output. p30/txd0/ irtxd switches as follows according to combinations of scr te bit of sci0 and the p30ddr bit. te 0 1 p30ddr 0 1 ? pin function p30 input pin p30 output pin * txd0/irtxd output pin * note: * when p30odr = 1, it becomes nmos open drain output.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 373 of 1220 rej09b0186-0300o 10.5 port 4 10.5.1 overview port 4 is an 8-bit input-only port. port 4 pins also function as a/d converter analog input pins (an0 to an7) and d/a converter analog output pins (da0, da1). port 4 pin functions are the same in all operating modes. figure 10.4 shows the port 4 pin configuration. p47 p46 p45 p44 p43 p42 p41 p40 (input) / (input) / (input) / (input) / (input) / (input) / (input) / (input) / an7 (input) / da1 (output) an6 (input) / da0 (output) an5 (input) an4 (input) an3 (input) an2 (input) an1 (input) an0 (input) port 4 pins port 4 figure 10.4 port 4 pin functions
section 10 i/o ports rev. 3.00 jan 11, 2005 page 374 of 1220 rej09b0186-0300o 10.5.2 register configuration table 10.8 shows the port 4 register configuration. port 4 is an input-only port, and does not have a data direction register or data register. table 10.8 port 4 registers name abbreviation r/w initial value address * port 4 register port4 r undefined h'ffb3 note: * lower 16 bits of the address. (1) port 4 register (port4) the pin states are always read when a port 4 read is performed. bit:76543210 p47 p46 p45 p44 p43 p42 p41 p40 initial value : ? * ? * ? * ? * ? * ? * ? * ? * r/w : rrrrrrrr note: * determined by state of pins p47 to p40. 10.5.3 pin functions port 4 pins also function as a/d converter analog input pins (an0 to an7) and d/a converter analog output pins (da0 and da1).
section 10 i/o ports rev. 3.00 jan 11, 2005 page 375 of 1220 rej09b0186-0300o 10.6 port 5 10.6.1 overview port 5 is a 3-bit i/o port. port 5 pins also function as sci2 i/o pins (sck2, rxd2, txd2). port 5 pin functions are the same in all operating modes. the port 5 pin configuration is shown in figure 10.5. p52 p51 p50 (i/o) / (i/o) / (i/o) / sck2 (i/o) rxd2 (input) txd2 (output) port 5 pins (functions in modes 4 to 7) port 5 figure 10.5 port 5 pin functions 10.6.2 register configuration table 10.9 shows the port 5 register configuration. table 10.9 port 5 register configuration name abbreviation r/w initial value * 2 address * 1 port 5 data direction register p5ddr w h'0 h'fe34 port 5 data register p5dr r/w h'0 h'ff04 port 5 register port5 r h'0 h'ffb4 notes: 1. lower 16 bits of the address. 2. lower 3 bits of data.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 376 of 1220 rej09b0186-0300o (1) port 5 data direction register (p5ddr) bit:76543210 ????? p52ddr p51ddr p50ddr initial value : undefined undefined undefined undefined undefined 0 0 0 r/w : ????? www p5ddr is a 3-bit write-only register that can select input or output for each pin in port 5. p5ddr cannot be read; if it is, an undefined value will be returned. a pin in port 5 becomes an output port if the corresponding p5ddr bit is set to 1, and an input port if the bit is cleared to 0. p5ddr is initialized to h'0 (bits 2 to 0) by a power-on reset and in hardware standby mode. it maintains its previous state in a manual reset and in software standby mode. as the sci is initialized by a manual reset, the pin states are determined by the p5ddr and p5dr specifications. (2) port 5 data register (p5dr) bit:76543210 ????? p52dr p51dr p50dr initial value : undefined undefined undefined undefined undefined 0 0 0 r/w : ????? r/w r/w r/w p5dr is a 3-bit readable/writable register that stores output data for port 5 pins (p52 to p50). p5dr is initialized to h'0 (bits 2 to 0) by a power-on reset and in hardware standby mode. it maintains its previous state in a manual reset and in software standby mode.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 377 of 1220 rej09b0186-0300o (3) port 5 register (port5) bit:76543210 ????? p52 p51 p50 initial value : undefined undefined undefined undefined undefined ? * ? * ? * r/w : ????? rrr note: * determined by state of pins p52 to p50. port5 is a 3-bit read-only register that shows the pin states. writing of output data for the port 5 pins (p52 to p50) must always be performed on p5dr. if a port 5 read is performed while p5ddr bits are set to 1, the p5dr values are read. if a port 5 read is performed while p5ddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, port5 contents are determined by the pin states, as p5ddr and p5dr are initialized. port5 maintains its previous state in a manual reset and in software standby mode.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 378 of 1220 rej09b0186-0300o 10.6.3 pin functions port 5 pins also function as sci2 i/o pins (sck2, rxd2, txd2). port 5 pin functions are shown in table 10.10. table 10.10 port 5 pin functions pin selection method and pin functions p52/sck2 the pin function is switched as shown below according to the combination of bit c/ a in smr of sci2, bits cke0 and cke1 in scr, and bit p52ddr. cke1 0 1 c/ a 01 ? cke0 0 1 ?? p52ddr 0 1 ??? pin function p52 input p52 output sck2 output sck2 output sck2 input p51/rxd2 the pin function is switched as shown below according to the combination of bit re in scr of sci2, and bit p51ddr. re 0 1 p51ddr 0 1 ? pin function p51 input p51 output rxd2 input p50/txd2 the pin function is switched as shown below according to the combination of bit te in scr of sci2, and bit p50ddr. te 0 1 p50ddr 0 1 ? pin function p50 input p50 output txd2 output
section 10 i/o ports rev. 3.00 jan 11, 2005 page 379 of 1220 rej09b0186-0300o 10.7 port 7 10.7.1 overview port 7 is an 8-bit i/o port. port 7 is a multipurpose port for the 8-bit timer i/o pins (tmri01, tmci01, tmri23, tmci23, tmo0, tmo1, tmo2, tmo3), bus control output pins ( cs4 to cs7 ), sci i/o pins (sck3, rxd3, txd3) and manual reset input pin ( mres ). the pin functions for p77 to p74 are the same in all operating modes. p73 to p70 pin functions are switched according to operating mode. figure 10.6 shows the configuration for port 7 pins. p77 / p76 / p75 / p74 / p73 / p72 / p71 / p70 / p77 (i/o) / p76 (i/o) / p75 (i/o) / p74 (i/o) / p73 (i/o) / p72 (i/o) / p71 (i/o) / p70 (i/o) / txd3 rxd3 tmo3 sck3 tmo2 / mres tmo1 / cs7 tmo0 / cs6 tmri23 / tmci23 / cs5 tmri01 / tmci01 / cs4 port 7 pins pins functions for modes 4 to 6 modes 7 pin functions port 7 txd3 (output) rxd3 (input) tmo3 (output) / sck3 (i/o) tmo2 (output) / mres (input) tmo1 (output) / cs7 (output) tmo0 (output) / cs6 (output) tmri23 (input) / tmci23 (input) / cs5 (output) tmri01 (input) / tmci01 (input) / cs4 (output) p77 (i/o) / p76 (i/o) / p75 (i/o) / p74 (i/o) / p73 (i/o) / p72 (i/o) / p71 (i/o) / p70 (i/o) / txd3 (output) rxd3 (input) tmo3 (output) / sck3 (i/o) tmo2 (output) / mres (input) tmo1 (output) tmo0 (output) tmri23 (input) / tmci23 (input) tmri01 (input) / tmci01 (input) figure 10.6 port 7 pin functions
section 10 i/o ports rev. 3.00 jan 11, 2005 page 380 of 1220 rej09b0186-0300o 10.7.2 register configuration table 10.11 shows the port 7 register configuration. table 10.11 port 7 register configuration name abbreviation r/w initial value address * port 7 data direction register p7ddr w h'00 h'fe36 port 7 data register p7dr r/w h'00 h'ff06 port 7 register port7 r undefined h'ffb6 note: * indicates the lower-place 16 bits of the address. (1) port 7 data direction register (p7ddr) 7 p77ddr 0 w bit : initial value : r/w : 6 p76ddr 0 w 5 p75ddr 0 w 4 p74ddr 0 w 3 p73ddr 0 w 2 p72ddr 0 w 1 p71ddr 0 w 0 p70ddr 0 w p7ddr is an 8-bit write-dedicated register, which specifies the i/o for each port 7 pin by bit. read is disenabled. if a read is carried out, undefined values are read out. by setting p7ddr to 1, the corresponding port 7 pins become output, and by clearing to 0 they become input. p7ddr is initialized to h'00 by a power-on reset and in hardware standby mode. the previous state is maintained by a manual reset and in software standby mode. the 8-bit timer and sci are initialized by a manual reset, so the pin states are determined by the specification of p7ddr and p7dr.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 381 of 1220 rej09b0186-0300o (2) port 7 data register (p7dr) 7 p77dr 0 r/w bit : initial value : r/w : 6 p76dr 0 r/w 5 p75dr 0 r/w 4 p74dr 0 r/w 3 p73dr 0 r/w 2 p72dr 0 r/w 1 p71dr 0 r/w 0 p70dr 0 r/w p7dr is an 8-bit readable/writable register, which stores the output data of port 7 pins (p77 to p70). p7dr is initialized to h'00 by a power-on reset and in hardware standby mode. the previous state is maintained by a manual reset and in software standby mode. (3) port 7 register (port7) 7 p77 ? * r bit : initial value : r/w : 6 p76 ? * r 5 p75 ? * r 4 p74 ? * r 3 p73 ? * r 2 p72 ? * r 1 p71 ? * r 0 p70 ? * r note: * determined by the state of pins p77 to p70. port7 is an 8-bit read-dedicated register, which reflects the state of pins. write is disenabled. always carry out writing off output data of port 7 pins (p77 to p70) to p7dr without fail. when p7ddr is set to 1, if port 7 is read, the values of p7dr are read. when p7ddr is cleared to 0, if port 7 is read, the states of pins are read out. p7ddr and p7dr are initialized by a power-on reset and in hardware standby mode, so port7 is determined by the state of the pins. the previous state is maintained by a manual reset and in software standby mode.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 382 of 1220 rej09b0186-0300o 10.7.3 pin functions the pins of port 7 are multipurpose pins which function as 8-bit timer i/o pins, (tmri01, tmci01, tmri23, tmci23, tmo0, tmo1, tmo2, tmo3), bus control output pins ( cs4 to cs7 ), sci i/o pins (sck3, rxd3, txd3) and manual reset input pin ( mres ). table 10.12 shows the functions of port 7 pins. table 10.12 port 7 pin functions pin selection method and pin functions p77/txd3 switches as follows according to combinations of scr te bit of sci3, and the p77ddr bit. te 0 1 p77ddr 0 1 ? pin function p77 input pin p77 output pin txd3 output pin p76/rxd3 switches as follows according to combinations of scr re bit of sci3 and the p76ddr bit. re 0 1 p76ddr 0 1 ? pin function p76 input pin p76 output pin rxd3 i/o pin p75/tmo3/ sck3 switches as follows according to combinations of smr c/ a bit of sci3, scr cke0 and cke1 bits, tcsr3 os3 to os0 bits of the 8-bit timer, and the p75ddr bit. os3 to os0 all 0 any is 1 cke1 0 1 ? c/ a 01 ?? cke0 0 1 ??? p75ddr 0 1 ???? pin function p75 input pin p75 output pin sck3 output pin sck3 output pin sck3 input pin tmo3 output
section 10 i/o ports rev. 3.00 jan 11, 2005 page 383 of 1220 rej09b0186-0300o pin selection method and pin functions p74/tmo2/ mres switches as follows according to combinations of tcsr2 os3 to os0 bits of the 8- bit timer, syscr mrese bit and the p74ddr bit. mrese 0 1 os3 to os0 all 0 any is 1 ? p74ddr 0 1 ?? pin function p74 input pin p74 output pin tmo2 output mres input pin p73/tmo1/ cs7 switches as follows according to combinations of operating mode and tcsr1 os3 to os0 bits of the 8-bit timer, and the p73ddr bit. operating mode modes 4 to 6 mode 7 os3 to os0 all 0 any is 1 all 0 any is 1 p73ddr 0 1 ? 01 ? pin function p73 input pin cs7 output pin tmo1 output p73 input pin p73 output pin tmo1 output p72/tmo0/ cs6 switches as follows according to combinations of operating mode and os3 to os0 bits of 8-bit timer tcsr0, and the p72ddr bit. operating mode modes 4 to 6 mode 7 os3 to os0 all 0 any is 1 all 0 any is 1 p72ddr 0 1 ? 01 ? pin function p72 input pin cs6 output pin tmo0 output p72 input pin p72 output pin tmo0 output
section 10 i/o ports rev. 3.00 jan 11, 2005 page 384 of 1220 rej09b0186-0300o pin selection method and pin functions switches as follows according to operating mode and p71ddr. operating mode modes 4 to 6 mode 7 p71ddr0101 pin function p71 input pin cs5 output p71 input pin p71 output pin p71/tmri23/ tmci23/ cs5 tmri23, tmci23 input ? tmri23, tmci23 input switches as follows according to operating mode and p70ddr. operating mode modes 4 to 6 mode 7 p70ddr0101 pin function p70 input pin cs4 output p70 input pin p70 output pin p70/tmri01/ tmci01/ cs4 tmri01, tmci01 input ? tmri01, tmci01 input
section 10 i/o ports rev. 3.00 jan 11, 2005 page 385 of 1220 rej09b0186-0300o 10.8 port 8 10.8.1 overview port 8 is a 7-bit i/o port. port 8 pins also function as dmac input pins ( dreq1 , dreq0 ) and dmac output pins ( dack1 , dack0 , tend1 , tend0 ). port 8 pin functions are the same in all operating modes. the port 8 pin configuration is shown in figure 10.7. p86 p85 p84 p83 p82 p81 p80 (i/o) (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / dack1 (output) dack0 (output) tend1 (output) tend0 (output) dreq1 (input) dreq0 (input) port 8 pins (functions in modes 4 to 7) port 8 figure 10.7 port 8 pin functions 10.8.2 register configuration table 10.13 shows the port 8 register configuration. table 10.13 port 8 register configuration name abbreviation r/w initial value address * port 8 data direction register p8ddr w h'00 h'fe37 port 8 data register p8dr r/w h'00 h'ff07 port 8 register port8 r h'00 h'ffb7 note: * lower 16 bits of the address.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 386 of 1220 rej09b0186-0300o (1) port 8 data direction register (p8ddr) bit:76543210 ? p86ddr p85ddr p84ddr p83ddr p82ddr p81ddr p80ddr initial value : undefined 0000000 r/w : ? wwwwwww p8ddr is a 7-bit write-only register that can select input or output for each pin in port 8. p8ddr cannot be read; if it is, an undefined value will be returned. a pin in port 8 becomes an output port if the corresponding p8ddr bit is set to 1, and an input port if the bit is cleared to 0. p8ddr is initialized to h'00 by a power-on reset and in hardware standby mode. it maintains its previous state in a manual reset and in software standby mode. dmac is initialized by a manual reset, so the pin states are determined by the specification of p8ddr and p8dr. (2) port 8 data register (p8dr) bit:76543210 ? p86dr p85dr p84dr p83dr p82dr p81dr p80dr initial value : undefined 0000000 r/w : ? r/w r/w r/w r/w r/w r/w r/w p8dr is a 7-bit readable/writable register that stores output data for port 8 pins (p86 to p80). p8dr is initialized to h'00 by a power-on reset and in hardware standby mode. it maintains its previous state in a manual reset and in software standby mode. dmac is initialized by a manual reset, so the pin states are determined by the specification of p8ddr and p8dr.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 387 of 1220 rej09b0186-0300o (3) port 8 register (port8) bit:76543210 ? p86 p85 p84 p83 p82 p81 p80 initial value : undefined ? * ? * ? * ? * ? * ? * ? * r/w : ? rrrrrrr note: * determined by state of pins p86 to p80. port8 is a 7-bit read-only register that shows the pin states. writing of output data for the port 8 pins (p86 to p80) must always be performed on p8dr. if a port 8 read is performed while p8ddr bits are set to 1, the p8dr values are read. if a port 8 read is performed while p8ddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, port8 contents are determined by the pin states, as p8ddr and p8dr are initialized. port8 maintains its previous state in a manual reset and in software standby mode.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 388 of 1220 rej09b0186-0300o 10.8.3 pin functions port 8 pins also function as dmac input pins ( dreq1 , dreq0 ) and dmac output pins ( dack1 , dack0 , tend1 , tend0 ). port 8 pin functions are shown in table 10.14. table 10.14 port 8 pin functions pin selection method and pin functions p86 the pin function is switched as shown below according to bit p86ddr. p86ddr 0 1 pin function p86 input p86 output p85/ dack1 the pin function is switched as shown below according to the combination of bit sae1 in dmabcr of the dmac, and bit p85ddr. sae1 0 1 p85ddr 0 1 ? pin function p85 input p85 output dack1 output p84/ dack0 the pin function is switched as shown below according to the combination of bit sae0 in dmabcr of the dmac, and bit p84ddr. sae0 0 1 p84ddr 0 1 ? pin function p84 input p84 output dack0 output p83/ tend1 the pin function is switched as shown below according to the combination of bit tee1 in dmabcr of the dmac, and bit p83ddr. tee1 0 1 p83ddr 0 1 ? pin function p83 input p83 output tend1 output p82/ tend0 the pin function is switched as shown below according to the combination of bit tee0 in dmabcr of the dmac, and bit p82ddr. tee0 0 1 p82ddr 0 1 ? pin function p82 input p82 output tend0 output
section 10 i/o ports rev. 3.00 jan 11, 2005 page 389 of 1220 rej09b0186-0300o pin selection method and pin functions p81/ dreq1 the pin function is switched as shown below according to bit p81ddr. p81ddr 0 1 pin function p81 input p81 output dreq1 input p80/ dreq0 the pin function is switched as shown below according to bit p80ddr. p80ddr 0 1 pin function p80 input p80 output dreq0 input
section 10 i/o ports rev. 3.00 jan 11, 2005 page 390 of 1220 rej09b0186-0300o 10.9 port 9 10.9.1 overview port 9 is an 8-bit input-only port. port 9 pins also function as a/d converter analog input pins (an8 to an15) and d/a converter analog output pins (da2, da3). port 9 pin functions are the same in all operating modes. figure 10.8 shows the port 9 pin configuration. p97 p96 p95 p94 p93 p92 p91 p90 (input) / (input) / (input) / (input) / (input) / (input) / (input) / (input) / an15 (input) / da3 (output) an14 (input) / da2 (output) an13 (input) an12 (input) an11 (input) an10 (input) an9 (input) an8 (input) port 9 pins port 9 figure 10.8 port 9 pin functions
section 10 i/o ports rev. 3.00 jan 11, 2005 page 391 of 1220 rej09b0186-0300o 10.9.2 register configuration table 10.15 shows the port 9 register configuration. port 9 is an input-only port, and does not have a data direction register or data register. table 10.15 port 9 registers name abbreviation r/w initial value address * port 9 register port9 r undefined h'ffb8 note: * lower 16 bits of the address. port 9 register (port9): the pin states are always read when a port 9 read is performed. bit:76543210 p97 p96 p95 p94 p93 p92 p91 p90 initial value : ? * ? * ? * ? * ? * ? * ? * ? * r/w:rrrrrrrr note: * determined by state of pins p97 to p90. 10.9.3 pin functions port 9 pins are multipurpose pins which function as a/d converter analog input pins (an8 to an15) and d/a converter analog output pins (da2, da3).
section 10 i/o ports rev. 3.00 jan 11, 2005 page 392 of 1220 rej09b0186-0300o 10.10 port a 10.10.1 overview port a is an 8-bit i/o port. port a pins also function as address bus outputs. the pin functions change according to the operating mode. port a has a built-in mos input pull-up function that can be controlled by software. figure 10.9 shows the port a pin configuration. pa7 / pa6 / pa5 / pa4 / pa3 / pa2 / pa1 / pa0 / pa7 (i/o) / a23 (output) pa6 (i/o) / a22 (output) pa5 (i/o) / a21 (output) pa4 (i/o) / a20 (output) pa3 (i/o) / a19 (output) pa2 (i/o) / a18 (output) pa1 (i/o) / a17 (output) pa0 (i/o) / a16 (output) a23 a22 a21 a20 a19 a18 a17 a16 port a pins pins functions for modes 4 to 6 pin functions in mode 7 port a pa7 (i/o) pa6 (i/o) pa5 (i/o) pa4 (i/o) pa3 (i/o) pa2 (i/o) pa1 (i/o) pa0 (i/o) figure 10.9 port a pin functions
section 10 i/o ports rev. 3.00 jan 11, 2005 page 393 of 1220 rej09b0186-0300o 10.10.2 register configuration table 10.16 shows the port a register configuration. table 10.16 port a registers name abbreviation r/w initial value * address * port a data direction register paddr w h'00 h'fe39 port a data register padr r/w h'00 h'ff09 port a register porta r undefined h'ffb9 port a mos pull-up control register papcr r/w h'00 h'fe40 port a open-drain control register paodr r/w h'00 h'fe47 note: * lower 16 bits of the address. (1) port a data direction register (paddr) bit:76543210 pa7ddr pa6ddr pa5ddr pa4ddr pa3ddr pa2ddr pa1ddr pa0ddr initial value:00000000 r/w:wwwwwwww paddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port a. paddr cannot be read; if it is, an undefined value will be read. paddr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. see section 24.2.1, standby control register (sbycr), for details. ? modes 4 to 6 the corresponding port a pins become address outputs in accordance with the setting of bits ae3 to ae0 in pfcr, irrespective of the value of paddr. when pins are not used as address outputs, setting a paddr bit to 1 makes the corresponding port a pin an output port, while clearing the bit to 0 makes the pin an input port. ? mode 7 setting a paddr bit to 1 makes the corresponding port a pin an output port, while clearing the bit to 0 makes the pin an input port.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 394 of 1220 rej09b0186-0300o (2) port a data register (padr) bit:76543210 pa7dr pa6dr pa5dr pa4dr pa3dr pa2dr pa1dr pa0dr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w padr is an 8-bit readable/writable register that stores output data for the port a pins (pa7 to pa0). padr is initialized to h'00 by a powr-on reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode. (3) port a register (porta) bit:76543210 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 initial value : ? * ? * ? * ? * ? * ? * ? * ? * r/w:rrrrrrrr note: * determined by state of pins pa7 to pa0. porta is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port a pins (pa7 to pa0) must always be performed on padr. if a port a read is performed while paddr bits are set to 1, the padr values are read. if a port a read is performed while paddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, porta contents are determined by the pin states, as paddr and padr are initialized. porta retains its prior state by a manual reset or in software standby mode.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 395 of 1220 rej09b0186-0300o (4) port a mos pull-up control register (papcr) bit:76543210 pa7pcr pa6pcr pa5pcr pa4pcr pa3pcr pa2pcr pa1pcr pa0pcr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w papcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port a on an individual bit basis. in modes 4 to 6, if a pin is in the input state in accordance with the settings in pfcr, and in ddr, setting the corresponding papcr bit to 1 turns on the mos input pull-up for that pin. in mode 7, if a pin is in the input state in accordance with the settings in ddr, setting the corresponding papcr bit to 1 turns on the mos input pull-up for that pin. papcr is initialized by a manual reset or to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state in software standby mode. (5) port a open drain control register (paodr) bit:76543210 pa7odr pa6odr pa5odr pa4odr pa3odr pa2odr pa1odr pa0odr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w paodr is an 8-bit readable/writable register that controls whether pmos is on or off for each port a pin (pa7 to pa0). when pins are not address outputs in accordance with the setting of bits ae3 to ae0 in pfcr, setting a paodr bit makes the corresponding port a pin an nmos open-drain output, while clearing the bit to 0 makes the pin a cmos output. paodr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 396 of 1220 rej09b0186-0300o 10.10.3 pin functions (1) modes 4 to 6 in modes 4 to 6, port a pins function as address outputs according to the setting of ae3 to ae0 in pfcr; when they do not function as address outputs, the pins function as i/o ports. port a pin functions in modes 4 to 6 are shown in figure 10.10. pa7 (i/o) / a23 (output) pa6 (i/o) / a22 (output) pa5 (i/o) / a21 (output) pa4 (i/o) / a20 (output) pa3 (i/o) / a19 (output) pa2 (i/o) / a18 (output) pa1 (i/o) / a17 (output) pa0 (i/o) / a16 (output) port a figure 10.10 port a pin functions (modes 4 to 6) (2) mode 7 in mode 7, port a pins function as i/o ports. input or output can be specified for each pin on an individual bit basis. setting a paddr bit to 1 makes the corresponding port a pin an output port, while clearing the bit to 0 makes the pin an input port. port a pin functions are shown in figure 10.11. pa7 (i/o) pa6 (i/o) pa5 (i/o) pa4 (i/o) pa3 (i/o) pa2 (i/o) pa1 (i/o) pa0 (i/o) port a figure 10.11 port a pin functions (mode 7)
section 10 i/o ports rev. 3.00 jan 11, 2005 page 397 of 1220 rej09b0186-0300o 10.10.4 mos input pull-up function port a has a built-in mos input pull-up function that can be controlled by software. mos input pull-up can be specified as on or off on an individual bit basis. in modes 4 to 6, if a pin is in the input state in accordance with the settings in pfcr and in ddr, setting the corresponding papcr bit to 1 turns on the mos input pull-up for that pin. in mode 7, if a pin is in the input state in accordance with the settings in ddr, setting the corresponding papcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a power-on reset, and in hardware standby mode. the prior state is retained by a manual reset or in software standby mode. table 10.17 summarizes the mos input pull-up states. table 10.17 mos input pull-up states (port a) pin states power-on reset hardware standby mode manual reset software standby mode in other operations address output off off off off off other than above on/off on/off on/off legend: off: mos input pull-up is always off. on/off: on when paddr = 0 and papcr = 1; otherwise off.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 398 of 1220 rej09b0186-0300o 10.11 port b 10.11.1 overview port b is an 8-bit i/o port. port b pins also function as address bus outputs; the pin functions change according to the operating mode. port b has a built-in mos input pull-up function that can be controlled by software. figure 10.12 shows the port b pin configuration. pb7 / a15 pb6 / a14 pb5 / a13 pb4 / a12 pb3 / a11 pb2 / a10 pb1/a9 pb0/a8 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / a15 a14 a13 a12 a11 a10 a9 a8 (output) (output) (output) (output) (output) (output) (output) (output) port b pins pin functions in mode 7 pin functions in modes 4 to 6 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) ( i/o ) port b figure 10.12 port b pin functions
section 10 i/o ports rev. 3.00 jan 11, 2005 page 399 of 1220 rej09b0186-0300o 10.11.2 register configuration table 10.18 shows the port b register configuration. table 10.18 port b registers name abbreviation r/w initial value address * port b data direction register pbddr w h'00 h'fe3a port b data register pbdr r/w h'00 h'ff0a port b register portb r undefined h'ffba port b mos pull-up control register pbpcr r/w h'00 h'fe41 port b open-drain control register pbodr r/w h'00 h'fe48 note: * lower 16 bits of the address. (1) port b data direction register (pbddr) bit:76543210 pb7ddr pb6ddr pb5ddr pb4ddr pb3ddr pb2ddr pb1ddr pb0ddr initial value:00000000 r/w:wwwwwwww pbddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port b. pbddr cannot be read; if it is, an undefined value will be read. pbddr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. see section 24.2.1, standby control register (sbycr), for details. ? modes 4 to 6 the corresponding port b pins become address outputs in accordance with the setting of bits ae3 to ae0 in pfcr, irrespective of the value of the pbddr bits. when pins are not used as address outputs, setting a pbddr bit to 1 makes the corresponding port b pin an output port, while clearing the bit to 0 makes the pin an input port. ? mode 7 setting a pbddr bit to 1 makes the corresponding port b pin an output port, while clearing the bit to 0 makes the pin an input port.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 400 of 1220 rej09b0186-0300o (2) port b data register (pbdr) bit:76543210 pb7dr pb6dr pb5dr pb4dr pb3dr pb2dr pb1dr pb0dr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pbdr is an 8-bit readable/writable register that stores output data for the port b pins (pb7 to pb0). pbdr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode. (3) port b register (portb) bit:76543210 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 initial value : ? * ? * ? * ? * ? * ? * ? * ? * r/w:rrrrrrrr note: * determined by state of pins pb7 to pb0. portb is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port b pins (pb7 to pb0) must always be performed on pbdr. if a port b read is performed while pbddr bits are set to 1, the pbdr values are read. if a port b read is performed while pbddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, portb contents are determined by the pin states, as pbddr and pbdr are initialized. portb retains its prior state in software standby mode.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 401 of 1220 rej09b0186-0300o (4) port b mos pull-up control register (pbpcr) bit:76543210 pb7pcr pb6pcr pb5pcr pb4pcr pb3pcr pb2pcr pb1pcr pb0pcr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pbpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port b on an individual bit basis. in modes 4 to 6, if a pin is in the input state in accordance with the settings in pfcr and in ddr, setting the corresponding pbpcr bit to 1 turns on the mos input pull-up for that pin. in mode 7, if a pin is in the input state in accordance with the settings in ddr, setting the corresponding pbpcr bit to 1 turns on the mos input pull-up for that pin. pbpcr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode. (5) port b open drain control register (pbodr) bit:76543210 pb7odr pb6odr pb5odr pb4odr pb3odr pb2odr pb1odr pb0odr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pbodr is an 8-bit readable/writable register that controls the pmos on/off state for each port b pin (pb7 to pb0). when pins are not address outputs in accordance with the setting of bits ae3 to ae0 in pfcr, setting a pbodr bit makes the corresponding port b pin an nmos open-drain output, while clearing the bit to 0 makes the pin a cmos output. pbodr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 402 of 1220 rej09b0186-0300o 10.11.3 pin functions (1) modes 4 to 6 in modes 4 to 6, the corresponding port b pins become address outputs in accordance with the setting of bits ae3 to ae0 in pfcr. when pins are not used as address outputs, they function as i/o ports. port b pin functions in modes 4 to 6 are shown in figure 10.13. pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 port b (i/o) / a15 (output) (i/o) / a14 (output) (i/o) / a13 (output) (i/o) / a12 (output) (i/o) / a11 (output) (i/o) / a10 (output) (i/o) / a9 (output) (i/o) / a8 (output) figure 10.13 port b pin functions (modes 4 to 6) (2) mode 7 in mode 7, port b pins function as i/o ports. input or output can be specified for each pin on an individual bit basis. setting a pbddr bit to 1 makes the corresponding port b pin an output port, while clearing the bit to 0 makes the pin an input port. port b pin functions in mode 7 are shown in figure 10.14.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 403 of 1220 rej09b0186-0300o pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 port b (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) figure 10.14 port b pin functions (mode 7) 10.11.4 mos input pull-up function port b has a built-in mos input pull-up function that can be controlled by software. mos input pull-up can be specified as on or off on an individual bit basis. in modes 4 to 6, if a pin is in the input state in accordance with the settings in pfcr and in ddr, setting the corresponding pbpcr bit to 1 turns on the mos input pull-up for that pin. in mode 7, if a pin is in the input state in accordance with the settings in ddr, setting the corresponding pbpcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a power-on reset, and in hardware standby mode. the prior state is retained by a manual reset or in software standby mode. table 10.19 summarizes the mos input pull-up states. table 10.19 mos input pull-up states (port b) pin states power-on reset hardware standby mode manual reset software standby mode in other operations address output off off off off off other than above on/off on/off on/off legend: off: mos input pull-up is always off. on/off: on when pbddr = 0 and pbpcr = 1; otherwise off.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 404 of 1220 rej09b0186-0300o 10.12 port c 10.12.1 overview port c is an 8-bit i/o port. port c has a 14-bit pwm output (pwm0, pwm1) and an address bus output function. the pin functions change according to the operating mode. port c has a built-in mos input pull-up function that can be controlled by software. figure 10.15 shows the port c pin configuration. pc7/a7/pwm1 pc6/a6/pwm0 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 port c port c pins pin functions in mode 7 a7 a6 a5 a4 a3 a2 a1 a0 (output) (output) (output) (output) (output) (output) (output) (output) pin functions in modes 4 and 5 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (i/o) / pwm1 (output) (i/o) / pwm0 (output) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) pin functions in mode 6 a7 a6 a5 a4 a3 a2 a1 a0 when pcddr = 1 (output) (output) (output) (output) (output) (output) (output) (output) pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 when pcddr = 0 (input) / pwm1 (output) (input) / pwm0 (output) (input) (input) (input) (input) (input) (input) figure 10.15 port c pin functions
section 10 i/o ports rev. 3.00 jan 11, 2005 page 405 of 1220 rej09b0186-0300o 10.12.2 register configuration table 10.20 shows the port c register configuration. table 10.20 port c registers name abbreviation r/w initial value address * port c data direction register pcddr w h'00 h'fe3b port c data register pcdr r/w h'00 h'ff0b port c register portc r undefined h'ffbb port c mos pull-up control register pcpcr r/w h'00 h'fe42 port c open-drain control register pcodr r/w h'00 h'fe49 note: * lower 16 bits of the address. (1) port c data direction register (pcddr) bit:76543210 pc7ddr pc6ddr pc5ddr pc4ddr pc3ddr pc2ddr pc1ddr pc0ddr initial value:00000000 r/w:wwwwwwww pcddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port c. pcddr cannot be read; if it is, an undefined value will be read. pcddr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when the mode is changed to software standby mode. see section 24.2.1, standby control register (sbycr), for details. ? modes 4 and 5 the corresponding port c pins are address outputs irrespective of the value of the pcddr bits. ? mode 6 setting a pcddr bit to 1 makes the corresponding port c pin an address output, while clearing the bit to 0 makes the pin an input port.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 406 of 1220 rej09b0186-0300o ? mode 7 setting a pcddr bit to 1 makes the corresponding port c pin an output port, while clearing the bit to 0 makes the pin an input port. (2) port c data register (pcdr) bit:76543210 pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pcdr is an 8-bit readable/writable register that stores output data for the port c pins (pc7 to pc0). pcdr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode. (3) port c register (portc) bit:76543210 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 initial value : ? * ? * ? * ? * ? * ? * ? * ? * r/w:rrrrrrrr note: * determined by state of pins pc7 to pc0. portc is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port c pins (pc7 to pc0) must always be performed on pcdr. if a port c read is performed while pcddr bits are set to 1, the pcdr values are read. if a port c read is performed while pcddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, portc contents are determined by the pin states, as pcddr and pcdr are initialized. portc retains its prior state by a manual reset or in software standby mode.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 407 of 1220 rej09b0186-0300o (4) port c mos pull-up control register (pcpcr) bit:76543210 pc7pcr pc6pcr pc5pcr pc4pcr pc3pcr pc2pcr pc1pcr pc0pcr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pcpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port c on an individual bit basis. in modes 6 and 7, if pcpcr is set to 1 when the port is in the input state in accordance with the settings of dacr and pcddr in pwm, the mos input pull-up is set to on. pcpcr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode. (5) port c open drain control register (pcodr) 7 pc7odr 0 r/w bit : initial value : r/w : 6 pc6odr 0 r/w 5 pc5odr 0 r/w 4 pc4odr 0 r/w 3 pc3odr 0 r/w 2 pc2odr 0 r/w 1 pc1odr 0 r/w 0 pc0odr 0 r/w pcddr is an 8-bit read/write register and controls pmos on/off of each pin (pc7 to pc0) of port c. if pcodr is set to 1 by setting ae3 to ae0 in pfcr in mode other than address output mode, port c pins function as nmos open drain outputs and when the setting is cleared to 0, the pins function as cmos outputs. pcodr is initialized to h'00 in power-on reset mode or hardware standby mode. pcodr retains the last state in manual reset mode or software standby mode.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 408 of 1220 rej09b0186-0300o 10.12.3 pin functions for each mode (1) modes 4 and 5 in mode 4 and 5, port c pins function as address outputs automatically. figure 10.16 shows the port c pin functions. a7 a6 a5 a4 a3 a2 a1 a0 (output) (output) (output) (output) (output) (output) (output) (output) port c figure 10.16 port c pin functions (modes 4 and 5) (2) mode 6 in mode 6, port c pints function as address outputs or input ports and i/o can be specified in bit units. when each bit in pcddr is set to 1, the corresponding pin functions as an address output and when the bit cleared to 0, the pin functions as a pwm output and an input port. figure 10.17 shows the port c pin functions.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 409 of 1220 rej09b0186-0300o a7 a6 a5 a4 a3 a2 a1 a0 (output) (output) (output) (output) (output) (output) (output) (output) pcddr= 1 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (input) / pwm1 (output) (input) / pwm0 (output) (input) (input) (input) (input) (input) (input) pcddr= 0 port c figure 10.17 port c pin functions (mode 6) (3) mode 7 in mode 7, port c pins function as pwm outputs and i/o ports and i/o can be specified for each pin in bit units. when each bit in pcddr is set to 1, the corresponding pin functions as an output port and when the bit is cleared to 0, the pin functions as an input port. figure 10.18 shows the port c pin functions. pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (i/o) / pwm1 (output) (i/o) / pwm0 (output) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) port c figure 10.18 port c pin functions (mode 7)
section 10 i/o ports rev. 3.00 jan 11, 2005 page 410 of 1220 rej09b0186-0300o 10.12.4 mos input pull-up function port c has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis. in modes 6 and 7, when pcpcr is set to 1 in the input state by setting of dacr and pcddr, the mos input pull-up is set to on. the mos input pull-up function is in the off state after a power-on reset, and in hardware standby mode. the prior state is retained by a manual reset or in software standby mode. table 10.21 summarizes the mos input pull-up states. table 10.21 mos input pull-up states (port c) pin states power-on reset hardware standby mode manual reset software standby mode in other operations address output or pwm output off off off off off other than above on/off on/off on/off legend: off: mos input pull-up is always off. on/off: on when pcddr = 0 and pcpcr = 1; otherwise off.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 411 of 1220 rej09b0186-0300o 10.13 port d 10.13.1 overview port d is an 8-bit i/o port. port d has a data bus i/o function, and the pin functions change according to the operating mode. port d has a built-in mos input pull-up function that can be controlled by software. figure 10.19 shows the port d pin configuration. pd7 / d15 pd6 / d14 pd5 / d13 pd4 / d12 pd3 / d11 pd2 / d10 pd1/d9 pd0/d8 port d d15 d14 d13 d12 d11 d10 d9 d8 (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) port d pins pin functions in modes 4 to 6 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) pin functions in mode 7 figure 10.19 port d pin functions
section 10 i/o ports rev. 3.00 jan 11, 2005 page 412 of 1220 rej09b0186-0300o 10.13.2 register configuration table 10.22 shows the port d register configuration. table 10.22 port d registers name abbreviation r/w initial value address * port d data direction register pdddr w h'00 h'fe3c port d data register pddr r/w h'00 h'ff0c port d register portd r undefined h'ffbc port d mos pull-up control register pdpcr r/w h'00 h'fe43 note: * lower 16 bits of the address. (1) port d data direction register (pdddr) bit:76543210 pd7ddr pd6ddr pd5ddr pd4ddr pd3ddr pd2ddr pd1ddr pd0ddr initial value:00000000 r/w:wwwwwwww pdddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port d. pdddr cannot be read; if it is, an undefined value will be read. pdddr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode. ? modes 4 to 6 the input/output direction specification by pdddr is ignored, and port d is automatically designated for data i/o. ? mode 7 setting a pdddr bit to 1 makes the corresponding port d pin an output port, while clearing the bit to 0 makes the pin an input port.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 413 of 1220 rej09b0186-0300o (2) port d data register (pddr) bit:76543210 pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pddr is an 8-bit readable/writable register that stores output data for the port d pins (pd7 to pd0). pddr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode. (3) port d register (portd) bit:76543210 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 initial value : ? * ? * ? * ? * ? * ? * ? * ? * r/w:rrrrrrrr note: * determined by state of pins pd7 to pd0. portd is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port d pins (pd7 to pd0) must always be performed on pddr. if a port d read is performed while pdddr bits are set to 1, the pddr values are read. if a port d read is performed while pdddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, portd contents are determined by the pin states, as pdddr and pddr are initialized. portd retains its prior state by a manual reset or in software standby mode.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 414 of 1220 rej09b0186-0300o (4) port d mos pull-up control register (pdpcr) bit:76543210 pd7pcr pd6pcr pd5pcr pd4pcr pd3pcr pd2pcr pd1pcr pd0pcr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pdpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port d on an individual bit basis. when a pdddr bit is cleared to 0 (input port setting) in mode 7, setting the corresponding pdpcr bit to 1 turns on the mos input pull-up for the corresponding pin. pdpcr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode. 10.13.3 pin functions (1) modes 4 to 6 in modes 4 to 6, port d pins are automatically designated as data i/o pins. port d pin functions in modes 4 to 6 are shown in figure 10.20. d15 d14 d13 d12 d11 d10 d9 d8 port d (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) figure 10.20 port d pin functions (modes 4 to 6)
section 10 i/o ports rev. 3.00 jan 11, 2005 page 415 of 1220 rej09b0186-0300o (2) mode 7 in mode 7, port d pins function as i/o ports. input or output can be specified for each pin on an individual bit basis. setting a pdddr bit to 1 makes the corresponding port d pin an output port, while clearing the bit to 0 makes the pin an input port. port d pin functions in mode 7 are shown in figure 10.21. pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 port d (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) figure 10.21 port d pin functions (mode 7) 10.13.4 mos input pull-up function port d has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in mode 7, and can be specified as on or off on an individual bit basis. when a pdddr bit is cleared to 0 in mode 7, setting the corresponding pdpcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a power-on reset, and in hardware standby mode. the prior state is retained by a manual reset or in software standby mode. table 10.23 summarizes the mos input pull-up states.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 416 of 1220 rej09b0186-0300o table 10.23 mos input pull-up states (port d) modes power-on reset hardware standby mode manual reset software standby mode in other operations 4 to 6 off off off off off 7 on/off on/off on/off legend: off: mos input pull-up is always off. on/off: on when pdddr = 0 and pdpcr = 1; otherwise off.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 417 of 1220 rej09b0186-0300o 10.14 port e 10.14.1 overview port e is an 8-bit i/o port. port e has a data bus i/o function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. port e has a built-in mos input pull-up function that can be controlled by software. figure 10.22 shows the port e pin configuration. pe7/d7 pe6/d6 pe5/d5 pe4/d4 pe3/d3 pe2/d2 pe1/d1 pe0/d0 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / (i/o) / port e pins pin functions in modes 4 to 6 pin functions in mode 7 d7 d6 d5 d4 d3 d2 d1 d0 (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) port e figure 10.22 port e pin functions
section 10 i/o ports rev. 3.00 jan 11, 2005 page 418 of 1220 rej09b0186-0300o 10.14.2 register configuration table 10.24 shows the port e register configuration. table 10.24 port e registers name abbreviation r/w initial value address * port e data direction register peddr w h'00 h'fe3d port e data register pedr r/w h'00 h'ff0d port e register porte r undefined h'ffbd port e mos pull-up control register pepcr r/w h'00 h'fe44 note: * lower 16 bits of the address. (1) port e data direction register (peddr) bit:76543210 pe7ddr pe6ddr pe5ddr pe4ddr pe3ddr pe2ddr pe1ddr pe0ddr initial value:00000000 r/w:wwwwwwww peddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port e. peddr cannot be read; if it is, an undefined value w ill be read. peddr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode. ? modes 4 to 6 when 8-bit bus mode has been selected, port e pins function as i/o ports. setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. when 16-bit bus mode has been selected, the input/output direction specification by peddr is ignored, and port e is designated for data i/o. for details of 8-bit and 16-bit bus modes, see section 7, bus controller. ? mode 7 setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 419 of 1220 rej09b0186-0300o (2) port e data register (pedr) bit:76543210 pe7dr pe6dr pe5dr pe4dr pe3dr pe2dr pe1dr pe0dr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pedr is an 8-bit readable/writable register that stores output data for the port e pins (pe7 to pe0). pedr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode. (3) port e register (porte) bit:76543210 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 initial value : ? * ? * ? * ? * ? * ? * ? * ? * r/w:rrrrrrrr note: * determined by state of pins pe7 to pe0. porte is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port e pins (pe7 to pe0) must always be performed on pedr. if a port e read is performed while peddr bits are set to 1, the pedr values are read. if a port e read is performed while peddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, porte contents are determined by the pin states, as peddr and pedr are initialized. porte retains its prior state by a manual reset or in software standby mode.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 420 of 1220 rej09b0186-0300o (4) port e mos pull-up control register (pepcr) bit:76543210 pe7pcr pe6pcr pe5pcr pe4pcr pe3pcr pe2pcr pe1pcr pe0pcr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pepcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port e on an individual bit basis. when a peddr bit is cleared to 0 (input port setting) with 8-bit bus mode selected in mode 4, 5, or 6, or in mode 7, setting the corresponding pepcr bit to 1 turns on the mos input pull-up for the corresponding pin. pepcr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode. 10.14.3 pin functions (1) modes 4 to 6 in modes 4 to 6, when 8-bit access is designated and 8-bit bus mode is selected, port e pins are automatically designated as i/o ports. setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. when 16-bit bus mode is selected, the input/output direction specification by peddr is ignored, and port e is designated for data i/o. port e pin functions in modes 4 to 6 are shown in figure 10.23.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 421 of 1220 rej09b0186-0300o pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 port e d7 d6 d5 d4 d3 d2 d1 d0 (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) 8-bit bus mode 16-bit bus mod e (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) figure 10.23 port e pin functions (modes 4 to 6) (2) mode 7 in mode 7, port e pins function as i/o ports. input or output can be specified for each pin on a bit- by-bit basis. setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. port e pin functions in mode 7 are shown in figure 10.24. pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 port e (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) (i/o) figure 10.24 port e pin functions (mode 7)
section 10 i/o ports rev. 3.00 jan 11, 2005 page 422 of 1220 rej09b0186-0300o 10.14.4 mos input pull-up function port e has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in modes 4 to 6 when 8-bit bus mode is selected, or in mode 7, and can be specified as on or off on an individual bit basis. when a peddr bit is cleared to 0 in mode 4 to 6 when 8-bit bus mode is selected, or in mode 7, setting the corresponding pepcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a power-on reset, and in hardware standby mode. the prior state is retained by a manual reset or in software standby mode. table 10.25 summarizes the mos input pull-up states. table 10.25 mos input pull-up states (port e) modes power-on reset hardware standby mode manual reset software standby mode in other operations 7 off off on/off on/off on/off 4 to 6 8-bit bus 16-bit bus off off off legend: off: mos input pull-up is always off. on/off: on when peddr = 0 and pepcr = 1; otherwise off.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 423 of 1220 rej09b0186-0300o 10.15 port f 10.15.1 overview port f is an 8-bit i/o port. port f pins also function as external interrupt input pins ( irq2 and irq3 ), buzz output pin, a/d trigger input pin ( adtrg ), bus control signal input/output pins ( as , rd , hwr , lwr , lcas , wait , breqo , breq , and back ) and the system clock ( ) output pin. figure 10.25 shows the port f pin configuration. pf7 / pf6 / as / lcas pf5 / rd pf4 / hwr pf3 / lwr / adtrg / irq3 pf2 / lcas / wait / breqo pf1 / back / buzz pf0 / breq / irq2 port f port f pins pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 (input) / (output) (i/o) (i/o) (i/o) (i/o) / adtrg (input) / irq3 (input) (i/o) (i/o) / buzz (output) (i/o) / irq2 (input) pin functions in mode 7 pf7 (input) / (output) as (output) / lcas (output) rd (output) hwr (output) pf3 (i/o) / lwr (output) / adtrg (input) / irq3 (input) pf2 (i/o) / lcas (output) / wait (input) / breqo (output) pf1 (i/o) / back (output) / buzz (output) pf0 (i/o) / breq (input) / irq2 (input) pin functions in modes 4 to 6 figure 10.25 port f pin functions
section 10 i/o ports rev. 3.00 jan 11, 2005 page 424 of 1220 rej09b0186-0300o 10.15.2 register configuration table 10.26 shows the port f register configuration. table 10.26 port f registers name abbreviation r/w initial value address * 1 port f data direction register pfddr w h'80/h'00 * 2 h'fe3e port f data register pfdr r/w h'00 h'ff0e port f register portf r undefined h'ffbe notes: 1. lower 16 bits of the address. 2. initial value depends on the mode. (1) port f data direction register (pfddr) bit:76543210 pf7ddr pf6ddr pf5ddr pf4ddr pf3ddr pf2ddr pf1ddr pf0ddr modes 4 to 6 initial value:10000000 r/w:wwwwwwww mode 7 initial value:00000000 r/w:wwwwwwww pfddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port f. pfddr cannot be read; if it is, an undefined value will be read. pfddr is initialized by a power-on reset, and in hardware standby mode, to h'80 in modes 4 to 6, and to h'00 in mode 7. it retains its prior state by a manual reset or in software standby mode. the ope bit in sbycr is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode. see section 24.2.1, standby control register (sbycr), for details. ? modes 4 to 6 pin pf7 functions as the output pin when the corresponding pfddr bit is set to 1, and as an input port when the bit is cleared to 0. the input/output direction specified by pfddr is ignored for pins pf6 to pf3, which are automatically designated as bus control outputs ( as , rd , hwr , and lwr ). pf6 functions as a bus control output ( lcas ) by setting of the bus controller.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 425 of 1220 rej09b0186-0300o pins pf2 to pf0 are designated as bus control input/output pins ( lcas , wait , breqo , back , breq ) by means of bus controller settings. at other times, setting a pfddr bit to 1 makes the corresponding port f pin an output port, while clearing the bit to 0 makes the pin an input port. ? mode 7 setting a pfddr bit to 1 makes the corresponding port f pin pf6 to pf0 an output port, or in the case of pin pf7, the output pin. clearing the bit to 0 makes the pin an input port. (2) port f data register (pfdr) bit:76543210 pf7dr pf6dr pf5dr pf4dr pf3dr pf2dr pf1dr pf0dr initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pfdr is an 8-bit readable/writable register that stores output data for the port f pins (pf7 to pf0). pfdr is initialized to h'00 by a power-on reset, and in hardware standby mode. it retains its prior state by a manual reset or in software standby mode. (3) port f register (portf) bit:76543210 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 initial value : ? * ? * ? * ? * ? * ? * ? * ? * r/w:rrrrrrrr note: * determined by state of pins pf7 to pf0. portf is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port f pins (pf7 to pf0) must always be performed on pfdr. if a port f read is performed while pfddr bits are set to 1, the pfdr values are read. if a port f read is performed while pfddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, portf contents are determined by the pin states, as pfddr and pfdr are initialized. portf retains its prior state by a manual reset or in software standby mode.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 426 of 1220 rej09b0186-0300o 10.15.3 pin functions port f pins also function as external interrupt input pins ( irq2 and irq3 ), buzz output pin, a/d trigger input pin ( adtrg ), bus control signal input/output pins ( as , rd , hwr , lwr , lcas , wait , breqo , breq , and back ) and the system clock ( ) output pin. the pin functions differ between modes 4 to 6, and mode 7. port f pin functions are shown in table 10.27. table 10.27 port f pin functions pin selection method and pin functions pf7/ the pin function is switched as shown below according to bit pf7ddr. pf7ddr 0 1 pin function pf7 input pin output pin pf6/ as / lcas the pin function is switched as shown below according to the combination of the operating mode and bits rmts2 to rmts0, lc ass, breqoe, waite, abw5 to abw2, and pf2ddr. operating mode modes 4 to 6 mode 7 lcass 0 1 * ? pf6ddr ?? 01 pin function as output pin lcas output pin pf6 input pin pf6 output pin note: * restricted to rmts2 to tmts0 = b'001 to b'011, dram space 16-bit access in modes 4 to 6 only pf5/ rd the pin function is switched as shown below according to the operating mode and bit pf5ddr. operating mode modes 4 to 6 mode 7 pf5ddr ? 01 pin function rd output pin pf5 input pin pf5 output pin pf4/ hwr the pin function is switched as shown below according to the operating mode and bit pf4ddr. operating mode modes 4 to 6 mode 7 pf4ddr ? 01 pin function hwr output pin pf4 input pin pf4 output pin
section 10 i/o ports rev. 3.00 jan 11, 2005 page 427 of 1220 rej09b0186-0300o pin selection method and pin functions pf3/ lwr / adtrg / irq3 the pin function is switched as shown below according to the operating mode, the bus mode, a/d converter bits trgs1 and trgs0, and bit pf3ddr. operating mode modes 4 to 6 mode 7 bus mode 16-bit bus mode 8-bit bus mode ? pf3ddr ? 0101 pin function lwr output pin pf3 input pin pf3 output pin pf3 input pin pf3 output pin adtrg input pin * 1 irq3 input pin * 2 notes: 1. adtrg input when trgs0 = trgs1 = 1. 2. when used as an external interrupt input pin, do not use as an i/o pin for another function. pf2/ lcas / wait / breqo the pin function is switched as shown below according to the combination of the operating mode and bits rmts2 to rmts0, lc ass, breqoe, waite, abw5 to abw2, and pf2ddr. operating mode modes 4 to 6 mode 7 lcass 0 * 1 ? breqoe ? 01 ? waite ? 01 ?? pf2ddr ? 01 ?? 01 pin function lcas output pin pf2 input pin pf2 output pin wait input pin breqo output pin pf2 input pin pf2 output pin note: * restricted to rmts2 to tmts0 = b'001 to b'011, dram space 16-bit access in modes 4 to 6 only. pf1/ back / buzz the pin function is switched as shown below according to the combination of the operating mode and bits brle, buzze, and pf1ddr. operating mode modes 4 to 6 mode 7 brle 0 1 ? buzze 0 1 ? 01 pf1ddr 0 1 ?? 01 ? pin function pf1 input pin pf1 output pin buzz output pin back output pin pf1 input pin pf1 output pin buzz output pin
section 10 i/o ports rev. 3.00 jan 11, 2005 page 428 of 1220 rej09b0186-0300o pin selection method and pin functions pf0/ breq / irq2 the pin function is switched as shown below according to the combination of the operating mode, and bits brle and pf0ddr. operating mode modes 4 to 6 mode 7 brle 0 1 ? pf0ddr 0 1 ? 01 pin function pf0 input pin pf0 output pin breq input pin pf0 input pin pf0 output pin irq2 input pin 10.16 port g 10.16.1 overview port g is a 5-bit i/o port and also used as external interrupt input pins ( irq6 , irq7 ) and bus control signal output pins ( cs0 to cs3 , cas , oe ). figure 10.26 shows the configuration of port g pins. pg4 / pg3 / pg2 / pg1 / pg0 / pg4 (input) / cs0 (output) pg3 (input) / cs1 (output) pg2 (input) / cs2 (output) pg1 (input) / cs3 (output) / oe (output) / irq7 (input) pg0 (i/o) / cas (output) / irq6 (input) cs0 cs1 cs2 cs3 / oe / irq7 cas / irq6 port g pin pin functions in modes 4 to 6 port g pg4 (i/o) pg3 (i/o) pg2 (i/o) pg1 (i/o) / irq7 (input) pg0 (i/o) / irq6 (input) pin functions in mode 7 figure 10.26 port g pin functions
section 10 i/o ports rev. 3.00 jan 11, 2005 page 429 of 1220 rej09b0186-0300o 10.16.2 register configuration table 10.28 shows the port g register configuration. table 10.28 port g registers name abbreviation r/w initial value * 2 address * 1 port g data direction register pgddr w h'10/h'00 * 3 h'fe3f port g data register pgdr rw h'00 h'ff0f port g register portg r undefined h'ffbf notes: 1. indicates the low order 16 bits of the address 2. value of bits 4 to 0 3. the initial value varies according to the mode. (1) port g data direction register (pgddr) 7 ? undefined ? bit : modes 4 and 5 initial value : r/w : 6 ? undefined ? 5 ? undefined ? 4 pg4ddr 1 w 3 pg3ddr 0 w 2 pg2ddr 0 w 1 pg1ddr 0 w 0 pg0ddr 0 w undefined ? modes 6 and 7 initial value : r/w : undefined ? undefined ? 0 w 0 w 0 w 0 w 0 w pgddr is an 8-bit write only register and specifies i/o of each pin of port g in bit units. read processing is invalid. bits 7 to 5 are reserved bits. when the contents are read, undefined values are read. in modes 4 and 5, the pgddr are initialized to h'10 (bits 4 to 0) in power-on reset or hardware standby mode, in modes 6 and 7, the bits are initialized to h'00 (bits 4 to 0). in manual reset or software standby mode, pgddr retains the last status. use the ope bit of sbycr to select whether the bus control output pin retains the output state or becomes the high-impedance when the mode is changed to a software standby mode. ? modes 4 to 6 when pgddr is set to 1, pins pg4 to pg1 function as bus control signal output pins ( cs0 to cs3 , oe ). when pgddr is cleared to 0, the pins function as input ports.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 430 of 1220 rej09b0186-0300o when the dram interface is set, pin pg0 functions as the cas output pin. when pgddr is set to 1, the pin functions as an output port. when pgddr is cleared to 0, the pin functions as an input port. see chapter 7 for the dram interface. ? mode 7 pgddr to 1 it becomes an output port, and by clearing it to 0 it becomes an input port. (2) port g data register (pgdr) 7 ? undefined ? bit : initial value : r/w : 6 ? undefined ? 5 ? undefined ? 4 pg4dr 0 r/w 3 pg3dr 0 r/w 2 pg2dr 0 r/w 1 pg1dr 0 r/w 0 pg0dr 0 r/w pgdr is an 8-bit read/write register and stores output data of port g output pins (pg4 to pg0). bits 7 to 5 are reserved bits. when the contents are read, undefined values are read. write processing is invalid. in power-on reset or hardware standby mode, pgdr is initialized to h'00 (bits 4 to 0). in manual reset or software standby mode, pgdr retains the last state. (3) port g register (portg) 7 ? undefined ? bit : initial value : r/w : 6 ? undefined ? 5 ? undefined ? 4 pg4 ? * r 3 pg3 ? * r 2 pg2 ? * r 1 pg1 ? * r 0 pg0 ? * r note: * determined by the state of pg4 to pg0 portg is an 8-bit read only register and reflects the pin state. write processing is invalid. write processing of output data of port g pins (pg4 to pg0) must be performed for pgdr. bits 7 to 5 are reserved bits. when the contents are read, undefined values are read. write processing is invalid. if port g is read when pgddr is set to 1, the value in pgdr is read. if port g is read when pgddr is cleared to 0, the pin state is read.
section 10 i/o ports rev. 3.00 jan 11, 2005 page 431 of 1220 rej09b0186-0300o in power-on reset or hardware standby mode, port g is determined by the pin state because pgddr and pgdr are initialized. in manual reset or software standby mode, the last state is retained. 10.16.3 pin functions port g is used also as external interrupt input pins ( irq6 , irq7 ) and bus control signal output pins ( cs0 to cs3 , cas , oe ). the pin functions are different between modes 4 and 6, and mode 7. table 10.29 shows the port g pin functions. table 10.29 port g pin functions pin selection method and pin functions pg4/ cs0 the pin function is switched as shown below according to the operating mode and bit pg4ddr. operating mode modes 4 to 6 mode 7 pg4ddr0101 pin function pg4 input pin cs0 output pin pg4 input pin pg4 output pin pg3/ cs1 the pin function is switched as shown below according to the operating mode and bit pg3ddr. operating mode modes 4 to 6 mode 7 pg3ddr0101 pin function pg3 input pin cs1 output pin pg3 input pin pg3 output pin pg2/ cs2 the pin function is switched as shown below according to the operating mode and bit pg2ddr. operating mode modes 4 to 6 mode 7 pg2ddr0101 pin function pg2 input pin cs2 output pin pg2 input pin pg2 output pin
section 10 i/o ports rev. 3.00 jan 11, 2005 page 432 of 1220 rej09b0186-0300o pin selection method and pin functions pg1/ cs3 / oe / irq7 the pin function is switched as shown below according to the operating mode and bits oes and pg1ddr in bcrl. operating mode modes 4 to 6 mode 7 pg1ddr 0 1 0 1 oes ? 01 ?? pin function pg1 input pin cs3 output pin oe output pin pg1 input pin pg1 output pin irq7 input pg0/ cas / irq6 the pin function is switched as shown below according to the operating mode and bits rmts2 to rmts0 in bcrh. operating mode modes 4 to 6 mode 7 rmts2 to rmts0 b'000 b'001 to b'011 ? pg0ddr 0 1 ? 01 pin function pg0 input pin pg0 output pin cas output pin pg0 input pin pg0 output pin irq6 input
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 433 of 1220 rej09b0186-0300o section 11 16-bit timer pulse unit (tpu) 11.1 overview the h8s/2643 group has an on-chip 16-bit timer pulse unit (tpu) that comprises six 16-bit timer channels. 11.1.1 features ? maximum 16-pulse input/output ? a total of 16 timer general registers (tgrs) are provided (four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5), each of which can be set independently as an output compare/input capture register ? tgrc and tgrd for channels 0 and 3 can also be used as buffer registers ? selection of 8 counter input clocks for each channel ? the following operations can be set for each channel ? waveform output at compare match: selection of 0, 1, or toggle output ? input capture function: selection of rising edge, falling edge, or both edge detection ? counter clear operation: counter clearing possible by compare match or input capture ? synchronous operation: multiple timer counters (tcnt) can be written to simultaneously ? simultaneous clearing by compare match and input capture possible ? register simultaneous input/output possible by counter synchronous operation ? pwm mode: any pwm output duty can be set ? maximum of 15-phase pwm output possible by combination with synchronous operation ? buffer operation settable for channels 0 and 3 ? input capture register double-buffering possible ? automatic rewriting of output compare register possible ? phase counting mode settable independently for each of channels 1, 2, 4, and 5 ? two-phase encoder pulse up/down-count possible ? cascaded operation ? channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel 4) overflow/underflow ? fast access via internal 16-bit bus ? fast access is possible via a 16-bit bus interface
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 434 of 1220 rej09b0186-0300o ? 26 interrupt sources ? for channels 0 and 3, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently ? for channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently ? automatic transfer of register data ? block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer controller (dtc) or dma controller (dmac) ? programmable pulse generator (ppg) output trigger can be generated ? channel 0 to 3 compare match/input capture signals can be used as ppg output trigger ? a/d converter conversion start trigger can be generated ? channel 0 to 5 compare match a/input capture a signals can be used as a/d converter conversion start trigger ? module stop mode can be set ? as the initial setting, tpu operation is halted. register access is enabled by exiting module stop mode. table 11.1 lists the functions of the tpu.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 435 of 1220 rej09b0186-0300o table 11.1 tpu functions item channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 count clock /1 /4 /16 /64 tclka tclkb tclkc tclkd /1 /4 /16 /64 /256 tclka tclkb /1 /4 /16 /64 /1024 tclka tclkb tclkc /1 /4 /16 /64 /256 /1024 /4096 tclka /1 /4 /16 /64 /1024 tclka tclkc /1 /4 /16 /64 /256 tclka tclkc tclkd general registers tgr0a tgr0b tgr1a tgr1b tgr2a tgr2b tgr3a tgr3b tgr4a tgr4b tgr5a tgr5b general registers/ buffer registers tgr0c tgr0d ?? tgr3c tgr3d ?? i/o pins tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 tioca3 tiocb3 tiocc3 tiocd3 tioca4 tiocb4 tioca5 tiocb5 counter clear function tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture 0 outputoooooo 1 outputoooooo compare match output toggle output oooooo input capture function oooooo synchronous operation oooooo pwm mode oooooo phase counting mode ?oo?oo buffer operation o ? ? o ? ?
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 436 of 1220 rej09b0186-0300o item channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 dmac activation tgr0a compare match or input capture tgr1a compare match or input capture tgr2a compare match or input capture tgr3a compare match or input capture tgr4a compare match or input capture tgr5a compare match or input capture dtc activation tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture a/d converter trigger tgr0a compare match or input capture tgr1a compare match or input capture tgr2a compare match or input capture tgr3a compare match or input capture tgr4a compare match or input capture tgr5a compare match or input capture ppg trigger tgr0a/ tgr0b compare match or input capture tgr1a/ tgr1b compare match or input capture tgr2a/ tgr2b compare match or input capture tgr3a/ tgr3b compare match or input capture ?? interrupt sources 5 sources ? compare match or input capture 0a ? compare match or input capture 0b ? compare match or input capture 0c ? compare match or input capture 0d ? overflow 4 sources ? compare match or input capture 1a ? compare match or input capture 1b ? overflow ? underflow 4 sources ? compare match or input capture 2a ? compare match or input capture 2b ? overflow ? underflow 5 sources ? compare match or input capture 3a ? compare match or input capture 3b ? compare match or input capture 3c ? compare match or input capture 3d ? overflow 4 sources ? compare match or input capture 4a ? compare match or input capture 4b ? overflow ? underflow 4 sources ? compare match or input capture 5a ? compare match or input capture 5b ? overflow ? underflow legend: o : possible ?: not possible
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 437 of 1220 rej09b0186-0300o 11.1.2 block diagram figure 11.1 shows a block diagram of the tpu. channel 3 tmdr tiorl tsr tcr tiorh tier tgra tcnt tgrb tgrc tgrd channel 4 tmdr tsr tcr tior tier tgra tcnt tgrb control logic tmdr tsr tcr tior tier tgra tcnt tgrb control logic for channels 3 to 5 tmdr tsr tcr tior tier tgra tcnt tgrb tgrc channel 1 tmdr tsr tcr tior tier tgra tcnt tgrb channel 0 tmdr tsr tcr tiorh tier control logic for channels 0 to 2 tgra tcnt tgrb tgrd tsyr tstr input/output pins tioca3 tiocb3 tiocc3 tiocd3 tioca4 tiocb4 tioca5 tiocb5 clock input /1 /4 /16 /64 /256 /1024 /4096 tclka tclkb tclkc tclkd input/output pins tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 interrupt request signals channel 3: channel 4: channel 5: interrupt request signals channel 0: channel 1: channel 2: internal data bus a/d converter convertion start signal ppg output trigger signal tiorl module data bus tgi3a tgi3b tgi3c tgi3d tci3v tgi4a tgi4b tci4v tci4u tgi5a tgi5b tci5v tci5u tgi0a tgi0b tgi0c tgi0d tci0v tgi1a tgi1b tci1v tci1u tgi2a tgi2b tci2v tci2u channel 3: channel 4: channel 5: internal clock: external clock: channel 0: channel 1: channel 2: legend: tstr: timer start register tsyr: timer synchro register tcr: timer control register tmdr: timer mode re g ister tior (h, l): timer i/o control registers (h, l) tier: timer interrupt enable register tsr: timer status register tgr ( a, b, c, d ) : timer g eneral re g isters ( a, b, c, d ) channel 2 common channel 5 bus interface figure 11.1 block diagram of tpu
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 438 of 1220 rej09b0186-0300o 11.1.3 pin configuration table 11.2 summarizes the tpu pins. table 11.2 tpu pins channel name symbol i/o function all clock input a tclka input external clock a input pin (channel 1 and 5 phase counting mode a phase input) clock input b tclkb input external clock b input pin (channel 1 and 5 phase counting mode b phase input) clock input c tclkc input external clock c input pin (channel 2 and 4 phase counting mode a phase input) clock input d tclkd input external clock d input pin (channel 2 and 4 phase counting mode b phase input) 0 input capture/out compare match a0 tioca0 i/o tgr0a input capture input/output compare output/pwm output pin input capture/out compare match b0 tiocb0 i/o tgr0b input capture input/output compare output/pwm output pin input capture/out compare match c0 tiocc0 i/o tgr0c input capture input/output compare output/pwm output pin input capture/out compare match d0 tiocd0 i/o tgr0d input capture input/output compare output/pwm output pin 1 input capture/out compare match a1 tioca1 i/o tgr1a input capture input/output compare output/pwm output pin input capture/out compare match b1 tiocb1 i/o tgr1b input capture input/output compare output/pwm output pin 2 input capture/out compare match a2 tioca2 i/o tgr2a input capture input/output compare output/pwm output pin input capture/out compare match b2 tiocb2 i/o tgr2b input capture input/output compare output/pwm output pin
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 439 of 1220 rej09b0186-0300o channel name symbol i/o function 3 input capture/out compare match a3 tioca3 i/o tgr3a input capture input/output compare output/pwm output pin input capture/out compare match b3 tiocb3 i/o tgr3b input capture input/output compare output/pwm output pin input capture/out compare match c3 tiocc3 i/o tgr3c input capture input/output compare output/pwm output pin input capture/out compare match d3 tiocd3 i/o tgr3d input capture input/output compare output/pwm output pin 4 input capture/out compare match a4 tioca4 i/o tgr4a input capture input/output compare output/pwm output pin input capture/out compare match b4 tiocb4 i/o tgr4b input capture input/output compare output/pwm output pin 5 input capture/out compare match a5 tioca5 i/o tgr5a input capture input/output compare output/pwm output pin input capture/out compare match b5 tiocb5 i/o tgr5b input capture input/output compare output/pwm output pin
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 440 of 1220 rej09b0186-0300o 11.1.4 register configuration table 11.3 summarizes the tpu registers. table 11.3 tpu registers channel name abbreviation r/w initial value address * 1 0 timer control register 0 tcr0 r/w h'00 h'ff10 timer mode register 0 tmdr0 r/w h'c0 h'ff11 timer i/o control register 0h tior0h r/w h'00 h'ff12 timer i/o control register 0l tior0l r/w h'00 h'ff13 timer interrupt enable register 0 tier0 r/w h'40 h'ff14 timer status register 0 tsr0 r/(w) * 2 h'c0 h'ff15 timer counter 0 tcnt0 r/w h'0000 h'ff16 timer general register 0a tgr0a r/w h'ffff h'ff18 timer general register 0b tgr0b r/w h'ffff h'ff1a timer general register 0c tgr0c r/w h'ffff h'ff1c timer general register 0d tgr0d r/w h'ffff h'ff1e 1 timer control register 1 tcr1 r/w h'00 h'ff20 timer mode register 1 tmdr1 r/w h'c0 h'ff21 timer i/o control register 1 tior1 r/w h'00 h'ff22 timer interrupt enable register 1 tier1 r/w h'40 h'ff24 timer status register 1 tsr1 r/(w) * 2 h'c0 h'ff25 timer counter 1 tcnt1 r/w h'0000 h'ff26 timer general register 1a tgr1a r/w h'ffff h'ff28 timer general register 1b tgr1b r/w h'ffff h'ff2a 2 timer control register 2 tcr2 r/w h'00 h'ff30 timer mode register 2 tmdr2 r/w h'c0 h'ff31 timer i/o control register 2 tior2 r/w h'00 h'ff32 timer interrupt enable register 2 tier2 r/w h'40 h'ff34 timer status register 2 tsr2 r/(w) * 2 h'c0 h'ff35 timer counter 2 tcnt2 r/w h'0000 h'ff36 timer general register 2a tgr2a r/w h'ffff h'ff38 timer general register 2b tgr2b r/w h'ffff h'ff3a
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 441 of 1220 rej09b0186-0300o channel name abbreviation r/w initial value address * 1 3 timer control register 3 tcr3 r/w h'00 h'fe80 timer mode register 3 tmdr3 r/w h'c0 h'fe81 timer i/o control register 3h tior3h r/w h'00 h'fe82 timer i/o control register 3l tior3l r/w h'00 h'fe83 timer interrupt enable register 3 tier3 r/w h'40 h'fe84 timer status register 3 tsr3 r/(w) * 2 h'c0 h'fe85 timer counter 3 tcnt3 r/w h'0000 h'fe86 timer general register 3a tgr3a r/w h'ffff h'fe88 timer general register 3b tgr3b r/w h'ffff h'fe8a timer general register 3c tgr3c r/w h'ffff h'fe8c timer general register 3d tgr3d r/w h'ffff h'fe8e 4 timer control register 4 tcr4 r/w h'00 h'fe90 timer mode register 4 tmdr4 r/w h'c0 h'fe91 timer i/o control register 4 tior4 r/w h'00 h'fe92 timer interrupt enable register 4 tier4 r/w h'40 h'fe94 timer status register 4 tsr4 r/(w) * 2 h'c0 h'fe95 timer counter 4 tcnt4 r/w h'0000 h'fe96 timer general register 4a tgr4a r/w h'ffff h'fe98 timer general register 4b tgr4b r/w h'ffff h'fe9a 5 timer control register 5 tcr5 r/w h'00 h'fea0 timer mode register 5 tmdr5 r/w h'c0 h'fea1 timer i/o control register 5 tior5 r/w h'00 h'fea2 timer interrupt enable register 5 tier5 r/w h'40 h'fea4 timer status register 5 tsr5 r/(w) * 2 h'c0 h'fea5 timer counter 5 tcnt5 r/w h'0000 h'fea6 timer general register 5a tgr5a r/w h'ffff h'fea8 timer general register 5b tgr5b r/w h'ffff h'feaa all timer start register tstr r/w h'00 h'feb0 timer synchro register tsyr r/w h'00 h'feb1 module stop control register a mstpcra r/w h'3f h'fde8 notes: 1. lower 16 bits of the address. 2. only 0 can be written, for flag clearing.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 442 of 1220 rej09b0186-0300o 11.2 register descriptions 11.2.1 timer control register (tcr) channel 0: tcr0 channel 3: tcr3 bit:76543210 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w channel 1: tcr1 channel 2: tcr2 channel 4: tcr4 channel 5: tcr5 bit:76543210 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value:00000000 r/w : ? r/w r/w r/w r/w r/w r/w r/w the tcr registers are 8-bit registers that control the tcnt channels. the tpu has six tcr registers, one for each of channels 0 to 5. the tcr registers are initialized to h'00 by a reset, and in hardware standby mode. tcr register settings should be made only when tcnt operation is stopped.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 443 of 1220 rej09b0186-0300o bits 7 to 5?counter clear 2 to 0 (cclr2 to cclr0): these bits select the tcnt counter clearing source. bit 7 bit 6 bit 5 channel cclr2 cclr1 cclr0 description 0, 3 0 0 0 tcnt clearing disabled (initial value) 1 tcnt cleared by tgra compare match/input capture 10 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 1 0 0 tcnt clearing disabled 1 tcnt cleared by tgrc compare match/input capture * 2 1 0 tcnt cleared by tgrd compare match/input capture * 2 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 bit 7 bit 6 bit 5 channel reserved * 3 cclr1 cclr0 description 1, 2, 4, 5 0 0 0 tcnt clearing disabled (initial value) 1 tcnt cleared by tgra compare match/input capture 1 0 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 notes: 1. synchronous operation setting is performed by setting the sync bit in tsyr to 1. 2. when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 3. bit 7 is reserved in channels 1, 2, 4, and 5. it is always read as 0 and cannot be modified.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 444 of 1220 rej09b0186-0300o bits 4 and 3?clock edge 1 and 0 (ckeg1 and ckeg0): these bits select the input clock edge. when the input clock is counted using both edges, the input clock period is halved (e.g. /4 both edges = /2 rising edge). if phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. bit 4 bit 3 ckeg1 ckeg0 description 0 0 count at rising edge (initial value) 1 count at falling edge 1 ? count at both edges note: internal clock edge selection is valid when the input clock is /4 or slower. this setting is ignored if the input clock is /1, or when overflow/underflow of another channel is selected. bits 2 to 0?time prescaler 2 to 0 (tpsc2 to tpsc0): these bits select the tcnt counter clock. the clock source can be selected independently for each channel. table 11.4 shows the clock sources that can be set for each channel. table 11.4 tpu clock sources internal clock external clock channel /1 /4 /16 /64 /256 /1024 /4096 tclka tclkb tclkc tclkd overflow/ underflow on another channel 0 ooo o o o o o 1 ooo o o o o o 2 ooo o o o o o 3 ooo o o o o o 4 ooo o o o o o 5 ooo o o o o o legend: o : setting blank: no setting
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 445 of 1220 rej09b0186-0300o bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 0 0 0 0 internal clock: counts on /1 (initial value) 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 external clock: counts on tclkd pin input bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 1 0 0 0 internal clock: counts on /1 (initial value) 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 internal clock: counts on /256 1 counts on tcnt2 overflow/underflow note: this setting is ignored when channel 1 is in phase counting mode. bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 2 0 0 0 internal clock: counts on /1 (initial value) 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 internal clock: counts on /1024 note: this setting is ignored when channel 2 is in phase counting mode.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 446 of 1220 rej09b0186-0300o bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 3 0 0 0 internal clock: counts on /1 (initial value) 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 internal clock: counts on /1024 1 0 internal clock: counts on /256 1 internal clock: counts on /4096 bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 4 0 0 0 internal clock: counts on /1 (initial value) 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkc pin input 1 0 internal clock: counts on /1024 1 counts on tcnt5 overflow/underflow note: this setting is ignored when channel 4 is in phase counting mode. bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 5 0 0 0 internal clock: counts on /1 (initial value) 1 internal clock: counts on /4 1 0 internal clock: counts on /16 1 internal clock: counts on /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkc pin input 1 0 internal clock: counts on /256 1 external clock: counts on tclkd pin input note: this setting is ignored when channel 5 is in phase counting mode.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 447 of 1220 rej09b0186-0300o 11.2.2 timer mode register (tmdr) channel 0: tmdr0 channel 3: tmdr3 bit:76543210 ?? bfb bfa md3 md2 md1 md0 initial value:11000000 r/w : ?? r/w r/w r/w r/w r/w r/w channel 1: tmdr1 channel 2: tmdr2 channel 4: tmdr4 channel 5: tmdr5 bit:76543210 ???? md3 md2 md1 md0 initial value:11000000 r/w : ???? r/w r/w r/w r/w the tmdr registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. the tpu has six tmdr registers, one for each channel. the tmdr registers are initialized to h'c0 by a reset, and in hardware standby mode. tmdr register settings should be made only when tcnt operation is stopped. bits 7 and 6?reserved: these bits are always read as 1 and cannot be modified. bit 5?buffer operation b (bfb): specifies whether tgrb is to operate in the normal way, or tgrb and tgrd are to be used together for buffer operation. when tgrd is used as a buffer register, tgrd input capture/output compare is not generated. in channels 1, 2, 4, and 5, which have no tgrd, bit 5 is reserved. it is always read as 0 and cannot be modified. bit 5 bfb description 0 tgrb operates normally (initial value) 1 tgrb and tgrd used together for buffer operation
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 448 of 1220 rej09b0186-0300o bit 4?buffer operation a (bfa): specifies whether tgra is to operate in the normal way, or tgra and tgrc are to be used together for buffer operation. when tgrc is used as a buffer register, tgrc input capture/output compare is not generated. in channels 1, 2, 4, and 5, which have no tgrc, bit 4 is reserved. it is always read as 0 and cannot be modified. bit 4 bfa description 0 tgra operates normally (initial value) 1 tgra and tgrc used together for buffer operation bits 3 to 0?modes 3 to 0 (md3 to md0): these bits are used to set the timer operating mode. bit 3 bit 2 bit 1 bit 0 md3 * 1 md2 * 2 md1 md0 description 0 0 0 0 normal operation (initial value) 1 reserved 1 0 pwm mode 1 1 pwm mode 2 1 0 0 phase counting mode 1 1 phase counting mode 2 1 0 phase counting mode 3 1 phase counting mode 4 1 *** ? * : don ? t care notes: 1. md3 is a reserved bit. in a write, it should always be written with 0. 2. phase counting mode cannot be set for channels 0 and 3. in this case, 0 should always be written to md2.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 449 of 1220 rej09b0186-0300o 11.2.3 timer i/o control register (tior) channel 0: tior0h channel 1: tior1 channel 2: tior2 channel 3: tior3h channel 4: tior4 channel 5: tior5 bit:76543210 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w channel 0: tior0l channel 3: tior3l bit:76543210 iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w note: when tgrc or tgrd is designated for buffer operation, this setting is invalid and the register operates as a buffer register. the tior registers are 8-bit registers that control the tgr registers. the tpu has eight tior registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. the tior registers are initialized to h'00 by a reset, and in hardware standby mode. care is required since tior is affected by the tmdr setting. the initial output specified by tior is valid when the counter is stopped (the cst bit in tstr is cleared to 0). note also that, in pwm mode 2, the output at the point at which the counter is cleared to 0 is specified.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 450 of 1220 rej09b0186-0300o bits 7 to 4? i/o control b3 to b0 (iob3 to iob0) i/o control d3 to d0 (iod3 to iod0): bits iob3 to iob0 specify the function of tgrb. bits iod3 to iod0 specify the function of tgrd. bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 0 0 0 0 0 output disabled (initial value) 1 1 0 1 tgr0b is output compare register initial output is 0 output 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 1 output toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 * capture input source is tiocb0 pin input capture at both edges 1 ** tgr0b is input capture register capture input source is channel 1/count clock input capture at tcnt1 count-up/count-down * 1 * : don ? t care note: 1. when bits tpsc2 to tpsc0 in tcr1 are set to b'000 and /1 is used as the tcnt1 count clock, this setting is invalid and input capture is not generated.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 451 of 1220 rej09b0186-0300o bit 7 bit 6 bit 5 bit 4 channel iod3 iod2 iod1 iod0 description 0 0 0 0 0 output disabled (initial value) 1 1 0 1 tgr0d is output compare register * 2 initial output is 0 output 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 1 output toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 * capture input source is tiocd0 pin input capture at both edges 1 ** tgr0d is input capture register * 2 capture input source is channel 1/count clock input capture at tcnt1 count-up/count-down * 1 * : don ? t care notes: 1. when bits tpsc2 to tpsc0 in tcr1 are set to b'000 and /1 is used as the tcnt1 count clock, this setting is invalid and input capture is not generated. 2. when the bfb bit in tmdr0 is set to 1 and tgr0d is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 452 of 1220 rej09b0186-0300o bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 1 0 0 0 0 output disabled (initial value) 1 1 0 1 tgr1b is output compare register initial output is 0 output 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 1 output toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 * capture input source is tiocb1 pin input capture at both edges 1 ** tgr1b is input capture register capture input source is tgr0c compare match/ input capture input capture at generation of tgr0c compare match/input capture * : don ? t care bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 2 0 0 0 0 output disabled (initial value) 1 1 0 1 tgr2b is output compare register initial output is 0 output 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 1 output toggle output at compare match 1 * 0 0 input capture at rising edge 1 input capture at falling edge 1 * tgr2b is input capture register capture input source is tiocb2 pin input capture at both edges * : don ? t care
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 453 of 1220 rej09b0186-0300o bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 3 0 0 0 0 output disabled (initial value) 1 1 0 1 tgr3b is output compare register initial output is 0 output 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 1 output toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 * capture input source is tiocb3 pin input capture at both edges 1 ** tgr3b is input capture register capture input source is channel 4/count clock input capture at tcnt4 count-up/count-down * 1 * : don ? t care note: 1. when bits tpsc2 to tpsc0 in tcr4 are set to b'000 and /1 is used as the tcnt4 count clock, this setting is invalid and input capture is not generated.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 454 of 1220 rej09b0186-0300o bit 7 bit 6 bit 5 bit 4 channel iod3 iod2 iod1 iod0 description 3 0 0 0 0 output disabled (initial value) 1 1 0 1 tgr3d is output compare register * 2 initial output is 0 output 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 1 output toggle output at compare match 0 0 1 10 1 * capture input source is tiocd3 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** tgr3d is input capture register * 2 capture input source is channel 4/count clock input capture at tcnt4 count-up/count-down * 1 * : don ? t care notes: 1. when bits tpsc2 to tpsc0 in tcr4 are set to b'000 and /1 is used as the tcnt4 count clock, this setting is invalid and input capture is not generated. 2. when the bfb bit in tmdr3 is set to 1 and tgr3d is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 455 of 1220 rej09b0186-0300o bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 4 0 0 0 0 output disabled (initial value) 1 1 0 1 tgr4b is output compare register initial output is 0 output 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 1 output toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 * capture input source is tiocb4 pin input capture at both edges 1 ** tgr4b is input capture register capture input source is tgr3c compare match/ input capture input capture at generation of tgr3c compare match/ input capture * : don ? t care bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 5 0 0 0 0 output disabled (initial value) 1 1 0 1 tgr5b is output compare register initial output is 0 output 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 1 output toggle output at compare match 1 * 0 0 input capture at rising edge 1 input capture at falling edge 1 * tgr5b is input capture register capture input source is tiocb5 pin input capture at both edges * : don ? t care
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 456 of 1220 rej09b0186-0300o bits 3 to 0? i/o control a3 to a0 (ioa3 to ioa0) i/o control c3 to c0 (ioc3 to ioc0): ioa3 to ioa0 specify the function of tgra. ioc3 to ioc0 specify the function of tgrc. bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 0 0 0 0 0 output disabled (initial value) 1 1 0 1 tgr0a is output compare register initial output is 0 output 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 1 output toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 * capture input source is tioca0 pin input capture at both edges 1 ** tgr0a is input capture register capture input source is channel 1/ count clock input capture at tcnt1 count-up/count-down * : don ? t care
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 457 of 1220 rej09b0186-0300o bit 3 bit 2 bit 1 bit 0 channel ioc3 ioc2 ioc1 ioc0 description 0 0 0 0 0 output disabled (initial value) 1 1 0 1 tgr0c is output compare register * 1 initial output is 0 output 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 1 output toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 * capture input source is tiocc0 pin input capture at both edges 1 ** tgr0c is input capture register * 1 capture input source is channel 1/count clock input capture at tcnt1 count-up/count-down * : don ? t care note: 1. when the bfa bit in tmdr0 is set to 1 and tgr0c is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 458 of 1220 rej09b0186-0300o bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 1 0 0 0 0 output disabled (initial value) 1 1 0 1 tgr1a is output compare register initial output is 0 output 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 1 output toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 * capture input source is tioca1 pin input capture at both edges 1 ** tgr1a is input capture register capture input source is tgr0a compare match/ input capture input capture at generation of channel 0/tgr0a compare match/input capture * : don ? t care bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 2 0 0 0 0 output disabled (initial value) 1 1 0 1 tgr2a is output compare register initial output is 0 output 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 1 output toggle output at compare match 1 * 0 0 input capture at rising edge 1 input capture at falling edge 1 * tgr2a is input capture register capture input source is tioca2 pin input capture at both edges * : don ? t care
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 459 of 1220 rej09b0186-0300o bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 3 0 0 0 0 output disabled (initial value) 1 1 0 1 tgr3a is output compare register initial output is 0 output 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 1 output toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge ** capture input source is tioca3 pin input capture at both edges 1 * tgr3a is input capture register capture input source is channel 4/count clock input capture at tcnt4 count-up/count-down * : don ? t care
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 460 of 1220 rej09b0186-0300o bit 3 bit 2 bit 1 bit 0 channel ioc3 ioc2 ioc1 ioc0 description 3 0 0 0 0 output disabled (initial value) 1 1 0 1 tgr3c is output compare register * 1 initial output is 0 output 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 1 output toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 * capture input source is tiocc3 pin input capture at both edges 1 ** tgr3c is input capture register * 1 capture input source is channel 4/count clock input capture at tcnt4 count-up/count-down * : don ? t care note: 1. when the bfa bit in tmdr3 is set to 1 and tgr3c is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 461 of 1220 rej09b0186-0300o bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 4 0 0 0 0 output disabled (initial value) 1 1 0 1 tgr4a is output compare register initial output is 0 output 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 1 output toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 * capture input source is tioca4 pin input capture at both edges 1 ** tgr4a is input capture register capture input source is tgr3a compare match/ input capture input capture at generation of tgr3a compare match/input capture * : don ? t care bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 5 0 0 0 0 output disabled (initial value) 1 1 0 1 tgr5a is output compare register initial output is 0 output 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 1 output toggle output at compare match 1 * 0 0 input capture at rising edge 1 input capture at falling edge 1 * tgr5a is input capture register capture input source is tioca5 pin input capture at both edges * : don ? t care
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 462 of 1220 rej09b0186-0300o 11.2.4 timer interrupt enable register (tier) channel 0: tier0 channel 3: tier3 bit:76543210 ttge ?? tciev tgied tgiec tgieb tgiea initial value:01000000 r/w : r/w ?? r/w r/w r/w r/w r/w channel 1: tier1 channel 2: tier2 channel 4: tier4 channel 5: tier5 bit:76543210 ttge ? tcieu tciev ?? tgieb tgiea initial value:01000000 r/w : r/w ? r/w r/w ?? r/w r/w the tier registers are 8-bit registers that control enabling or disabling of interrupt requests for each channel. the tpu has six tier registers, one for each channel. the tier registers are initialized to h'40 by a reset, and in hardware standby mode.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 463 of 1220 rej09b0186-0300o bit 7?a/d conversion start request enable (ttge): enables or disables generation of a/d conversion start requests by tgra input capture/compare match. bit 7 ttge description 0 a/d conversion start request generation disabled (initial value) 1 a/d conversion start request generation enabled bit 6?reserved: this bit is always read as 1 and cannot be modified. bit 5?underflow interrupt enable (tcieu): enables or disables interrupt requests (tciu) by the tcfu flag when the tcfu flag in tsr is set to 1 in channels 1, 2, 4, and 5. in channels 0 and 3, bit 5 is reserved. it is always read as 0 and cannot be modified. bit 5 tcieu description 0 interrupt requests (tciu) by tcfu disabled (initial value) 1 interrupt requests (tciu) by tcfu enabled bit 4?overflow interrupt enable (tciev): enables or disables interrupt requests (tciv) by the tcfv flag when the tcfv flag in tsr is set to 1. bit 4 tciev description 0 interrupt requests (tciv) by tcfv disabled (initial value) 1 interrupt requests (tciv) by tcfv enabled bit 3?tgr interrupt enable d (tgied): enables or disables interrupt requests (tgid) by the tgfd bit when the tgfd bit in tsr is set to 1 in channels 0 and 3. in channels 1, 2, 4, and 5, bit 3 is reserved. it is always read as 0 and cannot be modified. bit 3 tgied description 0 interrupt requests (tgid) by tgfd bit disabled (initial value) 1 interrupt requests (tgid) by tgfd bit enabled
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 464 of 1220 rej09b0186-0300o bit 2?tgr interrupt enable c (tgiec): enables or disables interrupt requests (tgic) by the tgfc bit when the tgfc bit in tsr is set to 1 in channels 0 and 3. in channels 1, 2, 4, and 5, bit 2 is reserved. it is always read as 0 and cannot be modified. bit 2 tgiec description 0 interrupt requests (tgic) by tgfc bit disabled (initial value) 1 interrupt requests (tgic) by tgfc bit enabled bit 1?tgr interrupt enable b (tgieb): enables or disables interrupt requests (tgib) by the tgfb bit when the tgfb bit in tsr is set to 1. bit 1 tgieb description 0 interrupt requests (tgib) by tgfb bit disabled (initial value) 1 interrupt requests (tgib) by tgfb bit enabled bit 0?tgr interrupt enable a (tgiea): enables or disables interrupt requests (tgia) by the tgfa bit when the tgfa bit in tsr is set to 1. bit 0 tgiea description 0 interrupt requests (tgia) by tgfa bit disabled (initial value) 1 interrupt requests (tgia) by tgfa bit enabled
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 465 of 1220 rej09b0186-0300o 11.2.5 timer status register (tsr) channel 0: tsr0 channel 3: tsr3 bit:76543210 ??? tcfv tgfd tgfc tgfb tgfa initial value:11000000 r/w : ??? r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * note: * only 0 can be written, for flag clearing. channel 1: tsr1 channel 2: tsr2 channel 4: tsr4 channel 5: tsr5 bit:76543210 tcfd ? tcfu tcfv ?? tgfb tgfa initial value:11000000 r/w : r ? r/(w) * r/(w) * ?? r/(w) * r/(w) * note: * only 0 can be written, for flag clearing. the tsr registers are 8-bit registers that indicate the status of each channel. the tpu has six tsr registers, one for each channel. the tsr registers are initialized to h'c0 by a reset, and in hardware standby mode.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 466 of 1220 rej09b0186-0300o bit 7?count direction flag (tcfd): status flag that shows the direction in which tcnt counts in channels 1, 2, 4, and 5. in channels 0 and 3, bit 7 is reserved. it is always read as 1 and cannot be modified. bit 7 tcfd description 0 tcnt counts down 1 tcnt counts up (initial value) bit 6?reserved: this bit is always read as 1 and cannot be modified. bit 5?underflow flag (tcfu): status flag that indicates that tcnt underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. in channels 0 and 3, bit 5 is reserved. it is always read as 0 and cannot be modified. bit 5 tcfu description 0 [clearing condition] (initial value) ? when 0 is written to tcfu after reading tcfu = 1 1 [setting condition] ? when the tcnt value underflows (changes from h'0000 to h'ffff) bit 4?overflow flag (tcfv): status flag that indicates that tcnt overflow has occurred. bit 4 tcfv description 0 [clearing condition] (initial value) ? when 0 is written to tcfv after reading tcfv = 1 1 [setting condition] ? when the tcnt value overflows (changes from h'ffff to h'0000 )
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 467 of 1220 rej09b0186-0300o bit 3?input capture/output compare flag d (tgfd): status flag that indicates the occurrence of tgrd input capture or compare match in channels 0 and 3. in channels 1, 2, 4, and 5, bit 3 is reserved. it is always read as 0 and cannot be modified. bit 3 tgfd description 0 [clearing conditions] (initial value) ? when dtc is activated by tgid interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfd after reading tgfd = 1 1 [setting conditions] ? when tcnt = tgrd while tgrd is functioning as output compare register ? when tcnt value is transferred to tgrd by input capture signal while tgrd is functioning as input capture register bit 2?input capture/output compare flag c (tgfc): status flag that indicates the occurrence of tgrc input capture or compare match in channels 0 and 3. in channels 1, 2, 4, and 5, bit 2 is reserved. it is always read as 0 and cannot be modified. bit 2 tgfc description 0 [clearing conditions] (initial value) ? when dtc is activated by tgic interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfc after reading tgfc = 1 1 [setting conditions] ? when tcnt = tgrc while tgrc is functioning as output compare register ? when tcnt value is transferred to tgrc by input capture signal while tgrc is functioning as input capture register
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 468 of 1220 rej09b0186-0300o bit 1?input capture/output compare flag b (tgfb): status flag that indicates the occurrence of tgrb input capture or compare match. bit 1 tgfb description 0 [clearing conditions] (initial value) ? when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfb after reading tgfb = 1 1 [setting conditions] ? when tcnt = tgrb while tgrb is functioning as output compare register ? when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register bit 0?input capture/output compare flag a (tgfa): status flag that indicates the occurrence of tgra input capture or compare match. bit 0 tgfa description 0 [clearing conditions] (initial value) ? when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ? when dmac is activated by tgia interrupt while dta bit of dmabcr in dmac is 1 ? when 0 is written to tgfa after reading tgfa = 1 1 [setting conditions] ? when tcnt = tgra while tgra is functioning as output compare register ? when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 469 of 1220 rej09b0186-0300o 11.2.6 timer counter (tcnt) channel 0: tcnt0 (up-counter) channel 1: tcnt1 (up/down-counter * ) channel 2: tcnt2 (up/down-counter * ) channel 3: tcnt3 (up-counter) channel 4: tcnt4 (up/down-counter * ) channel 5: tcnt5 (up/down-counter * ) bit :1514131211109876543210 initial value:0000000000000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w note: * these counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. in other cases they function as up- counters. the tcnt registers are 16-bit counters. the tpu has six tcnt counters, one for each channel. the tcnt counters are initialized to h'0000 by a reset, and in hardware standby mode. the tcnt counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 470 of 1220 rej09b0186-0300o 11.2.7 timer general register (tgr) bit :1514131211109876543210 initial value:1111111111111111 r/w : r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w the tgr registers are 16-bit registers with a dual function as output compare and input capture registers. the tpu has 16 tgr registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. tgrc and tgrd for channels 0 and 3 can also be designated for operation as buffer registers*. the tgr registers are initialized to h'ffff by a reset, and in hardware standby mode. the tgr registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. note: * tgr buffer register combinations are tgra?tgrc and tgrb?tgrd.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 471 of 1220 rej09b0186-0300o 11.2.8 timer start register (tstr) bit:76543210 ?? cst5 cst4 cst3 cst2 cst1 cst0 initial value:00000000 r/w : ?? r/w r/w r/w r/w r/w r/w tstr is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. tstr is initialized to h'00 by a reset, and in hardware standby mode. when setting the operating mode in tmdr or setting the count clock in tcr, first stop the tcnt counter. bits 7 and 6?reserved: should always be written with 0. bits 5 to 0?counter start 5 to 0 (cst5 to cst0): these bits select operation or stoppage for tcnt. bit n cstn description 0 tcntn count operation is stopped (initial value) 1 tcntn performs count operation n = 5 to 0 note: if 0 is written to the cst bit during operation with the tioc pin designated for output, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 472 of 1220 rej09b0186-0300o 11.2.9 timer synchro register (tsyr) bit:76543210 ?? sync5 sync4 sync3 sync2 sync1 sync0 initial value:00000000 r/w : ?? r/w r/w r/w r/w r/w r/w tsyr is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 5 tcnt counters. a channel performs synchronous operation when the corresponding bit in tsyr is set to 1. tsyr is initialized to h'00 by a reset, and in hardware standby mode. bits 7 and 6?reserved: should always be written with 0. bits 5 to 0?timer synchro 5 to 0 (sync5 to sync0): these bits select whether operation is independent of or synchronized with other channels. when synchronous operation is selected, synchronous presetting of multiple channels* 1 , and synchronous clearing through counter clearing on another channel* 2 are possible. bit n syncn description 0 tcntn operates independently (tcnt presetting/clearing is unrelated to other channels) (initial value) 1 tcntn performs synchronous operation tcnt synchronous presetting/synchronous clearing is possible n = 5 to 0 notes: 1. to set synchronous operation, the sync bits for at least two channels must be set to 1. 2. to set synchronous clearing, in addition to the sync bit , the tcnt clearing source must also be set by means of bits cclr2 to cclr0 in tcr.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 473 of 1220 rej09b0186-0300o 11.2.10 module stop control register a (mstpcra) bit:76543210 mstpa7 mstpa6 mstpa5 mstpa4 mstpa3 mstpa2 mstpa1 mstpa0 initial value:00111111 r/w : r/w r/w r/w r/w r/w r/w r/w r/w mstpcra is an 8-bit readable/writable register that performs module stop mode control. when the mstpa5 bit in mstpcra is set to 1, tpu operation stops at the end of the bus cycle and a transition is made to module stop mode. registers cannot be read or written to in module stop mode. for details, see section 24.5, module stop mode. mstpcra is initialized to h'3f by a power-on reset and in hardware standby mode. it is not initialized by a manual reset and in software standby mode. bit 5?module stop (mstpa5): specifies the tpu module stop mode. bit 5 mstpa5 description 0 tpu module stop mode cleared 1 tpu module stop mode set (initial value)
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 474 of 1220 rej09b0186-0300o 11.3 interface to bus master 11.3.1 16-bit registers tcnt and tgr are 16-bit registers. as the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. these registers cannot be read or written to in 8-bit units; 16-bit access must always be used. an example of 16-bit register access operation is shown in figure 11.2. bus interface h internal data bus l bus master module data bu s tcnth tcntl figure 11.2 16-bit register access operation [bus master ? ? ? ? tcnt (16 bits)] 11.3.2 8-bit registers registers other than tcnt and tgr are 8-bit. as the data bus to the cpu is 16 bits wide, these registers can be read and written to in 16-bit units. they can also be read and written to in 8-bit units.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 475 of 1220 rej09b0186-0300o examples of 8-bit register access operation are shown in figures 11.3 to 11.5. bus interface h internal data bus l module data bus tcr bus master figure 11.3 8-bit register access operation [bus master ? ? ? ? tcr (upper 8 bits)] bus interface h internal data bus l module data bus tmdr bus master figure 11.4 8-bit register access operation [bus master ? ? ? ? tmdr (lower 8 bits)] bus interface h internal data bus l module data bus tcr tmdr bus master figure 11.5 8-bit register access operation [bus master ? ? ? ? tcr and tmdr (16 bits)]
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 476 of 1220 rej09b0186-0300o 11.4 operation 11.4.1 overview operation in each mode is outlined below. (1) normal operation each channel has a tcnt and tgr register. tcnt performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. each tgr can be used as an input capture register or output compare register. (2) synchronous operation when synchronous operation is designated for a channel, tcnt for that channel performs synchronous presetting. that is, when tcnt for a channel designated for synchronous operation is rewritten, the tcnt counters for the other channels are also rewritten at the same time. synchronous clearing of the tcnt counters is also possible by setting the timer synchronization bits in tsyr for channels designated for synchronous operation. (3) buffer operation ? when tgr is an output compare register when a compare match occurs, the value in the buffer register for the relevant channel is transferred to tgr. ? when tgr is an input capture register when input capture occurs, the value in tcnt is transfer to tgr and the value previously held in tgr is transferred to the buffer register. (4) cascaded operation the channel 1 counter (tcnt1), channel 2 counter (tcnt2), channel 4 counter (tcnt4), and channel 5 counter (tcnt5) can be connected together to operate as a 32-bit counter. (5) pwm mode in this mode, a pwm waveform is output. the output level can be set by means of tior. a pwm waveform with a duty of between 0% and 100% can be output, according to the setting of each tgr register.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 477 of 1220 rej09b0186-0300o (6) phase counting mode in this mode, tcnt is incremented or decremented by detecting the phases of two clocks input from the external clock input pins in channels 1, 2, 4, and 5. when phase counting mode is set, the corresponding tclk pin functions as the clock pin, and tcnt performs up- or down-counting. this can be used for two-phase encoder pulse input.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 478 of 1220 rej09b0186-0300o 11.4.2 basic functions (1) counter operation when one of bits cst0 to cst5 is set to 1 in tstr, the tcnt counter for the corresponding channel starts counting. tcnt can operate as a free-running counter, periodic counter, and so on. ? example of count operation setting procedure figure 11.6 shows an example of the count operation setting procedure. select counter clock operation selection select counter clearing source periodic counter set period start count operation [1] [2] [4] [3] [5] free-running counter start count operation [5] [1] [2] [3] [4] [5] select output compare register select the counter clock with bits tpsc2 to tpsc0 in tcr. at the same time, select the input clock edge with bits ckeg1 and ckeg0 in tcr. for periodic counter operation, select the tgr to be used as the tcnt clearing source with bits cclr2 to cclr0 in tcr. designate the tgr selected in [2] as an output compare register by means of tior. set the periodic counter cycle in the tgr selected in [2]. set the cst bit in tstr to 1 to start the counter operation. figure 11.6 example of counter operation setting procedure
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 479 of 1220 rej09b0186-0300o ? free-running count operation and periodic count operation immediately after a reset, the tpu?s tcnt counters are all designated as free-running counters. when the relevant bit in tstr is set to 1 the corresponding tcnt counter starts up- count operation as a free-running counter. when tcnt overflows (from h'ffff to h'0000), the tcfv bit in tsr is set to 1. if the value of the corresponding tciev bit in tier is 1 at this point, the tpu requests an interrupt. after overflow, tcnt starts counting up again from h'0000. figure 11.7 illustrates free-running c ounter operation. tcnt value h'ffff h'0000 cst bit tcfv time figure 11.7 free-running counter operation when compare match is selected as the tcnt clearing source, the tcnt counter for the relevant channel performs periodic count operation. the tgr register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits cclr2 to cclr0 in tcr. after the settings have been made, tcnt starts up-count operation as periodic counter when the corresponding bit in tstr is set to 1. when the count value matches the value in tgr, the tgf bit in tsr is set to 1 and tcnt is cleared to h'0000. if the value of the corresponding tgie bit in tier is 1 at this point, the tpu requests an interrupt. after a compare match, tcnt starts counting up again from h'0000.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 480 of 1220 rej09b0186-0300o figure 11.8 illustrates periodic counter operation. tcnt value tgr h'0000 cst bit tgf time counter cleared by tgr compare match flag cleared by software or dtc/dmac activation figure 11.8 periodic counter operation (2) waveform output by compare match the tpu can perform 0, 1, or toggle output from the corresponding output pin using compare match. ? example of setting procedure for waveform output by compare match figure 11.9 shows an example of the setting procedure for waveform output by compare match
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 481 of 1220 rej09b0186-0300o select waveform output mode output selection set output timing start count operation [1] [2] [3] [1] select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of tior. the set initial value is output at the tioc pin until the first compare match occurs. [2] set the timing for compare match generation in tgr. [3] set the cst bit in tstr to 1 to start the count operation. figure 11.9 example of setting procedure for waveform output by compare match ? examples of waveform output operation figure 11.10 shows an example of 0 output/1 output. in this example tcnt has been designated as a free-running counter, and settings have been made so that 1 is output by compare match a, and 0 is output by compare match b. when the set level and the pin level coincide, the pin level does not change. tcnt value h'ffff h'0000 tioca tiocb tim e tgra tgrb no change no change no change no change 1 output 0 output figure 11.10 example of 0 output/1 output operation
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 482 of 1220 rej09b0186-0300o figure 11.11 shows an example of toggle output. in this example tcnt has been designated as a periodic counter (with counter clearing performed by compare match b), and settings have been made so that output is toggled by both compare match a and compare match b. tcnt value h'ffff h'0000 tiocb tioca time tgrb tgra toggle output toggle output counter cleared by tgrb compare match figure 11.11 example of toggle output operation
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 483 of 1220 rej09b0186-0300o (3) input capture function the tcnt value can be transferred to tgr on detection of the tioc pin input edge. rising edge, falling edge, or both edges can be selected as the detected edge. for channels 0, 1, 3, and 4, it is also possible to specify another channel?s counter input clock or compare match signal as the input capture source. note: when another channel?s counter input clock is used as the input capture input for channels 0 and 3, /1 should not be selected as the counter input clock used for input capture input. input capture will not be generated if /1 is selected. ? example of input capture operation setting procedure figure 11.12 shows an example of the input capture operation setting procedure. select input capture input input selection start count [1] [2] [1] designate tgr as an input capture register by means of tior, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] set the cst bit in tstr to 1 to start the count operation. figure 11.12 example of input capture operation setting procedure
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 484 of 1220 rej09b0186-0300o ? example of input capture operation figure 11.13 shows an example of input capture operation. in this example both rising and falling edges have been selected as the tioca pin i nput capture input edge, fa lling edge has been selected as the tiocb pin i nput capture input edge, and counter clearing by tgrb input capture has been designated for tcnt. tcnt value h'0180 h'0000 tioca tgra time h'0010 h'0005 counter cleared by tiocb input (falling edge) h'0160 h'0005 h'0160 h'0010 tgrb h'0180 tiocb figure 11.13 example of input capture operation 11.4.3 synchronous operation in synchronous operation, the values in a number of tcnt counters can be rewritten simultaneously (synchronous presetting). also, a number of tcnt counters can be cleared simultaneously by making the appropriate setting in tcr (synchronous clearing). synchronous operation enables tgr to be incremented with respect to a single time base. channels 0 to 5 can all be designated for synchronous operation.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 485 of 1220 rej09b0186-0300o (1) example of synchronous operation setting procedure figure 11.14 shows an example of the synchronous operation setting procedure. set synchronous operation synchronous operation selection set tcnt synchronous presetting [1] [2] synchronous clearing select counter clearing source [3] start count [5] set synchronous counter clearing [4] start count [5] clearing sourcegeneration channel? no yes [1] [2] [3] [4] [5] set to 1 the sync bits in tsyr corresponding to the channels to be designated for synchronous operation. when the tcnt counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other tcnt counters. use bits cclr2 to cclr0 in tcr to specify tcnt clearing by input capture/output compare, etc. use bits cclr2 to cclr0 in tcr to designate synchronous clearing for the counter clearing source. set to 1 the cst bits in tstr for the relevant channels, to start the count operation. figure 11.14 example of synchronous operation setting procedure
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 486 of 1220 rej09b0186-0300o (2) example of synchronous operation figure 11.15 shows an example of synchronous operation. in this example, synchronous operation and pwm mode 1 have been designated for channels 0 to 2, tgr0b compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. three-phase pwm waveforms are output from pins tioc0a to tioc2a. at this time, synchronous presetting, and synchronous clearing by tgr0b compare match, is performed for channel 0 to 2 tcnt counters, and the data set in tgr0b is used as the pwm cycle. for details of pwm modes, see section 11.4.6, pwm modes. tcnt0 to tcnt2 values h'0000 tioc0a tioc1a time tgr0b synchronous clearing by tgr0b compare match tgr2a tgr1a tgr2b tgr0a tgr1b tioc2a figure 11.15 example of synchronous operation
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 487 of 1220 rej09b0186-0300o 11.4.4 buffer operation buffer operation, provided for channels 0 and 3, enables tgrc and tgrd to be used as buffer registers. buffer operation differs depending on whether tgr has been designated as an input capture register or as a compare match register. table 11.5 shows the register combinations used in buffer operation. table 11.5 register combinations in buffer operation channel timer general register buffer register 0tgr0a tgr0c tgr0b tgr0d 3tgr3a tgr3c tgr3b tgr3d ? when tgr is an output compare register when a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. this operation is illustrated in figure 1 1.16. buffer register timer general register tcnt comparator compare match signal figure 11.16 compare match buffer operation
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 488 of 1220 rej09b0186-0300o ? when tgr is an input capture register when input capture occurs, the value in tcnt is transferred to tgr and the value previously held in the timer general register is transferred to the buffer register. this operation is illustrated in figure 1 1.17. buffer register timer general register tcnt input capture signal figure 11.17 input capture buffer operation (1) example of buffer operation setting procedure figure 11.18 shows an example of the buffer operation setting procedure. select tgr function buffer operation set buffer operation start count [1] [2] [3] [1] designate tgr as an input capture register or output compare register by means of tior. [2] designate tgr for buffer operation with bits bfa and bfb in tmdr. [3] set the cst bit in tstr to 1 to start the count operation. figure 11.18 example of buffer operation setting procedure
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 489 of 1220 rej09b0186-0300o (2) examples of buffer operation ? when tgr is an output compare register figure 11.19 shows an operation example in which pwm mode 1 has been designated for channel 0, and buffer operation has been designated for tgra and tgrc. the settings used in this example are tcnt clearing by compare match b, 1 output at compare match a, and 0 output at compare match b. as buffer operation has been set, when compare match a occurs the output changes and the value in buffer register tgrc is simultaneously transferred to timer general register tgra. this operation is repeated each time compare match a occurs. for details of pwm modes, see section 11.4.6, pwm modes. tcnt value tgr0b h'0000 tgr0c time tgr0a h'0200 h'0520 tioca h'0200 h'0450 h'0520 h'0450 tgr0a h'0450 h'0200 transfer figure 11.19 example of buffer operation (1)
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 490 of 1220 rej09b0186-0300o ? when tgr is an input capture register figure 11.20 shows an operation example in which tgra has been designated as an input capture register, and buffer operation has been designated for tgra and tgrc. counter clearing by tgra input capture has been set for tcnt, and both rising and fa lling edges have been selected as the tioca pin input capture input edge. as buffer operation has been set, when the tcnt value is stored in tgra upon occurrence of input capture a, the value previously stored in tgra is simultaneously transferred to tgrc. tcnt value h'09fb h'0000 tgrc time h'0532 tioca tgra h'0f07 h'0532 h'0f07 h'0532 h'0f07 h'09fb figure 11.20 example of buffer operation (2)
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 491 of 1220 rej09b0186-0300o 11.4.5 cascaded operation in cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. this function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of tcnt2 (tcnt5) as set in bits tpsc2 to tpsc0 in tcr. underflow occurs only when the lower 16-bit tcnt is in phase-counting mode. table 11.6 shows the register combinations used in cascaded operation. note: when phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. table 11.6 cascaded combinations combination upper 16 bits lower 16 bits channels 1 and 2 tcnt1 tcnt2 channels 4 and 5 tcnt4 tcnt5 (1) example of cascaded operation setting procedure figure 11.21 shows an example of the setting procedure for cascaded operation. set cascading cascaded operation start count [1] [2] [1] set bits tpsc2 to tpsc0 in the channel 1 (channel 4) tcr to b'111 to select tcnt2 (tcnt5) overflow/underflow counting. [2] set the cst bit in tstr for the upper and lower channel to 1 to start the count operation. figure 11.21 cascaded operation setting procedure
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 492 of 1220 rej09b0186-0300o (2) examples of cascaded operation figure 11.22 illustrates the operation when counting upon tcnt2 overflow/underflow has been set for tcnt1, tgr1a and tgr2a have been designated as input capture registers, and tioc pin rising edge has been selected. when a rising edge is input to the tioca1 and tioca2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to tgr1a, and the lower 16 bits to tgr2a. tcnt2 clock tcnt2 h'ffff h'0000 h'0001 tioca1, tioca2 tgr1a h'03a2 tgr2a h'0000 tcnt1 clock tcnt1 h'03a1 h'03a2 figure 11.22 example of cascaded operation (1) figure 11.23 illustrates the operation when counting upon tcnt2 overflow/underflow has been set for tcnt1, and phase counting mode has been designated for channel 2. tcnt1 is incremented by tcnt2 overflow and decremented by tcnt2 underflow.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 493 of 1220 rej09b0186-0300o tclkc tcnt2 fffd tcnt1 0001 tclkd fffe ffff 0000 0001 0002 0001 0000 ffff 0000 0000 figure 11.23 example of cascaded operation (2) 11.4.6 pwm modes in pwm mode, pwm waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each tgr. designating tgr compare match as the counter clearing source enables the period to be set in that register. all channels can be designated for pwm mode independently. synchronous operation is also possible. there are two pwm modes, as described below. ? pwm mode 1 pwm output is generated from the tioca and tiocc pins by pairing tgra with tgrb and tgrc with tgrd. the output specified by bits ioa3 to ioa0 and ioc3 to ioc0 in tior is output from the tioca and tiocc pins at compare matches a and c, and the output specified by bits iob3 to iob0 and iod3 to iod0 in tior is output at compare matches b and d. the initial output value is the value set in tgra or tgrc. if the set values of paired tgrs are identical, the output value does not change when a compare match occurs. in pwm mode 1, a maximum 8-phase pwm output is possible. ? pwm mode 2 pwm output is generated using one tgr as the cycle register and the others as duty registers. the output specified in tior is performed by means of compare matches. upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in tior. if the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. in pwm mode 2, a maximum 15-phase pwm output is possible by combined use with synchronous operation. the correspondence between pwm output pins and registers is shown in table 11.7.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 494 of 1220 rej09b0186-0300o table 11.7 pwm output registers and output pins output pins channel registers pwm mode 1 pwm mode 2 0 tgr0a tioca0 tioca0 tgr0b tiocb0 tgr0c tiocc0 tiocc0 tgr0d tiocd0 1 tgr1a tioca1 tioca1 tgr1b tiocb1 2 tgr2a tioca2 tioca2 tgr2b tiocb2 3 tgr3a tioca3 tioca3 tgr3b tiocb3 tgr3c tiocc3 tiocc3 tgr3d tiocd3 4 tgr4a tioca4 tioca4 tgr4b tiocb4 5 tgr5a tioca5 tioca5 tgr5b tiocb5 note: in pwm mode 2, pwm output is not possible for the tgr register in which the period is set.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 495 of 1220 rej09b0186-0300o (1) example of pwm mode setting procedure figure 11.24 shows an example of the pwm mode setting procedure. select counter clock pwm mode select counter clearing source select waveform output level [1] [2] [3] set tgr [4] set pwm mode [5] start count [6] [1] select the counter clock with bits tpsc2 to tpsc0 in tcr. at the same time, select the input clock edge with bits ckeg1 and ckeg0 in tcr. [2] use bits cclr2 to cclr0 in tcr to select the tgr to be used as the tcnt clearing source. [3] use tior to designate the tgr as an output compare register, and select the initial value and output value. [4] set the cycle in the tgr selected in [2], and set the duty in the other the tgr. [5] select the pwm mode with bits md3 to md0 in tmdr. [6] set the cst bit in tstr to 1 to start the count operation. figure 11.24 example of pwm mode setting procedure (2) examples of pwm mode operation figure 11.25 shows an example of pwm mode 1 operation. in this example, tgra compare match is set as the tcnt clearing source, 0 is set for the tgra initial output value and output value, and 1 is set as the tgrb output value. in this case, the value set in tgra is used as the period, and the values set in tgrb registers as the duty.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 496 of 1220 rej09b0186-0300o tcnt value tgra h'0000 tioca time tgrb counter cleared by tgra compare match figure 11.25 example of pwm mode operation (1) figure 11.26 shows an example of pwm mode 2 operation. in this example, synchronous operation is designated for channels 0 and 1, tgr1b compare match is set as the tcnt clearing source, and 0 is set for the initial output value and 1 for the output value of the other tgr registers (tgr0a to tgr0d, tgr1a), to output a 5-phase pwm waveform. in this case, the value set in tgr1b is used as the cycle, and the values set in the other tgrs as the duty.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 497 of 1220 rej09b0186-0300o tcnt value tgr1b h'0000 tioca0 counter cleared by tgr1b compare match tgr1a tgr0d tgr0c tgr0b tgr0a tiocb0 tiocc0 tiocd0 tioca1 time figure 11.26 example of pwm mode operation (2)
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 498 of 1220 rej09b0186-0300o figure 11.27 shows examples of pwm waveform output with 0% duty and 100% duty in pwm mode. tcnt value tgra h'0000 tioca tim e tgrb 0% duty tgrb rewritten tgrb rewritten tgrb rewritten tcnt value tgra h'0000 tioca tim e tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not change when cycle register and duty register compare matches occur simultaneously tcnt value tgra h'0000 tioca tim e tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not change when cycle register and duty register compare matches occur simultaneously 0% duty figure 11.27 example of pwm mode operation (3)
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 499 of 1220 rej09b0186-0300o 11.4.7 phase counting mode in phase counting mode, the phase difference between two external clock inputs is detected and tcnt is incremented/decremented accordingly. this mode can be set for channels 1, 2, 4, and 5. when phase counting mode is set, an external clock is selected as the counter input clock and tcnt operates as an up/down-counter regardless of the setting of bits tpsc2 to tpsc0 and bits ckeg1 and ckeg0 in tcr. however, the functions of bits cclr1 and cclr0 in tcr, and of tior, tier, and tgr are valid, and input capture/compare match and interrupt functions can be used. when overflow occurs while tcnt is counting up, the tcfv flag in tsr is set; when underflow occurs while tcnt is counting down, the tcfu flag is set. the tcfd bit in tsr is the count direction flag. reading the tcfd flag provides an indication of whether tcnt is counting up or down. table 11.8 shows the correspondence between external clock pins and channels. table 11.8 phase counting mode clock input pins external clock pins channels a-phase b-phase when channel 1 or 5 is set to phase counting mode tclka tclkb when channel 2 or 4 is set to phase counting mode tclkc tclkd
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 500 of 1220 rej09b0186-0300o (1) example of phase counting mode setting procedure figure 11.28 shows an example of the phase counting mode setting procedure. select phase counting mode phase counting mode start count [1] [2] [1] select phase counting mode with bits md3 to md0 in tmdr. [2] set the cst bit in tstr to 1 to start the count operation. figure 11.28 example of phase counting mode setting procedure (2) examples of phase counting mode operation in phase counting mode, tcnt counts up or down according to the phase difference between two external clocks. there are four modes, according to the count conditions. ? phase counting mode 1 figure 11.29 shows an example of phase counting mode 1 operation, and table 11.9 summarizes the tcnt up/down-count conditions. tcnt value time down-count up-count tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) figure 11.29 example of phase counting mode 1 operation
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 501 of 1220 rej09b0186-0300o table 11.9 up/down-count conditions in phase counting mode 1 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level up-count low level low level high level high level down-count low level high level low level legend: : rising edge : falling edge ? phase counting mode 2 figure 11.30 shows an example of phase counting mode 2 operation, and table 11.10 summarizes the tcnt up/down-count conditions. tcnt value time down-count up-count tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) figure 11.30 example of phase counting mode 2 operation
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 502 of 1220 rej09b0186-0300o table 11.10 up/down-count conditions in phase counting mode 2 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level don ? t care low level don ? t care low level don ? t care high level up-count high level don ? t care low level don ? t care high level don ? t care low level down-count legend: : rising edge : falling edge ? phase counting mode 3 figure 11.31 shows an example of phase counting mode 3 operation, and table 11.11 summarizes the tcnt up/down-count conditions. tcnt value time up-count tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) down-count figure 11.31 example of phase counting mode 3 operation
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 503 of 1220 rej09b0186-0300o table 11.11 up/down-count conditions in phase counting mode 3 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level don ? t care low level don ? t care low level don ? t care high level up-count high level down-count low level don ? t care high level don ? t care low level don ? t care legend: : rising edge : falling edge ? phase counting mode 4 figure 11.32 shows an example of phase counting mode 4 operation, and table 11.12 summarizes the tcnt up/down-count conditions. time tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) up-count down-count tcnt value figure 11.32 example of phase counting mode 4 operation
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 504 of 1220 rej09b0186-0300o table 11.12 up/down-count conditions in phase counting mode 4 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level up-count low level low level don ? t care high level high level down-count low level high level don ? t care low level legend: : rising edge : falling edge (3) phase counting mode application example figure 11.33 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. channel 1 is set to phase counting mode 1, and the encoder pulse a-phase and b-phase are input to tclka and tclkb. channel 0 operates with tcnt counter clearing by tgr0c compare match; tgr0a and tgr0c are used for the compare match function, and are set with the speed control period and position control period. tgr0b is used for input capture, with tgr0b and tgr0d operating in buffer mode. the channel 1 counter input clock is designated as the tgr0b input capture source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed. tgr1a and tgr1b for channel 1 are designated for input capture, channel 0 tgr0a and tgr0c compare matches are selected as the input capture source, and store the up/down-counter values for the control periods. this procedure enables accurate position/speed detection to be achieved.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 505 of 1220 rej09b0186-0300o tcnt1 tcnt0 channel 1 tgr1a (speed period capture) tgr0a (speed control period) tgr1b (position period capture) tgr0c (position control period) tgr0b (pulse width capture) tgr0d (buffer operation) channel 0 tclka tclkb edge detection circuit + ? + ? figure 11.33 phase counting mode application example
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 506 of 1220 rej09b0186-0300o 11.5 interrupts 11.5.1 interrupt sources and priorities there are three kinds of tpu interrupt source: tgr input capture/compare match, tcnt overflow, and tcnt underflow. each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. when an interrupt request is generated, the corresponding status flag in tsr is set to 1. if the corresponding enable/disable bit in tier is set to 1 at this time, an interrupt is requested. the interrupt request is cleared by clearing the status flag to 0. relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. for details, see section 5, interrupt controller. table 11.13 lists the tpu interrupt sources.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 507 of 1220 rej09b0186-0300o table 11.13 tpu interrupts channel interrupt source description dmac activation dtc activation priority 0 tgi0a tgr0a input capture/compare match possible possible high tgi0b tgr0b input capture/compare match not possible possible tgi0c tgr0c input capture/compare match not possible possible tgi0d tgr0d input capture/compare match not possible possible tci0v tcnt0 overflow not possible not possible 1 tgi1a tgr1a input capture/compare match possible possible tgi1b tgr1b input capture/compare match not possible possible tci1v tcnt1 overflow not possible not possible tci1u tcnt1 underflow not possible not possible 2 tgi2a tgr2a input capture/compare match possible possible tgi2b tgr2b input capture/compare match not possible possible tci2v tcnt2 overflow not possible not possible tci2u tcnt2 underflow not possible not possible 3 tgi3a tgr3a input capture/compare match possible possible tgi3b tgr3b input capture/compare match not possible possible tgi3c tgr3c input capture/compare match not possible possible tgi3d tgr3d input capture/compare match not possible possible tci3v tcnt3 overflow not possible not possible 4 tgi4a tgr4a input capture/compare match possible possible tgi4b tgr4b input capture/compare match not possible possible tci4v tcnt4 overflow not possible not possible tci4u tcnt4 underflow not possible not possible 5 tgi5a tgr5a input capture/compare match possible possible tgi5b tgr5b input capture/compare match not possible possible tci5v tcnt5 overflow not possible not possible tci5u tcnt5 underflow not possible not possible low note: this table shows the initial state immediately after a reset. the relative channel priorities can be changed by the interrupt controller.
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 508 of 1220 rej09b0186-0300o (1) input capture/compare match interrupt an interrupt is requested if the tgie bit in tier is set to 1 when the tgf flag in tsr is set to 1 by the occurrence of a tgr input capture/compare match on a particular channel. the interrupt request is cleared by clearing the tgf flag to 0. the tpu has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. (2) overflow interrupt an interrupt is requested if the tciev bit in tier is set to 1 when the tcfv flag in tsr is set to 1 by the occurrence of tcnt overflow on a channel. the interrupt request is cleared by clearing the tcfv flag to 0. the tpu has six overflow interrupts, one for each channel. (3) underflow interrupt an interrupt is requested if the tcieu bit in tier is set to 1 when the tcfu flag in tsr is set to 1 by the occurrence of tcnt underflow on a channel. the interrupt request is cleared by clearing the tcfu flag to 0. the tpu has four underflow interrupts, one each for channels 1, 2, 4, and 5. 11.5.2 dtc/dmac activation (1) dtc activation the dtc can be activated by the tgr input capture/compare match interrupt for a channel. for details, see section 9, data transfer controller. a total of 16 tpu input capture/compare match interrupts can be used as dtc activation sources, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. (2) dmac activation it is possible to activate the dmac by the tgra input capture/compare match interrupt for each channel. see section 8, dma controller for details. in tpu, it is possible to set the tgra input capture/compare match interrupts for each channel, giving a total of 6, as dmac activation factors. 11.5.3 a/d converter activation the a/d converter can be activated by the tgra input capture/compare match for a channel. if the ttge bit in tier is set to 1 when the tgfa flag in tsr is set to 1 by the occurrence of a tgra input capture/compare match on a particular channel, a request to start a/d conversion is
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 509 of 1220 rej09b0186-0300o sent to the a/d converter. if the tpu conversion start trigger has been selected on the a/d converter side at this time, a/d conversion is started. in the tpu, a total of six tgra input capture/compare match interrupts can be used as a/d converter conversion start sources, one for each channel. 11.6 operation timing 11.6.1 input/output timing (1) tcnt count timing figure 11.34 shows tcnt count t iming in internal clock operati on, and figure 11.35 shows tcnt count timing in external clock operation. tcnt tcnt input clock internal clock n ? 1 n n + 1 n + 2 falling edge rising edge figure 11.34 count timing in internal clock operation tcnt tcnt input clock external clock n ? 1 n n + 1 n + 2 rising edge falling edge falling edge figure 11.35 count timing in external clock operation
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 510 of 1220 rej09b0186-0300o (2) output compare output timing a compare match signal is generated in the final state in which tcnt and tgr match (the point at which the count value matched by tcnt is updated). when a compare match signal is generated, the output value set in tior is output at the output compare output pin. after a match between tcnt and tgr, the compare match signal is not generated until the tcnt input clock is generated. figure 11.36 shows output compare output t iming. tgr tcnt tcnt input clock n n n + 1 compare match signal tioc pin figure 11.36 output compare output timing
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 511 of 1220 rej09b0186-0300o (3) input capture signal timing figure 11.37 shows input capture signal t iming. tcnt input capture input n n + 1 n + 2 n n + 2 tgr input capture signal figure 11.37 input capture input signal timing (4) timing for counter clearing by compare match/input capture figure 11.38 shows the t iming when c ounter clearing by compare match occurrence is specified, and figure 11.39 shows the t iming when c ounter clearing by input capture occurrence is specified. tcnt counter clear signal compare match signal tgr n n h'0000 figure 11.38 counter clear timing (compare match)
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 512 of 1220 rej09b0186-0300o tcnt counter clear signal input capture signal tgr n h'0000 n figure 11.39 counter clear timing (input capture) (5) buffer operation timing figures 11.40 and 11.41 show the t iming in buffer operation. tgra, tgrb compare match signal tcnt tgrc, tgrd nn n n n + 1 figure 11.40 buffer operation timing (compare match)
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 513 of 1220 rej09b0186-0300o tgra, tgrb tcnt input capture signal tgrc, tgrd n n n n + 1 n n n + 1 figure 11.41 buffer operation timing (input capture)
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 514 of 1220 rej09b0186-0300o 11.6.2 interrupt signal timing (1) tgf flag setting timing in case of compare match figure 11.42 shows the t iming for setting of the tgf flag in tsr by compare match occurrence, and tgi interrupt request signal timing. tgr tcnt tcnt input clock n n n + 1 compare match signal tgf flag tgi interrupt figure 11.42 tgi interrupt timing (compare match)
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 515 of 1220 rej09b0186-0300o (2) tgf flag setting timing in case of input capture figure 11.43 shows the t iming for setting of the tgf flag in tsr by i nput capture occurrence, and tgi interrupt request signal timing. tgr tcnt input capture signal n n tgf flag tgi interrupt figure 11.43 tgi interrupt timing (input capture)
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 516 of 1220 rej09b0186-0300o (3) tcfv flag/tcfu flag setting timing figure 11.44 shows the t iming for setting of the tcfv flag in tsr by overflow occurrence, and tciv interrupt request signal timing. figure 11.45 shows the t iming for setting of the tcfu flag in tsr by underflow occurrence, and tciu interrupt request signal timing. overflow signal tcnt (overflow) tcnt input clock h'ffff h'0000 tcfv flag tciv interrupt figure 11.44 tciv interrupt setting timing
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 517 of 1220 rej09b0186-0300o underflow signal tcnt (underflow) tcnt input clock h'0000 h'ffff tcfu flag tciu interrupt figure 11.45 tciu interrupt setting timing
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 518 of 1220 rej09b0186-0300o (4) status flag clearing timing after a status flag is read as 1 by the cpu, it is cleared by writing 0 to it. when the dtc or dmac is activated, the flag is cleared automatically. figure 11.46 shows the t iming for status flag clearing by the cpu, and figure 11.47 shows the t iming for status flag clearing by the dtc or dmac. status flag write signal address tsr address interrupt request signal tsr write cycle t 1 t 2 figure 11.46 timing for status flag clearing by cpu interrupt request signal status flag address source address dtc/dmac read cycle t 1 t 2 destination address t 1 t 2 dtc/dmac write cycle figure 11.47 timing for status flag clearing by dtc or dmac activation
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 519 of 1220 rej09b0186-0300o 11.7 usage notes note that the kinds of operation and contention described below occur during tpu operation. (1) input clock restrictions the input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. the tpu will not operate properly with a narrower pulse width. in phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. figure 11.48 shows the input clock conditions in phase counting mode. overlap phase differ- ence phase differ- ence overlap tclka (tclkc) tclkb (tclkd) pulse width pulse width pulse width pulse width notes: phase difference and overlap pulse width : 1.5 states or more : 2.5 states or more figure 11.48 phase difference, overlap, and pulse width in phase counting mode (2) caution on period setting when counter clearing by compare match is set, tcnt is cleared in the final state in which it matches the tgr value (the point at which the count value matched by tcnt is updated). consequently, the actual counter frequency is given by the following formula: f = (n + 1) where f : counter frequency : operating frequency n: tgr set value
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 520 of 1220 rej09b0186-0300o (3) contention between tcnt write and clear operations if the counter clear signal is generated in the t 2 state of a tcnt write cycle, tcnt clearing takes precedence and the tcnt write is not performed. figure 11.49 shows the t iming in this case. counter clear signal write signal address tcnt address tcnt tcnt write cycle t 1 t 2 n h'0000 figure 11.49 contention between tcnt write and clear operations
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 521 of 1220 rej09b0186-0300o (4) contention between tcnt write and increment operations if incrementing occurs in the t 2 state of a tcnt write cycle, the tcnt write takes precedence and tcnt is not incremented. figure 11.50 shows the t iming in this case. tcnt input clock write signal address tcnt address tcnt tcnt write cycle t 1 t 2 n m tcnt write data figure 11.50 contention between tcnt write and increment operations
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 522 of 1220 rej09b0186-0300o (5) contention between tgr write and compare match if a compare match occurs in the t 2 state of a tgr write cycle, the tgr write takes precedence and the compare match signal is prohibited. a compare match does not occur even if the same value as before is written. figure 11.51 shows the t iming in this case. compare match signal write signal address tgr address tcnt tgr write cycle t 1 t 2 n m tgr write data tgr n n + 1 prohibited figure 11.51 contention between tgr write and compare match
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 523 of 1220 rej09b0186-0300o (6) contention between buffer register write and compare match if a compare match occurs in the t 2 state of a tgr write cycle, the data transferred to tgr by the buffer operation will be the data prior to the write. figure 11.52 shows the t iming in this case. compare match signal write signal address buffer register address buffer register tgr write cycle t 1 t 2 n tgr n m buffer register write data figure 11.52 contention between buffer register write and compare match
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 524 of 1220 rej09b0186-0300o (7) contention between tgr read and input capture if the input capture signal is generated in the t 1 state of a tgr read cycle, the data that is read will be the data after input capture transfer. figure 11.53 shows the t iming in this case. input capture signal read signal address tgr address tgr tgr read cycle t 1 t 2 m internal data bus x m figure 11.53 contention between tgr read and input capture
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 525 of 1220 rej09b0186-0300o (8) contention between tgr write and input capture if the input capture signal is generated in the t 2 state of a tgr write cycle, the input capture operation takes precedence and the write to tgr is not performed. figure 11.54 shows the t iming in this case. input capture signal write signal address tcnt tgr write cycle t 1 t 2 m tgr m tgr address figure 11.54 contention between tgr write and input capture
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 526 of 1220 rej09b0186-0300o (9) contention between buffer register write and input capture if the input capture signal is generated in the t 2 state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. figure 11.55 shows the t iming in this case. input capture signal write signal address tcnt buffer register write cycle t 1 t 2 n tgr n m m buffer re g ister buffer register address figure 11.55 contention between buffer register write and input capture
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 527 of 1220 rej09b0186-0300o (10) contention between overflow/underflow and counter clearing if overflow/underflow and counter clearing occur simultaneously, the tcfv/tcfu flag in tsr is not set and tcnt clearing takes precedence. figure 11.56 shows the operation t iming when a tgr compare match is specified as the clearing source, and h'ffff is set in tgr. counter clear signal tcnt input clock tcnt tgf prohibited tcfv h'ffff h'0000 figure 11.56 contention between overflow and counter clearing
section 11 16-bit timer pulse unit (tpu) rev. 3.00 jan 11, 2005 page 528 of 1220 rej09b0186-0300o (11) contention between tcnt write and overflow/underflow if there is an up-count or down-count in the t 2 state of a tcnt write cycle, and overflow/underflow occurs, the tcnt write takes precedence and the tcfv/tcfu flag in tsr is not set. figure 11.57 shows the operation t iming when there is contention between tcnt write and overflow. write signal address tcnt address tcnt tcnt write cycle t 1 t 2 h'ffff m tcnt write data tcfv prohibited figure 11.57 contention between tcnt write and overflow (12) multiplexing of i/o pins in the h8s/2643 group, the tclka input pin is multiplexed with the tiocc0 i/o pin, the tclkb input pin with the tiocd0 i/o pin, the tclkc input pin with the tiocb1 i/o pin, and the tclkd input pin with the tiocb2 i/o pin. when an external clock is input, compare match output should not be performed from a multiplexed pin. (13) interrupts and module stop mode if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source or the dtc activation source. interrupts should therefore be disabled before entering module stop mode.
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 529 of 1220 rej09b0186-0300o section 12 programmable pulse generator (ppg) 12.1 overview the h8s/2643 group has a built-in programmable pulse generator (ppg) that provides pulse outputs by using the 16-bit timer-pulse unit (tpu) as a time base. the ppg pulse outputs are divided into 4-bit groups (groups 3 to 0) that can operate both simultaneously and independently. 12.1.1 features ppg features are listed below. ? 16-bit output data ? maximum 16-bit data can be output, and output can be enabled on a bit-by-bit basis ? four output groups ? output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit outputs ? selectable output trigger signals ? output trigger signals can be selected for each group from the compare match signals of four tpu channels ? non-overlap mode ? a non-overlap margin can be provided between pulse outputs ? can operate together with the data transfer controller (dtc) and dma controller (dmac) ? the compare match signals selected as output trigger signals can activate the dtc or dmac for sequential output of data without cpu intervention ? settable inverted output ? inverted data can be output for each group ? module stop mode can be set ? as the initial setting, ppg operation is halted. register access is enabled by exiting module stop mode
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 530 of 1220 rej09b0186-0300o 12.1.2 block diagram figure 12.1 shows a block diagram of the ppg. compare match signals po15 po14 po13 po12 po11 po10 po9 po8 po7 po6 po5 po4 po3 po2 po1 po0 legend: ppg output mode register ppg output control register next data enable register h next data enable register l next data register h next data register l output data register h output data register l internal data bus pmr: pcr: nderh: nderl: ndrh: ndrl: podrh: podrl: pulse output pins, group 3 pulse output pins, group 2 pulse output pins, group 1 pulse output pins, group 0 podrh podrl ndrh ndrl control logic nderh pmr nderl pcr figure 12.1 block diagram of ppg
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 531 of 1220 rej09b0186-0300o 12.1.3 pin configuration table 12.1 summarizes the ppg pins. table 12.1 ppg pins name symbol i/o function pulse output 0 po0 output group 0 pulse output pulse output 1 po1 output pulse output 2 po2 output pulse output 3 po3 output pulse output 4 po4 output group 1 pulse output pulse output 5 po5 output pulse output 6 po6 output pulse output 7 po7 output pulse output 8 po8 output group 2 pulse output pulse output 9 po9 output pulse output 10 po10 output pulse output 11 po11 output pulse output 12 po12 output group 3 pulse output pulse output 13 po13 output pulse output 14 po14 output pulse output 15 po15 output
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 532 of 1220 rej09b0186-0300o 12.1.4 registers table 12.2 summarizes the ppg registers. table 12.2 ppg registers name abbreviation r/w initial value address * 1 ppg output control register pcr r/w h'ff h'fe26 ppg output mode register pmr r/w h'f0 h'fe27 next data enable register h nderh r/w h'00 h'fe28 next data enable register l nderl r/w h'00 h'fe29 output data register h podrh r/(w) * 2 h'00 h'fe2a output data register l podrl r/(w) * 2 h'00 h'fe2b next data register h ndrh r/w h'00 h'fe2c * 3 h'fe2e next data register l ndrl r/w h'00 h'fe2d * 3 h'fe2f port 1 data direction register p1ddr w h'00 h'fe30 port 2 data direction register p2ddr w h'00 h'fe31 module stop control register a mstpcra r/w h'3f h'fde8 notes: 1. lower 16 bits of the address. 2. a bit that has been set for pulse output by nder is read-only. 3. when the same output trigger is selected for pulse output groups 2 and 3 by the pcr setting, the ndrh address is h'fe2c. when the output triggers are different, the ndrh address is h'fe2e for group 2 and h'fe2c for group 3. similarly, when the same output trigger is selected for pulse output groups 0 and 1 by the pcr setting, the ndrl address is h'fe2d. when the output triggers are different, the ndrl address is h'fe2f for group 0 and h'fe2d for group 1.
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 533 of 1220 rej09b0186-0300o 12.2 register descriptions 12.2.1 next data enable registers h and l (nderh, nderl) nderh bit:76543210 nder15 nder14 nder13 nder12 nder11 nder10 nder9 nder8 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w nderl bit:76543210 nder7 nder6 nder5 nder4 nder3 nder2 nder1 nder0 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w nderh and nderl are 8-bit readable/writable registers that enable or disable pulse output on a bit-by-bit basis. if a bit is enabled for pulse output by nderh or nderl, the ndr value is automatically transferred to the corresponding podr bit when the tpu compare match event specified by pcr occurs, updating the output value. if pulse output is disabled, the bit value is not transferred from ndr to podr and the output value does not change. nderh and nderl are each initialized to h'00 by a reset and in hardware standby mode. they are not initialized in software standby mode. nderh bits 7 to 0?next data enable 15 to 8 (nder15 to nder8): these bits enable or disable pulse output on a bit-by-bit basis. bits 7 to 0 nder15 to nder8 description 0 pulse outputs po15 to po8 are disabled (ndr15 to ndr8 are not transferred to pod15 to pod8) (initial value) 1 pulse outputs po15 to po8 are enabled (ndr15 to ndr8 are transferred to pod15 to pod8)
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 534 of 1220 rej09b0186-0300o nderl bits 7 to 0?next data enable 7 to 0 (nder7 to nder0): these bits enable or disable pulse output on a bit-by-bit basis. bits 7 to 0 nder7 to nder0 description 0 pulse outputs po7 to po0 are disabled (ndr7 to ndr0 are not transferred to pod7 to pod0) (initial value) 1 pulse outputs po7 to po0 are enabled (ndr7 to ndr0 are transferred to pod7 to pod0) 12.2.2 output data registers h and l (podrh, podrl) podrh bit:76543210 pod15 pod14 pod13 pod12 pod11 pod10 pod9 pod8 initial value:00000000 r/w : r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * podrl bit:76543210 pod7 pod6 pod5 pod4 pod3 pod2 pod1 pod0 initial value:00000000 r/w : r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * note: * a bit that has been set for pulse output by nder is read-only. podrh and podrl are 8-bit readable/writable registers that store output data for use in pulse output.
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 535 of 1220 rej09b0186-0300o 12.2.3 next data registers h and l (ndrh, ndrl) ndrh and ndrl are 8-bit readable/writable registers that store the next data for pulse output. during pulse output, the contents of ndrh and ndrl are transferred to the corresponding bits in podrh and podrl when the tpu compare match event specified by pcr occurs. the ndrh and ndrl addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. for details see section 12.2.4, notes on ndr access. ndrh and ndrl are each initialized to h'00 by a reset and in hardware standby mode. they are not initialized in software standby mode. 12.2.4 notes on ndr access the ndrh and ndrl addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. (1) same trigger for pulse output groups if pulse output groups 2 and 3 are triggered by the same compare match event, the ndrh address is h'fe2c. the upper 4 bits belong to group 3 and the lower 4 bits to group 2. address h'fe2e consists entirely of reserved bits that cannot be modified and are always read as 1. address h'fe2c bit:76543210 ndr15 ndr14 ndr13 ndr12 ndr11 ndr10 ndr9 ndr8 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w address h'fe2e bit:76543210 ???????? initial value:11111111 r/w:???????? if pulse output groups 0 and 1 are triggered by the same compare match event, the ndrl address is h'fe2d. the upper 4 bits belong to group 1 and the lower 4 bits to group 0. address h'fe2f consists entirely of reserved bits that cannot be modified and are always read as 1.
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 536 of 1220 rej09b0186-0300o address h'fe2d bit:76543210 ndr7 ndr6 ndr5 ndr4 ndr3 ndr2 ndr1 ndr0 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w address h'fe2f bit:76543210 ???????? initial value:11111111 r/w:???????? (2) different triggers for pulse output groups if pulse output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits in ndrh (group 3) is h'fe2c and the address of the lower 4 bits (group 2) is h'fe2e. bits 3 to 0 of address h'fe2c and bits 7 to 4 of address h'fe2e are reserved bits that cannot be modified and are always read as 1. address h'fe2c bit:76543210 ndr15 ndr14 ndr13 ndr12 ? ? ? ? initial value:00001111 r/w : r/w r/w r/w r/w ? ? ? ? address h'fe2e bit:76543210 ? ? ? ? ndr11 ndr10 ndr9 ndr8 initial value:11110000 r/w : ? ? ? ? r/w r/w r/w r/w if pulse output groups 0 and 1 are triggered by different compare match event, the address of the upper 4 bits in ndrl (group 1) is h'fe2d and the address of the lower 4 bits (group 0) is h'fe2f. bits 3 to 0 of address h'fe2d and bits 7 to 4 of address h'fe2f are reserved bits that cannot be modified and are always read as 1.
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 537 of 1220 rej09b0186-0300o address h'fe2d bit:76543210 ndr7 ndr6 ndr5 ndr4 ? ? ? ? initial value:00001111 r/w : r/w r/w r/w r/w ? ? ? ? address h'fe2f bit:76543210 ? ? ? ? ndr3 ndr2 ndr1 ndr0 initial value:11110000 r/w : ? ? ? ? r/w r/w r/w r/w 12.2.5 ppg output control register (pcr) bit:76543210 g3cms1 g3cms0 g2cms1 g2cms0 g1cms1 g1cms0 g0cms1 g0cms0 initial value:11111111 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pcr is an 8-bit readable/writable register that selects output trigger signals for ppg outputs on a group-by-group basis. pcr is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 and 6?group 3 compare match select 1 and 0 (g3cms1, g3cms0): these bits select the compare match that triggers pulse output group 3 (pins po15 to po12). bit 7 bit 6 description g3cms1 g3cms0 output trigger for pulse output group 3 0 0 compare match in tpu channel 0 1 compare match in tpu channel 1 1 0 compare match in tpu channel 2 1 compare match in tpu channel 3 (initial value)
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 538 of 1220 rej09b0186-0300o bits 5 and 4?group 2 compare match select 1 and 0 (g2cms1, g2cms0): these bits select the compare match that triggers pulse output group 2 (pins po11 to po8). bit 5 bit 4 description g2cms1 g2cms0 output trigger for pulse output group 2 0 0 compare match in tpu channel 0 1 compare match in tpu channel 1 1 0 compare match in tpu channel 2 1 compare match in tpu channel 3 (initial value) bits 3 and 2?group 1 compare match select 1 and 0 (g1cms1, g1cms0): these bits select the compare match that triggers pulse output group 1 (pins po7 to po4). bit 3 bit 2 description g1cms1 g1cms0 output trigger for pulse output group 1 0 0 compare match in tpu channel 0 1 compare match in tpu channel 1 1 0 compare match in tpu channel 2 1 compare match in tpu channel 3 (initial value) bits 1 and 0?group 0 compare match select 1 and 0 (g0cms1, g0cms0): these bits select the compare match that triggers pulse output group 0 (pins po3 to po0). bit 1 bit 0 description g0cms1 g0cms0 output trigger for pulse output group 0 0 0 compare match in tpu channel 0 1 compare match in tpu channel 1 1 0 compare match in tpu channel 2 1 compare match in tpu channel 3 (initial value)
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 539 of 1220 rej09b0186-0300o 12.2.6 ppg output mode register (pmr) bit:76543210 g3inv g2inv g1inv g0inv g3nov g2nov g1nov g0nov initial value:11110000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w pmr is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping operation for each group. the output trigger period of a non-overlapping operation ppg output waveform is set in tgrb and the non-overlap margin is set in tgra. the output values change at compare match a and b. for details, see section 12.3.4, non-overlapping pulse output. pmr is initialized to h'f0 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7?group 3 inversion (g3inv): selects direct output or inverted output for pulse output group 3 (pins po15 to po12). bit 7 g3inv description 0 inverted output for pulse output group 3 (low-level output at pin for a 1 in podrh) 1 direct output for pulse output group 3 (high-level output at pin for a 1 in podrh) (initial value ) bit 6?group 2 inversion (g2inv): selects direct output or inverted output for pulse output group 2 (pins po11 to po8). bit 6 g2inv description 0 inverted output for pulse output group 2 (low-level output at pin for a 1 in podrh) 1 direct output for pulse output group 2 (high-level output at pin for a 1 in podrh) (initial value )
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 540 of 1220 rej09b0186-0300o bit 5?group 1 inversion (g1inv): selects direct output or inverted output for pulse output group 1 (pins po7 to po4). bit 5 g1inv description 0 inverted output for pulse output group 1 (low-level output at pin for a 1 in podrl) 1 direct output for pulse output group 1 (high-level output at pin for a 1 in podrl) (initial value) bit 4?group 0 inversion (g0inv): selects direct output or inverted output for pulse output group 0 (pins po3 to po0). bit 4 g0inv description 0 inverted output for pulse output group 0 (low-level output at pin for a 1 in podrl) 1 direct output for pulse output group 0 (high-level output at pin for a 1 in podrl) (initial value) bit 3?group 3 non-overlap (g3nov): selects normal or non-overlapping operation for pulse output group 3 (pins po15 to po12). bit 3 g3nov description 0 normal operation in pulse output group 3 (output values updated at compare match a in the selected tpu channel) (initial value) 1 non-overlapping operation in pulse output group 3 (independent 1 and 0 output at compare match a or b in the selected tpu channel) bit 2?group 2 non-overlap (g2nov): selects normal or non-overlapping operation for pulse output group 2 (pins po11 to po8). bit 2 g2nov description 0 normal operation in pulse output group 2 (output values updated at compare match a in the selected tpu channel) (initial value) 1 non-overlapping operation in pulse output group 2 (independent 1 and 0 output at compare match a or b in the selected tpu channel)
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 541 of 1220 rej09b0186-0300o bit 1?group 1 non-overlap (g1nov): selects normal or non-overlapping operation for pulse output group 1 (pins po7 to po4). bit 1 g1nov description 0 normal operation in pulse output group 1 (output values updated at compare match a in the selected tpu channel) (initial value) 1 non-overlapping operation in pulse output group 1 (independent 1 and 0 output at compare match a or b in the selected tpu channel) bit 0?group 0 non-overlap (g0nov): selects normal or non-overlapping operation for pulse output group 0 (pins po3 to po0). bit 0 g0nov description 0 normal operation in pulse output group 0 (output values updated at compare match a in the selected tpu channel) (initial value) 1 non-overlapping operation in pulse output group 0 (independent 1 and 0 output at compare match a or b in the selected tpu channel)
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 542 of 1220 rej09b0186-0300o 12.2.7 port 1 data direction register (p1ddr) bit:76543210 p17ddr p16ddr p15ddr p14ddr p13ddr p12ddr p11ddr p10ddr initial value:00000000 r/w:wwwwwwww p1ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. port 1 is multiplexed with pins po15 to po8. bits corresponding to pins used for ppg output must be set to 1. for further information about p1ddr, see section 10.2, port 1. 12.2.8 port 2 data direction register (p1ddr) bit:76543210 p27ddr p26ddr p25ddr p24ddr p23ddr p22ddr p21ddr p20ddr initial value:00000000 r/w:wwwwwwww p2ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. port 2 is multiplexed with pins po7 to po0. bits corresponding to pins used for ppg output must be set to 1. for further information about p2ddr, see section 10.3, port 2.
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 543 of 1220 rej09b0186-0300o 12.2.9 module stop control register a (mstpcra) bit:76543210 mstpa7 mstpa6 mstpa5 mstpa4 mstpa3 mstpa2 mstpa1 mstpa0 initial value:00111111 r/w : r/w r/w r/w r/w r/w r/w r/w r/w mstpcra is an 8-bit readable/writable register that performs module stop mode control. when the mstpa3 bit in mstpcra is set to 1, ppg operation stops at the end of the bus cycle and a transition is made to module stop mode. registers cannot be read or written to in module stop mode. for details, see section 24.5, module stop mode. mstpcra is initialized to h'3f by a reset and in hardware standby mode. it is not initialized by a manual reset and in software standby mode. bit 3?module stop (mstpa3): specifies the ppg module stop mode. bit 3 mstpa3 description 0 ppg module stop mode cleared 1 ppg module stop mode set (initial value)
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 544 of 1220 rej09b0186-0300o 12.3 operation 12.3.1 overview ppg pulse output is enabled when the corresponding bits in p1ddr and nder are set to 1. in this state the corresponding podr contents are output. when the compare match event specified by pcr occurs, the corresponding ndr bit contents are transferred to podr to update the output values. figure 12.2 illustrates the ppg output operation and table 1 2.3 summarizes the ppg operating conditions. output trigger signal pulse output pin internal data bus normal output/inverted output c podr qd nder q ndr qd ddr q figure 12.2 ppg output operation table 12.3 ppg operating conditions nder ddr pin function 0 0 generic input port 1 generic output port 1 0 generic input port (but the podr bit is a read-only bit, and when compare match occurs, the ndr bit value is transferred to the podr bit) 1 ppg pulse output sequential output of data of up to 16 bits is possible by writing new output data to ndr before the next compare match. for details of non-overlapping operation, see section 12.3.4, non- overlapping pulse output.
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 545 of 1220 rej09b0186-0300o 12.3.2 output timing if pulse output is enabled, ndr contents are transferred to podr and output when the specified compare match event occurs. figure 12.3 shows the t iming of these operations for the case of normal output in groups 2 and 3, triggered by compare match a. tcnt n n + 1 tgra n compare match a signal ndrh mn podrh po8 to po15 n mn figure 12.3 timing of transfer and output of ndr contents (example)
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 546 of 1220 rej09b0186-0300o 12.3.3 normal pulse output (1) sample setup procedure for normal pulse output figure 12.4 shows a sample procedure for setting up normal pulse output. select tgr functions [1] set tgra value set counting operation select interrupt request set initial output data enable pulse output select output trigger set next pulse output data start counter set next pulse output data normal ppg output no yes tpu setup port and ppg setup tpu setup [2] [3] [4] [5] [6] [7] [8] [9] [10] compare match? [1] set tior to make tgra an output compare register (with output disabled). [2] set the ppg output trigger period. [3] select the counter clock source with bits tpsc2 to tpsc0 in tcr. select the counter clear source with bits cclr1 and cclr0. [4] enable the tgia interrupt in tier. the dtc or dmac can also be set up to transfer data to ndr. [5] set the initial output values in podr. [6] set the ddr and nder bits for the pins to be used for pulse output to 1. [7] select the tpu compare match event to be used as the output trigger in pcr. [8] set the next pulse output values in ndr. [9] set the cst bit in tstr to 1 to start the tcnt counter. [10] at each tgia interrupt, set the next output values in ndr. figure 12.4 setup procedure for normal pulse output (example)
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 547 of 1220 rej09b0186-0300o (2) example of normal pulse output (example of five-phase pulse output) figure 12.5 shows an example in which pulse output is used for cyclic five-phase pulse output. tcnt value tcnt tgra h'0000 ndrh 00 80 c0 40 60 20 30 10 18 08 88 podrh po15 po14 po13 po12 po11 time compare match c0 80 c0 80 40 60 20 30 10 18 08 88 80 c0 40 figure 12.5 normal pulse output example (five-phase pulse output) [1] set up the tpu channel to be used as the output trigger channel so that tgra is an output compare register and the counter will be cleared by compare match a. set the trigger period in tgra and set the tgiea bit in tier to 1 to enable the compare match a (tgia) interrupt. [2] write h'f8 in p1ddr and nderh, and set the g3cms1, g3cms0, g2cms1, and g2cms0 bits in pcr to select compare match in the tpu channel set up in the previous step to be the output trigger. write output data h'80 in ndrh. [3] the timer counter in the tpu channel starts. when compare match a occurs, the ndrh contents are transferred to podrh and output. the tgia interrupt handling routine writes the next output data (h'c0) in ndrh. [4] five-phase overlapping pulse output (one or two phases active at a time) can be obtained subsequently by writing h'40, h'60, h'20, h'30. h'10, h'18, h'08, h'88... at successive tgia interrupts. if the dtc or dmac is set for activation by this interrupt, pulse output can be obtained without imposing a load on the cpu.
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 548 of 1220 rej09b0186-0300o 12.3.4 non-overlapping pulse output (1) sample setup procedure for non-overlapping pulse output figure 12.6 shows a sample procedure for setting up non-overlapping pulse output. select tgr functions [1] set tgr values set counting operation select interrupt request set initial output data enable pulse output select output trigger set next pulse output data start counter set next pulse output data compare match? no yes tpu setup ppg setup tpu setup non-overlapping ppg output set non-overlapping groups [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [1] set tior to make tgra and tgrb an output compare registers (with output disabled). [2] set the pulse output trigger period in tgrb and the non-overlap margin in tgra. [3] select the counter clock source with bits tpsc2 to tpsc0 in tcr. select the counter clear source with bits cclr1 and cclr0. [4] enable the tgia interrupt in tier. the dtc or dmac can also be set up to transfer data to ndr. [5] set the initial output values in podr. [6] set the ddr and nder bits for the pins to be used for pulse output to 1. [7] select the tpu compare match event to be used as the pulse output trigger in pcr. [8] in pmr, select the groups that will operate in non-overlap mode. [9] set the next pulse output values in ndr. [10] set the cst bit in tstr to 1 to start the tcnt counter. [11] at each tgia interrupt, set the next output values in ndr. figure 12.6 setup procedure for non-overlapping pulse output (example)
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 549 of 1220 rej09b0186-0300o (2) example of non-overlapping pulse output (example of four-phase complementary non-overlapping output) figure 12.7 shows an example in which pulse output is used for four-phase complementary non- overlapping pulse output. tcnt value tcnt tgrb tgra h'0000 ndrh 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65 podrh po15 po14 po13 po12 po11 po10 po9 po8 time non-overlap margin figure 12.7 non-overlapping pulse output example (four-phase complementary)
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 550 of 1220 rej09b0186-0300o [1] set up the tpu channel to be used as the output trigger channel so that tgra and tgrb are output compare registers. set the trigger period in tgrb and the non-overlap margin in tgra, and set the counter to be cleared by compare match b. set the tgiea bit in tier to 1 to enable the tgia interrupt. [2] write h'ff in p1ddr and nderh, and set the g3cms1, g3cms0, g2cms1, and g2cms0 bits in pcr to select compare match in the tpu channel set up in the previous step to be the output trigger. set the g3nov and g2nov bits in pmr to 1 to select non-overlapping output. write output data h'95 in ndrh. [3] the timer counter in the tpu channel starts. when a compare match with tgrb occurs, outputs change from 1 to 0. when a compare match with tgra occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in tgra). the tgia interrupt handling routine writes the next output data (h'65) in ndrh. [4] four-phase complementary non-overlapping pulse output can be obtained subsequently by writing h'59, h'56, h'95... at successive tgia interrupts. if the dtc or dmac is set for activation by this interrupt, pulse output can be obtained without imposing a load on the cpu.
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 551 of 1220 rej09b0186-0300o 12.3.5 inverted pulse output if the g3inv to g0inv bits in pmr are cleared to 0, values that are the inverse of the podr contents can be output. figure 12.8 shows the outputs when g3inv and g2inv are cleared to 0, in addition to the settings of figure 12.7. tcnt value tcnt tgrb tgra h'0000 ndrh 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65 podrl po15 po14 po13 po12 po11 po10 po9 po8 time figure 12.8 inverted pulse output (example)
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 552 of 1220 rej09b0186-0300o 12.3.6 pulse output triggered by input capture pulse output can be triggered by tpu input capture as well as by compare match. if tgra functions as an input capture register in the tpu channel selected by pcr, pulse output will be triggered by the input capture signal. figure 12.9 shows the t iming of this output. n m n tioc pin input capture signal ndr podr mn po figure 12.9 pulse output triggered by input capture (example)
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 553 of 1220 rej09b0186-0300o 12.4 usage notes (1) operation of pulse output pins pins po0 to po15 are also used for other peripheral functions such as the tpu. when output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. note, however, that data transfer from ndr bits to podr bits takes place, regardless of the usage of the pins. pin functions should be changed only under conditions in which the output trigger event will not occur. (2) note on non-overlapping output during non-overlapping operation, the transfer of ndr bit values to podr bits takes place as follows. ? ndr bits are always transferred to podr bits at compare match a. ? at compare match b, ndr bits are transferred only if their value is 0. bits are not transferred if their value is 1. figure 12.10 illustrates the non-overlapping pulse output operation. compare match a compare match b pulse output pin normal output/inverted output c podr qd nder q ndr qd internal data bus ddr figure 12.10 non-overlapping pulse output
section 12 programmable pulse generator (ppg) rev. 3.00 jan 11, 2005 page 554 of 1220 rej09b0186-0300o therefore, 0 data can be transferred ahead of 1 data by making compare match b occur before compare match a. the ndr contents should not be altered during the interval from compare match b to compare match a (the non-overlap margin). this can be accomplished by having the tgia interrupt handling routine write the next data in ndr, or by having the tgia interrupt activate the dtc or dmac. note, however, that the next data must be written before the next compare match b occurs. figure 12.11 shows the t iming of this operation. 0/1 output 0 output 0/1 output 0 output do not write to ndr here write to ndr here compare match a compare match b ndr podr do not write to ndr here write to ndr here write to ndr write to ndr figure 12.11 non-overlapping operation and ndr write timing
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 555 of 1220 rej09b0186-0300o section 13 8-bit timers (tmr) 13.1 overview the h8s/2643 group includes an 8-bit timer module with four channels (tmr0 to tmr3). each channel has an 8-bit counter (tcnt) and two time constant registers (tcora and tcorb) that are constantly compared with the tcnt value to detect compare match events. the 8-bit timer module can thus be used for a variety of functions, including pulse output with an arbitrary duty cycle. 13.1.1 features the features of the 8-bit timer module are listed below. ? selection of four clock sources ? the counters can be driven by one of three internal clock signals ( /8, /64, or /8192) or an external clock input (enabling use as an external event counter). ? selection of three ways to clear the counters ? the counters can be cleared on compare match a or b, or by an external reset signal. ? timer output control by a combination of two compare match signals ? the timer output signal in each channel is controlled by a combination of two independent compare match signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or pwm output. ? provision for cascading of two channels ? operation as a 16-bit timer is possible, using channel 0 (channel 2) for the upper 8 bits and channel 1 (channel 3) for the lower 8 bits (16-bit count mode). ? channel 1 (channel 3) can be used to count channel 0 (channel 2) compare matches (compare match count mode). ? three independent interrupts ? compare match a and b and overflow interrupts can be requested independently. ? a/d converter conversion start trigger can be generated ? channel 0 compare match a signal can be used as an a/d converter conversion start trigger. ? module stop mode can be set ? as the initial setting, 8-bit timer operation is halted. register access is enabled by exiting module stop mode.
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 556 of 1220 rej09b0186-0300o 13.1.2 block diagram figure 13.1 shows a block diagram of the 8-bit timer module (tmr0, tmr1). external clock source internal clock sources ?/8 ?/64 ?/8192 clock 1 clock 0 compare match a1 compare match a0 clear 1 cmia0 cmib0 ovi0 cmia1 cmib1 ovi1 interrupt si g nals tmo0 tmri01 tmri23 internal bus tcora0 comparator a0 comparator b0 tcorb0 tcsr0 tcr0 tcora1 comparator a1 tcnt1 comparator b1 tcorb1 tcsr1 tcr1 tmci01 tmci23 tcnt0 overflow 1 overflow 0 compare match b1 compare match b0 tmo1 a/d conversion start request signal clock select control logic clear 0 figure 13.1 block diagram of 8-bit timer
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 557 of 1220 rej09b0186-0300o 13.1.3 pin configuration table 13.1 summarizes the input and output pins of the 8-bit timer. table 13.1 pin configuration channel name symbol i/o function 0 timer output pin 0 tmo0 output outputs at compare match timer clock input pin 01 tmci01 input inputs external clock for counter timer reset input pin 01 tmri01 input inputs external reset to counter 1 timer output pin 1 tmo1 output outputs at compare match timer clock input pin 23 tmci23 input inputs external clock for counter timer reset input pin 23 tmri23 input inputs external reset to counter 2 timer output pin 2 tmo2 output outputs at compare match timer clock input pin 23 tmci23 input inputs external clock for counter timer reset input pin 23 tmri23 input inputs external reset to counter 3 timer output pin 3 tmo3 output outputs at compare match timer clock input pin 01 tmci01 input inputs external clock for counter timer reset input pin 01 tmri01 input inputs external reset to counter
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 558 of 1220 rej09b0186-0300o 13.1.4 register configuration table 13.2 summarizes the registers of the 8-bit timer module. table 13.2 8-bit timer registers channel name abbreviation r/w initial value address * 1 0 timer control register 0 tcr0 r/w h'00 h'ff68 timer control/status register 0 tcsr0 r/(w) * 2 h'00 h'ff6a time constant register a0 tcora0 r/w h'ff h'ff6c time constant register b0 tcorb0 r/w h'ff h'ff6e timer counter 0 tcnt0 r/w h'00 h'ff70 1 timer control register 1 tcr1 r/w h'00 h'ff69 timer control/status register 1 tcsr1 r/(w) * 2 h'10 h'ff6b time constant register a1 tcora1 r/w h'ff h'ff6d time constant register b1 tcorb1 r/w h'ff h'ff6f timer counter 1 tcnt1 r/w h'00 h'ff71 2 timer control register 2 tcr2 r/w h'00 h'fdc0 timer control/status register 2 tcsr2 r/(w) * 2 h'00 h'fdc2 time constant register a2 tcora2 r/w h'ff h'fdc4 time constant register b2 tcorb2 r/w h'ff h'fdc6 timer counter 2 tcnt2 r/w h'00 h'fdc8 3 timer control register 3 tcr3 r/w h'00 h'fdc1 timer control/status register 3 tcsr3 r/(w) * 2 h'10 h'fdc3 time constant register a3 tcora3 r/w h'ff h'fdc5 time constant register b3 tcorb3 r/w h'ff h'fdc7 timer counter 3 tcnt3 r/w h'00 h'fdc9 all module stop control register a mstpcra r/w h'3f h'fde8 notes: 1. lower 16 bits of the address 2. only 0 can be written to bits 7 to 5, to clear these flags. each pair of registers for channel 0 (channel 2) and channel 1 (channel 3) is a 16-bit register with the upper 8 bits for channel 0 (channel 2) and the lower 8 bits for channel 1 (channel 3), so they can be accessed together by word transfer instruction.
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 559 of 1220 rej09b0186-0300o 13.2 register descriptions 13.2.1 timer counters 0 to 3 (tcnt0 to tcnt3) 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w tcnt0 (tcnt2) tcnt1 (tcnt3) bit initial value r/w : : : tcnt0 to tcnt3 are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. this clock source is selected by clock select bits cks2 to cks0 of tcr. the cpu can read or write to tcnt0 to tcnt3 at all times. tcnt0 and tcnt1 (tcnt2 and tcnt3) comprise a single 16-bit register, so they can be accessed together by word transfer instruction. tcnt0 and tcnt1 (tcnt2 and tcnt3) can be cleared by an external reset input or by a compare match signal. which signal is to be used for clearing is selected by clock clear bits cclr1 and cclr0 of tcr. when a timer counter overflows from h'ff to h'00, ovf in tcsr is set to 1. tcnt0 and tcnt1 are each initialized to h'00 by a reset and in hardware standby mode. 13.2.2 time constant registers a0 to a3 (tcora0 to tcora3) 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcora0 (tcora2) tcora1 (tcora3) bit initial value r/w : : : tcora0 to tcora3 are 8-bit readable/writable registers. tcora0 and tcora1 (tcora2 and tcora3) comprise a single 16-bit register so they can be accessed together by word transfer instruction. tcora is continually compared with the value in tcnt. when a match is detected, the corresponding cmfa flag of tcsr is set. note, however, that comparison is disabled during the t 2 state of a tcor write cycle.
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 560 of 1220 rej09b0186-0300o the timer output can be freely controlled by these compare match signals and the settings of bits os1 and os0 of tcsr. tcora0 and tcora1 are each initialized to h'ff by a reset and in hardware standby mode. 13.2.3 time constant registers b0 to b3 (tcorb0 to tcorb3) 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcorb0 (tcorb2) tcorb1 (tcorb3) bit initial value r/w : : : tcorb0 to tcorb3 are 8-bit readable/writable registers. tcorb0 and tcorb1 (tcorb2 and tcorb3) comprise a single 16-bit register so they can be accessed together by word transfer instruction. tcorb is continually compared with the value in tcnt. when a match is detected, the corresponding cmfb flag of tcsr is set. note, however, that comparison is disabled during the t 2 state of a tcor write cycle. the timer output can be freely controlled by these compare match signals and the settings of output select bits os3 and os2 of tcsr. tcorb0 and tcorb1 are each initialized to h'ff by a reset and in hardware standby mode. 13.2.4 timer control registers 0 to 3 (tcr0 to tcr3) 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value r/w : : : tcr0 to tcr3 are 8-bit readable/writable registers that select the input clock source and the time at which tcnt is cleared, and enable interrupts. tcr0 and tcr1 are each initialized to h'00 by a reset and in hardware standby mode. for details of this timing, see section 13.3, operation.
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 561 of 1220 rej09b0186-0300o bit 7?compare match interrupt enable b (cmieb): selects whether cmfb interrupt requests (cmib) are enabled or disabled when the cmfb flag of tcsr is set to 1. bit 7 cmieb description 0 cmfb interrupt requests (cmib) are disabled (initial value) 1 cmfb interrupt requests (cmib) are enabled bit 6?compare match interrupt enable a (cmiea): selects whether cmfa interrupt requests (cmia) are enabled or disabled when the cmfa flag of tcsr is set to 1. bit 6 cmiea description 0 cmfa interrupt requests (cmia) are disabled (initial value) 1 cmfa interrupt requests (cmia) are enabled bit 5?timer overflow interrupt enable (ovie): selects whether ovf interrupt requests (ovi) are enabled or disabled when the ovf flag of tcsr is set to 1. bit 5 ovie description 0 ovf interrupt requests (ovi) are disabled (initial value) 1 ovf interrupt requests (ovi) are enabled bits 4 and 3?counter clear 1 and 0 (cclr1, cclr0): these bits select the method by which tcnt is cleared: by compare match a or b, or by an external reset input. bit 4 bit 3 cclr1 cclr0 description 0 0 clear is disabled (initial value) 1 clear by compare match a 1 0 clear by compare match b 1 clear by rising edge of external reset input
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 562 of 1220 rej09b0186-0300o bits 2 to 0?clock select 2 to 0 (cks2 to cks0): these bits select whether the clock input to tcnt is an internal or external clock. three internal clocks can be selected, all divided from the system clock ( ): /8, /64, and /8,192. the fa lling edge of the selected internal clock triggers the count. when use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. some functions differ between channel 0 and channel 1. bit 2 bit 1 bit 0 cks2 cks1 cks0 description 0 0 0 clock input disabled (initial value) 1 internal clock, counted at falling edge of /8 1 0 internal clock, counted at falling edge of /64 1 internal clock, counted at falling edge of /8192 1 0 0 for channel 0: count at tcnt1 overflow signal * for channel 1: count at tcnt0 compare match a * for channel 2: count at tcnt3 overflow signal * for channel 3: count at tcnt2 compare match a * 1 external clock, counted at rising edge 1 0 external clock, counted at falling edge 1 external clock, counted at both rising and falling edges note: * if the count input of channel 0 (channel 2) is the tcnt1 (tcnt3) overflow signal and that of channel 1 (channel 3) is the tcnt0 (tcnt2) compare match signal, no incrementing clock is generated. do not use this setting.
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 563 of 1220 rej09b0186-0300o 13.2.5 timer control/status registers 0 to 3 (tcsr0 to tcsr3) 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 adte 0 r/w 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w only 0 can be written to bits 7 to 5, to clear these flags. bit initial value r/w : : : note: * 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 ? 1 ? 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w bit initial value r/w : : : tcsr0 tcsr1, tcsr3 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 ? 0 r/w 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w bit initial value r/w : : : tcsr2 tcsr0 to tcsr3 are 8-bit registers that display compare match and overflow statuses, and control compare match output. tcsr0 and tcsr2 are initialized to h'00, and tcsr1 and tcsr3 to h'10, by a reset and in hardware standby mode.
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 564 of 1220 rej09b0186-0300o bit 7?compare match flag b (cmfb): status flag indicating whether the values of tcnt and tcorb match. bit 7 cmfb description 0 [clearing conditions] (initial value) ? cleared by reading cmfb when cmfb = 1, then writing 0 to cmfb ? when dtc is activated by cmib interrupt while disel bit of mrb in dtc is 0 1 [setting condition] ? set when tcnt matches tcorb bit 6?compare match flag a (cmfa): status flag indicating whether the values of tcnt and tcora match. bit 6 cmfa description 0 [clearing conditions] (initial value) ? cleared by reading cmfa when cmfa = 1, then writing 0 to cmfa ? when dtc is activated by cmia interrupt while disel bit of mrb in dtc is 0 1 [setting condition] ? set when tcnt matches tcora bit 5?timer overflow flag (ovf): status flag indicating that tcnt has overflowed (changed from h'ff to h'00). bit 5 ovf description 0 [clearing condition] (initial value) ? cleared by reading ovf when ovf = 1, then writing 0 to ovf 1 [setting condition] ? set when tcnt overflows from h'ff to h'00
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 565 of 1220 rej09b0186-0300o bit 4?a/d trigger enable (adte) (tcsr0 only): selects enabling or disabling of a/d converter start requests by compare-match a. tcsr1 to tcsr3 are reserved bits. when tcsr1 and tcsr3 are read, always 1 is read off. write is disenabled. tcsr2 is readable/writable. bit 4 adte description 0 a/d converter start requests by compare match a are disabled (initial value) 1 a/d converter start requests by compare match a are enabled bits 3 to 0?output select 3 to 0 (os3 to os0): these bits specify how the timer output level is to be changed by a compare match of tcor and tcnt. bits os3 and os2 select the effect of compare match b on the output level, bits os1 and os0 select the effect of compare match a on the output level, and both of them can be controlled independently. note, however, that priorities are set such that: toggle output > 1 output > 0 output. if compare matches occur simultaneously, the output changes according to the compare match with the higher priority. timer output is disabled when bits os3 to os0 are all 0. after a reset, the timer output is 0 until the first compare match event occurs. bit 3 bit 2 os3 os2 description 0 0 no change when compare match b occurs (initial value) 1 0 is output when compare match b occurs 1 0 1 is output when compare match b occurs 1 output is inverted when compare match b occurs (toggle output)
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 566 of 1220 rej09b0186-0300o bit 1 bit 0 os1 os0 description 0 0 no change when compare match a occurs (initial value) 1 0 is output when compare match a occurs 1 0 1 is output when compare match a occurs 1 output is inverted when compare match a occurs (toggle output) 13.2.6 module stop control register a (mstpcra) 7 mstpa7 0 r/w bit initial value r/w : : : 6 mstpa6 0 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w 0 mstpa0 1 r/w mstpcra is an 8-bit readable/writable register that performs module stop mode control. when the mstpa4 and mstpa0 bits in mstpcr is set to 1, the 8-bit timer operation stops at the end of the bus cycle and a transition is made to module stop mode. for details, see section 24.5, module stop mode. mstpcra is initialized to h'3f by a power-on reset and in hardware standby mode. it is not initialized by a manual reset and in software standby mode. bit 4?module stop (mstpa4): specifies the tmr0 and tmr1 module stop mode. bit 4 mstpa4 description 0 tmr0, tmr1 module stop mode cleared 1 tmr0, tmr1 module stop mode set (initial value) bit 0?module stop (mstpa0): specifies the tmr2 and tmr3 module stop mode. bit 0 mstpa0 description 0 tmr2, tmr3 module stop mode cleared 1 tmr2, tmr3 module stop mode set (initial value)
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 567 of 1220 rej09b0186-0300o 13.3 operation 13.3.1 tcnt incrementation timing tcnt is incremented by input clock pulses (either internal or external). (1) internal clock three different internal clock signals ( /8, /64, or /8,192) divided from the system clock ( ) can be selected, by setting bits cks2 to cks0 in tcr. figure 13.2 shows the count t iming. internal clock clock input to tcnt tcnt n ? 1 n n + 1 figure 13.2 count timing for internal clock input (2) external clock three incrementation methods can be selected by setting bits cks2 to cks0 in tcr: at the rising edge, the falling edge, and both rising and falling edges. note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. the counter will not increment correctly if the pulse width is less than these values. figure 13.3 shows the t iming of incrementation at both edges of an external clock signal.
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 568 of 1220 rej09b0186-0300o external clock input clock input to tcnt tcnt n ? 1 n n + 1 figure 13.3 count timing for external clock input 13.3.2 compare match timing (1) setting of compare match flags a and b (cmfa, cmfb) the cmfa and cmfb flags in tcsr are set to 1 by a compare match signal generated when the tcor and tcnt values match. the compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. therefore, when tcor and tcnt match, the compare match signal is not generated until the next incrementation clock input. figure 13.4 shows this t iming. tcnt nn + 1 tcor n compare match signal cmf figure 13.4 timing of cmf setting
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 569 of 1220 rej09b0186-0300o (2) timer output timing when compare match a or b occurs, the timer output changes a specified by bits os3 to os0 in tcsr. depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. figure 13.5 shows the t iming when the output is set to toggle at compare match a. compare match a signal timer output pin figure 13.5 timing of timer output (3) timing of compare match clear the timer counter is cleared when compare match a or b occurs, depending on the setting of the cclr1 and cclr0 bits in tcr. figure 13.6 shows the t iming of this operation. n h'00 compare match signal tcnt figure 13.6 timing of compare match clear
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 570 of 1220 rej09b0186-0300o 13.3.3 timing of external reset on tcnt tcnt is cleared at the rising edge of an external reset input, depending on the settings of the cclr1 and cclr0 bits in tcr. the clear pulse width must be at least 1.5 states. figure 13.7 shows the timing of this operation. clear signal external reset input pin tcnt n h'00 n ? 1 figure 13.7 timing of external reset 13.3.4 timing of overflow flag (ovf) setting the ovf in tcsr is set to 1 when the timer count overflows (changes from h'ff to h'00). figure 13.8 shows the t iming of this operation. ovf overflow signal tcnt h'ff h'00 figure 13.8 timing of ovf setting
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 571 of 1220 rej09b0186-0300o 13.3.5 operation with cascaded connection if bits cks2 to cks0 in either tcr0 or tcr1 are set to b'100, the 8-bit timers of the two channels are cascaded. with this configuration, a single 16-bit timer could be used (16-bit timer mode) or compare matches of the 8-bit timer channel 0 could be counted by the timer of channel 1 (compare match counter mode). in this case, the timer operates as below. (1) 16-bit counter mode when bits cks2 to cks0 in tcr0 are set to b'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. ? setting of compare match flags ? the cmf flag in tcsr0 and tcsr2 is set to 1 when a 16-bit compare match event occurs. ? the cmf flag in tcsr1 and tcsr3 is set to 1 when a lower 8-bit compare match event occurs. ? counter clear specification ? if the cclr1 and cclr0 bits in tcr0 (tcr2) have been set for counter clear at compare match, the 16-bit counter (tcnt0 and tcnt1 (tcnt2 and tcnt3) together) is cleared when a 16-bit compare match event occurs. the 16-bit counter (tcnt0 and tcnt1 (tcnt2 and tcnt3) together) is cleared even if counter clear by the tmri01 (tmri23) pin has also been set. ? the settings of the cclr1 and cclr0 bits in tcr1 and tcr3 are ignored. the lower 8 bits cannot be cleared independently. ? pin output ? control of output from the tmo0 (tmo2) pin by bits os3 to os0 in tcsr0 (tcsr2) is in accordance with the 16-bit compare match conditions. ? control of output from the tmo1 (tmo3) pin by bits os3 to os0 in tcsr1 (tcsr3) is in accordance with the lower 8-bit compare match conditions. (2) compare match counter mode when bits cks2 to cks0 in tcr1 (tcr3) are b'100, tcnt1 (tcnt3) counts compare match a?s for channel 0 (channel 2). channels 0 to 3 are controlled independently. conditions such as setting of the cmf flag, generation of interrupts, output from the tmo pin, and counter clear are in accordance with the settings for each channel.
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 572 of 1220 rej09b0186-0300o (3) note on usage if the 16-bit counter mode and compare match counter mode are set simultaneously, the input clock pulses for tcnt0 and tcnt1 (tcnt2 and tcnt3) are not generated and thus the counters will stop operating. software s hould therefore avoid using both these modes. 13.4 interrupts 13.4.1 interrupt sources and dtc activation there are three 8-bit timer interrupt sources: cmia, cmib, and ovi. their relative priorities are shown in table 13.3. each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in tcr, and independent interrupt requests are sent for each to the interrupt controller. it is also possible to activate the dtc by means of cmia and cmib interrupts. table 13.3 8-bit timer interrupt sources channel interrupt source description dtc activation priority 0 cmia0 interrupt by cmfa possible high cmib0 interrupt by cmfb possible ovi0 interrupt by ovf not possible 1 cmia1 interrupt by cmfa possible cmib1 interrupt by cmfb possible ovi1 interrupt by ovf not possible 2 cmia2 interrupt by cmfa possible cmib2 interrupt by cmfb possible ovi2 interrupt by ovf not possible 3 cmia3 interrupt by cmfa possible cmib3 interrupt by cmfb possible ovi3 interrupt by ovf not possible low note: this table shows the initial state immediately after a reset. the relative channel priorities can be changed by the interrupt controller.
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 573 of 1220 rej09b0186-0300o 13.4.2 a/d converter activation the a/d converter can be activated only by channel 0 compare match a. if the adte bit in tcsr0 is set to 1 when the cmfa flag is set to 1 by the occurrence of channel 0 compare match a, a request to start a/d conversion is sent to the a/d converter. if the 8-bit timer conversion start trigger has been selected on the a/d converter side at this time, a/d conversion is started. 13.5 sample application in the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 13.9. the control bits are set as follows. [1] in tcr, bit cclr1 is cleared to 0 and bit cclr0 is set to 1 so that the timer counter is cleared when its value matches the constant in tcora. [2] in tcsr, bits os3 to os0 are set to b'0110, causing the output to change to 1 at a tcora compare match and to 0 at a tcorb compare match. with these settings, the 8-bit timer provides output of pulses at a rate determined by tcora with a pulse width determined by tcorb. no software intervention is required. tcnt h'ff counter clear tcora tcorb h'00 tmo figure 13.9 example of pulse output
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 574 of 1220 rej09b0186-0300o 13.6 usage notes application programmers should note that the following kinds of contention can occur in the 8-bit timer. 13.6.1 contention between tcnt write and clear if a timer counter clock pulse is generated during the t 2 state of a tcnt write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. figure 13.10 shows this operation. address tcnt address internal write signal counter clear signal tcnt n h'00 t 1 t 2 tcnt write cycle by cpu figure 13.10 contention between tcnt write and clear
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 575 of 1220 rej09b0186-0300o 13.6.2 contention between tcnt write and increment if a timer counter clock pulse is generated during the t 2 state of a tcnt write cycle, the write takes priority and the counter is not incremented. figure 13.11 shows this operation. address tcnt address internal write signal tcnt input clock tcnt nm t 1 t 2 tcnt write cycle by cpu counter write data figure 13.11 contention between tcnt write and increment
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 576 of 1220 rej09b0186-0300o 13.6.3 contention between tcor write and compare match during the t 2 state of a tcor write cycle, the tcor write has priority and the compare match signal is prohibited even if a compare match event occurs. figure 13.12 shows this operation. address tcor address internal write signal tcnt tcor nm t 1 t 2 tcor write cycle by cpu tcor write data n n + 1 compare match signal prohibited figure 13.12 contention between tcor write and compare match
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 577 of 1220 rej09b0186-0300o 13.6.4 contention between compare matches a and b if compare match events a and b occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match a and compare match b, as shown in table 13.4. table 13.4 timer output priorities output setting priority toggle output high 1 output 0 output no change low 13.6.5 switching of internal clocks and tcnt operation tcnt may increment erroneously when the internal clock is switched over. table 13.5 shows the relationship between the timing at which the internal clock is switched (by writing to the cks1 and cks0 bits) and the tcnt operation. when the tcnt clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. if clock switching causes a change from high to low level, as shown in case 3 in table 13.5, a tcnt clock pulse is generated on the assumption that the switchover is a fa lling edge. this increments tcnt. the erroneous incrementation can also happen when switching between internal and external clocks.
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 578 of 1220 rej09b0186-0300o table 13.5 switching of internal clock and tcnt operation no. timing of switchover by means of cks1 and cks0 bits tcnt clock operation 1 switching from low to low * 1 clock before switchover clock after switchover tcnt clock tcnt cks bit write nn + 1 2 switching from low to high * 2 clock before switchover clock after switchover tcnt clock tcnt cks bit write n n + 1 n + 2 3 switching from high to low * 3 clock before switchover clock after switchover tcnt clock tcnt cks bit write n n + 1 n + 2 * 4
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 579 of 1220 rej09b0186-0300o no. timing of switchover by means of cks1 and cks0 bits tcnt clock operation 4 switching from high to high clock before switchover clock after switchover tcnt clock tcnt cks bit write n n + 1 n + 2 notes: 1. includes switching from low to stop, and from stop to low. 2. includes switching from stop to high. 3. includes switching from high to stop. 4. generated on the assumption that the switchover is a falling edge; tcnt is incremented. 13.6.6 interrupts and module stop mode if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source or dmac and dtc activation source. interrupts should therefore be disabled before entering module stop mode.
section 13 8-bit timers (tmr) rev. 3.00 jan 11, 2005 page 580 of 1220 rej09b0186-0300o
section 14 14-bit pwm d/a rev. 3.00 jan 11, 2005 page 581 of 1220 rej09b0186-0300o section 14 14-bit pwm d/a 14.1 overview the h8s/2643 group has an on-chip 14-bit pulse-width modulator (pwm) with four output channels. each channel can be connected to an external low-pass filter to operate as a 14-bit d/a converter. both channels share the same counter (dacnt) and control register (dacr). 14.1.1 features the features of the 14-bit pwm d/a are listed below. ? the pulse is subdivided into multiple base cycles to reduce ripple. ? two resolution settings and two base cycle settings are available the resolution can be set equal to one or two system clock cycles. the base cycle can be set equal to t 64 or t 256, where t is the resolution. ? four operating rates the two resolution settings and two base cycle settings combine to give a selection of four operating rates.
section 14 14-bit pwm d/a rev. 3.00 jan 11, 2005 page 582 of 1220 rej09b0186-0300o 14.1.2 block diagram figure 14.1 shows a block diagram of the pwm d/a module. internal clock /2 pwm0 pwm1 dadra dadrb dacnt dacr legend: dacr: pwm d/a control register ( 6 bits) dadra: pwm d/a data register a (15 bits) dadrb: pwm d/a data register b (15 bits) dacnt: pwm d/a counter (14 bits) control logic clock selection clock internal data bus basic cycle compare-match a fine-adjustment pulse addition a basic cycle compare-match b fine-adjustment pulse addition b basic cycle overflow comparator a comparator b bus interface module data bus figure 14.1 pwm d/a block diagram
section 14 14-bit pwm d/a rev. 3.00 jan 11, 2005 page 583 of 1220 rej09b0186-0300o 14.1.3 pin configuration table 14.1 lists the pins used by the pwm d/a module. table 14.1 input and output pins name abbr. i/o function pwm output pin 0 pwm0 output pwm output, channel 0a pwm output pin 1 pwm1 output pwm output, channel 0b pwm output pin 2 pwm2 output pwm output, channel 1a pwm output pin 3 pwm3 output pwm output, channel 1b 14.1.4 register configuration table 14.2 lists the registers of the pwm d/a module. table 14.2 register configuration channel name abbreviation r/w initial value address * 1 0 pwm d/a control register 0 dacr0 r/w h'30 h'fdb8 * 2 pwm d/a data register ah0 dadrah0 r/w h'ff h'fdb8 * 2 pwm d/a data register al0 dadral0 r/w h'ff h'fdb9 * 2 pwm d/a data register bh0 dadrbh0 r/w h'ff h'fdba * 2 pwm d/a data register bl0 dadrbl0 r/w h'ff h'fdbb * 2 pwm d/a counter h0 dacnth0 r/w h'00 h'fdba * 2 pwm d/a counter l0 dacntl0 r/w h'03 h'fdbb * 2 1 pwm d/a control register 1 dacr1 r/w h'30 h'fdbc * 2 pwm d/a data register ah1 dadrah1 r/w h'ff h'fdbc * 2 pwm d/a data register al1 dadral1 r/w h'ff h'fdbd * 2 pwm d/a data register bh1 dadrbh1 r/w h'ff h'fdbe * 2 pwm d/a data register bl1 dadrbl1 r/w h'ff h'fdbf * 2 pwm d/a counter h1 dacnth1 r/w h'00 h'fdbe * 2 pwm d/a counter l1 dacntl1 r/w h'03 h'fdbf * 2 all module stop control register b mstpcrb r/w h'ff h'fde9 notes: 1. lower 16 bits of the address. 2. the same addresses are shared by dadra and dacr, and by dadrb and dacnt. switching is performed by the regs bit in dacnt or dadrb.
section 14 14-bit pwm d/a rev. 3.00 jan 11, 2005 page 584 of 1220 rej09b0186-0300o 14.2 register descriptions 14.2.1 pwm d/a counter (dacnt) 15 7 0 r/w 14 6 0 r/w 13 5 0 r/w 12 4 0 r/w 11 3 0 r/w 8 0 0 r/w 10 2 0 r/w 9 1 0 r/w bit (cpu) : bit (counter) initial value : r/w : 7 8 0 r/w 6 9 0 r/w 5 10 0 r/w 4 11 0 r/w 3 12 0 r/w 0 ? regs 1 r/w 2 13 0 r/w 1 ? 1 ? dacnth dacntl dacnt is a 14-bit readable/writable up-counter that increments on an input clock pulse. the input clock is selected by the clock select bit (cks) in dacr. the cpu can read and write the dacnt value, but since dacnt is a 16-bit register, data transfers between it and the cpu are performed using a temporary register (temp). see section 14.3, bus master interface, for details. dacnt functions as the time base for both pwm d/a channels. when a channel operates with 14-bit precision, it uses all dacnt bits. when a channel operates with 12-bit precision, it uses the lower 12 (counter) bits and ignores the upper two (counter) bits. dacnt is initialized to h'0003 by a reset, in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode, and by the pwme bit. bit 1 of dacntl (cpu) is not used, and is always read as 1. dacntl bit 0?register select (regs): dadra and dacr, and dadrb and dacnt, are located at the same addresses. the regs bit specifies which registers can be accessed. the regs bit can be accessed regardless of whether dadrb or dacnt is selected. bit 0 regs description 0 dadra and dadrb can be accessed 1 dacr and dacnt can be accessed (initial value)
section 14 14-bit pwm d/a rev. 3.00 jan 11, 2005 page 585 of 1220 rej09b0186-0300o 14.2.2 pwm d/a data registers a and b (dadra and dadrb) 15 13 da13 1 r/w 14 12 da12 1 r/w 13 11 da11 1 r/w 12 10 da10 1 r/w 11 9 da9 1 r/w 8 6 da6 1 r/w 10 8 da8 1 r/w 9 7 da7 1 r/w bit (cpu) bit (data) dadra initial value : r/w : 7 5 da5 1 r/w 6 4 da4 1 r/w 5 3 da3 1 r/w 4 2 da2 1 r/w 3 1 da1 1 r/w 0 ? ? 1 ? 2 0 da0 1 r/w 1 ? cfs 1 r/w dadrh dadrl da13 1 r/w da12 1 r/w da11 1 r/w da10 1 r/w da9 1 r/w da6 1 r/w da8 1 r/w da7 1 r/w dadrb initial value : r/w : da5 1 r/w da4 1 r/w da3 1 r/w da2 1 r/w da1 1 r/w regs 1 r/w da0 1 r/w cfs 1 r/w there are two 16-bit readable/writable pwm d/a data registers: dadra and dadrb. dadra corresponds to pwm d/a channel a, and dadrb to pwm d/a channel b. the cpu can read and write the pwm d/a data register values, but since dadra and dadrb are 16-bit registers, data transfers between them and the cpu are performed using a temporary register (temp). see section 14.3, bus master interface, for details. the least significant (cpu) bit of dadra is not used and is always read as 1. dadr is initialized to h'ffff by a reset, and in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode. bits 15 to 3?pwm d/a data 13 to 0 (da13 to da0): the digital value to be converted to an analog value is set in the upper 14 bits of the pwm d/a data register. in each base cycle, the dacnt value is continually compared with these upper 14 bits to determine the duty cycle of the output waveform, and to decide whether to output a fine- adjustment pulse equal in width to the resolution. to enable this operation, the data register must be set within a range that depends on the carrier frequency select bit (cfs). if the dadr value is outside this range, the pwm output is held constant. a channel can be operated with 12-bit precision by keeping the two lowest data bits (da0 and da1) cleared to 0 and writing the data to be converted in the upper 12 bits. the two lowest data bits correspond to the two highest counter (dacnt) bits.
section 14 14-bit pwm d/a rev. 3.00 jan 11, 2005 page 586 of 1220 rej09b0186-0300o bit 1?carrier frequency select (cfs) bit 1 cfs description 0 base cycle = resolution (t) 64 dadr range = h'0401 to h'fffd 1 base cycle = resolution (t) 256 dadr range = h'0103 to h'ffff (initial value) bit 0?reserved: this bit cannot be modified and is always read as 1. dadrb bit 0?register select (regs): dadra and dacr, and dadrb and dacnt, are located at the same addresses. the regs bit specifies which registers can be accessed. the regs bit can be accessed regardless of whether dadrb or dacnt is selected. bit 0 regs description 0 dadra and dadrb can be accessed 1 dacr and dacnt can be accessed (initial value) 14.2.3 pwm d/a control register (dacr) 7 test 0 r/w 6 pwme 0 r/w 5 ? 1 ? 4 ? 1 ? 3 oeb 0 r/w 0 cks 0 r/w 2 oea 0 r/w 1 os 0 r/w bit : initial value : r/w : dacr is an 8-bit readable/writable register that selects test mode, enables the pwm outputs, and selects the output phase and operating speed. dacr is initialized to h'30 by a reset, and in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode.
section 14 14-bit pwm d/a rev. 3.00 jan 11, 2005 page 587 of 1220 rej09b0186-0300o bit 7?test mode (test): selects test mode, which is used in testing the chip. normally this bit should be cleared to 0. bit 7 test description 0 pwm (d/a) in user state: normal operation (initial value) 1 pwm (d/a) in test state: correct conversion results unobtainable bit 6?pwm enable (pwme): starts or stops the pwm d/a counter (dacnt). bit 6 pwme description 0 dacnt operates as a 14-bit up-counter (initial value) 1 dacnt halts at h'0003 bits 5 and 4?reserved: these bits cannot be modified and are always read as 1. bit 3?output enable b (oeb): enables or disables output on pwm d/a channel b. bit 3 oeb description 0 pwm (d/a) channel b output (at the pwm1/pwm3 pin) is disabled (initial value) 1 pwm (d/a) channel b output (at the pwm1/pwm3 pin) is enabled bit 2?output enable a (oea): enables or disables output on pwm d/a channel a. bit 2 oea description 0 pwm (d/a) channel a output (at the pwm0/pwm2 pin) is disabled (initial value) 1 pwm (d/a) channel a output (at the pwm0/pwm2 pin) is enabled
section 14 14-bit pwm d/a rev. 3.00 jan 11, 2005 page 588 of 1220 rej09b0186-0300o bit 1?output select (os): selects the phase of the pwm d/a output. bit 1 os description 0 direct pwm output (initial value) 1 inverted pwm output bit 0?clock select (cks): selects the pwm d/a resolution. if the system clock (?) frequency is 10 mhz, resolutions of 100 ns and 200 ns can be selected. bit 0 cks description 0 operates at resolution (t) = system clock cycle time (t cyc ) (initial value) 1 operates at resolution (t) = system clock cycle time (t cyc ) 2 14.2.4 module stop control register b (mstpcrb) 7 mstpb7 1 r/w 6 mstpb6 1 r/w 5 mstpb5 1 r/w 4 mstpb4 1 r/w 3 mstpb3 1 r/w 0 mstpb0 1 r/w 2 mstpb2 1 r/w 1 mstpb1 1 r/w bit : initial value : r/w : mstpcrb is an 8-bit readable/writable register, and is used to perform module stop mode control. when the mstpb2 is set to 1, at the end of the bus cycle 14-bit pwm timer 0 operation is halted and a transition made to module stop mode. when the mstpb1 is set to 1, at the end of the bus cycle pwm timer 1 operation is halted and a transition made to module stop mode. see section 24.5, module stop mode for details. mstpcrb is initialized to h'ff by a power-on reset and in hardware standby mode. it is not initialized in manual reset or software standby mode. bit 2?module stop (mstpb2): specifies pwm0 module stop mode. bit 2 mstpb2 description 0 pwm0 module stop mode is cleared 1 pwm0 module stop mode is set (initial value)
section 14 14-bit pwm d/a rev. 3.00 jan 11, 2005 page 589 of 1220 rej09b0186-0300o bit 1?module stop (mstpb1): specifies pwm1 module stop mode. bit 1 mstpb1 description 0 pwm1 module stop mode is cleared 1 pwm1 module stop mode is set (initial value) 14.3 bus master interface dacnt, dadra, and dadrb are 16-bit registers. the data bus linking the bus master and the on-chip supporting modules, however, is only 8 bits wide. when the bus master accesses these registers, it therefore uses an 8-bit temporary register (temp). these registers are written and read as follows (taking the example of the cpu interface). ? write when the upper byte is written, the upper-byte write data is stored in temp. next, when the lower byte is written, the lower-byte write data and temp value are combined, and the combined 16-bit value is written in the register. ? read when the upper byte is read, the upper-byte value is transferred to the cpu and the lower-byte value is transferred to temp. next, when the lower byte is read, the lower-byte value in temp is transferred to the cpu. these registers should always be accessed 16 bits at a time (by word access or two consecutive byte accesses), and the upper byte should always be accessed before the lower byte. correct data will not be transferred if only the upper byte or only the lower byte is accessed. figure 14.2 shows the data flow for access to dacnt. the other registers are accessed s imilarly. example 1: write to dacnt mov.w r0, @dacnt ; write r0 contents to dacnt example 2: read dadra mov.w @dadra, r0 ; copy contents of dadra to r0
section 14 14-bit pwm d/a rev. 3.00 jan 11, 2005 page 590 of 1220 rej09b0186-0300o table 14.3 read and write access methods for 16-bit registers read write register name word byte word byte dadra and dadrb yes yes yes dacnt yes yes notes: yes: permitted type of access. word access includes successive byte accesses to the upper byte (first) and lower byte (second). : this type of access may give incorrect results. cpu (h'aa) upper byte bus interface module data bus upper-byte write temp (h'aa) dacntl ( ) dacnth ( ) cpu (h'57) lower byte bus interface module data bus lower-byte write temp (h'aa) dacntl (h'57) dacnth (h'aa) figure 14.2 (a) access to dacnt (cpu writes h'aa57 to dacnt)
section 14 14-bit pwm d/a rev. 3.00 jan 11, 2005 page 591 of 1220 rej09b0186-0300o cpu (h'aa) upper byte bus interface module data bus upper-byte read temp (h'57) dacntl (h'57) dacnth (h'aa) cpu (h'57) lower byte bus interface module data bus lower-byte read temp (h'57) dacntl ( ) dacnth ( ) figure 14.2 (b) access to dacnt (cpu reads h'aa57 from dacnt)
section 14 14-bit pwm d/a rev. 3.00 jan 11, 2005 page 592 of 1220 rej09b0186-0300o 14.4 operation a pwm waveform like the one shown in figure 14.3 is output from the pwmx pin. when os = 0, the value in dadr corresponds to the total width (t l ) of the low (0) pulses output in one conversion cycle (256 pulses when cfs = 0, 64 pulses when cfs = 1). when os = 1, the output waveform is inverted and the dadr value corresponds to the total width (t h ) of the high (1) output pulses. figure 14.4 shows the types of waveform output available. t f t l t l = t ln (when os = 0) m n = 1 1 conversion cycle (t 2 14 (= 16384)) basic cycle (t 64 or t 256) t: resolution legend: (when cfs = 0, m = 256; when cfs = 1, m = 64) figure 14.3 pwm d/a operation table 14.4 summarizes the relationships of the cks, cfs, and os bit settings to the resolution, base cycle, and conversion cycle. the pwm output remains flat unless dadr contains at least a certain minimum value. table 14.4 indicates the range of dadr settings that give an output waveform like the one in figure 14.3, and lists the conversion cycle length when low-order dadr bits are kept cleared to 0, reducing the conversion precision to 12 bits or 10 bits.
section 14 14-bit pwm d/a rev. 3.00 jan 11, 2005 page 593 of 1220 rej09b0186-0300o table 14.4 settings and operation (examples when = 10 mhz) fixed dadr bits bit data cks resolution t (s) cfs base cycle (s) conversion cycle (s) t l (if os = 0) t h (if os = 1) precision (bits) 3210 conversion cycle * (s) 0 0.1 0 6.4 1638.4 1. always low (or high) (dadr = h'0001 to h'03fd) 14 1638.4 2. (data value) t (dadr = h'0401 to h'fffd) 12 00409.6 10 0000102.4 1 25.6 1638.4 1. always low (or high) (dadr = h'0003 to h'00ff) 14 1638.4 2. (data value) t (dadr = h'0103 to h'ffff) 12 00409.6 10 0000102.4 1 0.2 0 12.8 3276.8 1. always low (or high) (dadr = h'0001 to h'03fd) 14 3276.8 2. (data value) t (dadr = h'0401 to h'fffd) 12 00819.2 10 0000204.8 1 51.2 3276.8 1. always low (or high) (dadr = h'0003 to h'00ff) 14 3276.8 2. (data value) t (dadr = h'0103 to h'ffff) 12 00819.2 10 0000204.8 note: * this column indicates the conversion cycle when specific dadr bits are fixed.
section 14 14-bit pwm d/a rev. 3.00 jan 11, 2005 page 594 of 1220 rej09b0186-0300o (1) os = 0 (dadr corresponds to t l ) (a) cfs = 0 [base cycle = resolution (t) 64] t l1 t l2 t l3 t l255 t l256 t f1 t f2 t f255 t f256 1 conversion cycle t f1 = t f2 = t f3 = = t f255 = t f256 = t 64 t l1 + t l2 + t l3 + + t l255 + t l256 = t l figure 14.4 (1) output waveform (b) cfs = 1 [base cycle = resolution (t) 256] t l1 t l2 t l3 t l63 t l64 t f1 t f2 t f63 t f64 1 conversion cycle t f1 = t f2 = t f3 = = t f63 = t f64 = t 256 t l1 + t l2 + t l3 + + t l63 + t l64 = t l figure 14.4 (2) output waveform
section 14 14-bit pwm d/a rev. 3.00 jan 11, 2005 page 595 of 1220 rej09b0186-0300o (2) os = 1 (dadr corresponds to t h ) (a) cfs = 0 [base cycle = resolution (t) 64] t h1 t h2 t h3 t h255 t h256 t f1 t f2 t f255 t f256 1 conversion cycle t f1 = t f2 = t f3 = = t f255 = t f256 = t 64 t h1 + t h2 + t h3 + + t h255 + t h256 = t h figure 14.4 (3) output waveform (b) cfs = 1 [base cycle = resolution (t) 256] t h1 t h2 t h3 t h63 t h64 t f1 t f2 t f63 t f64 1 conversion cycle t f1 = t f2 = t f3 = = t f63 = t f64 = t 256 t h1 + t h2 + t h3 + + t h63 + t h64 = t h figure 14.4 (4) output waveform
section 14 14-bit pwm d/a rev. 3.00 jan 11, 2005 page 596 of 1220 rej09b0186-0300o
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 597 of 1220 rej09b0186-0300o section 15 watchdog timer 15.1 overview the h8s/2643 group has a two channel inbuilt watchdog timer, (wdt0 and wdt1). the wdt outputs an overflow signal ( wdtovf ) if a system crash prevents the cpu from writing to the timer counter, allowing it to overflow. at the same time, the wdt can also generate an internal reset signal for the h8s/2643 group. when this watchdog function is not needed, the wdt can be used as an interval timer. in interval timer operation, an interval timer interrupt is generated each time the counter overflows. 15.1.1 features wdt features are listed below. ? switchable between watchdog timer mode and interval timer mode ? wdtovf output when in watchdog timer mode if the counter overflows, the wdt outputs wdtovf . it is possible to select whether the lsi is internally reset or an nmi interrupt is generated at the same time. this internal reset is effected by either a power-on reset or a manual reset. ? interrupt generation when in interval timer mode if the counter overflows, the wdt generates an interval timer interrupt. ? wdt0 and wdt1 respectively allow eight and sixteen types of counter input clock to be selected the maximum interval of the wdt is given as a system clock cycle 131072 256. a subclock may be selected for the input counter of wdt1. where a subclock is selected, the maximum interval is given as a subclock cycle 256 256. ? selected clock can be output from the buzz output pin (wdt1)
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 598 of 1220 rej09b0186-0300o 15.1.2 block diagram figures 15.1 (a) and 15.1 (b) show block diagrams of the wdt. overflow interrupt control wovi 0 (interrupt request signal) wdtovf internal reset signal * 1 reset control rstcsr tcnt tscr /2 * 2 /64 * 2 /128 * 2 /512 * 2 /2048 * 2 /8192 * 2 /32768 * 2 /131072 * 2 clock clock select internal clock sources bus interface module bus legend: tcsr: tcnt: rstcsr: notes: timer control/status register timer counter reset control/status register internal bus wdt 1. the type of internal reset signal depends on a register setting. there are two alternative types of reset, namely power-on reset and manual reset. 2. the in the subactive and subsleep modes is sub. figure 15.1 (a) block diagram of wdt0
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 599 of 1220 rej09b0186-0300o overflow interrupt control reset control wovi1 (interrupt request signal) buzz internal reset signal * tcnt tcsr /2 /64 /128 /512 /2048 /8192 /32768 /131072 clock clock select internal clock bus interface internal bus module bus tcsr : tcnt : note: * an internal reset signal can be generated by setting the register the reset thus generated is a power on reset timer control/status register timer counter wdt legend: internal nmi interrupt request signal sub/2 sub/4 sub/8 sub/16 sub/32 sub/64 sub/128 sub/256 figure 15.1 (b) block diagram of wdt1
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 600 of 1220 rej09b0186-0300o 15.1.3 pin configuration table 15.1 describes the wdt output pin. table 15.1 wdt pin name symbol i/o function watchdog timer overflow wdtovf output outputs counter overflow signal in watchdog timer mode buzzer output buzz output outputs clock selected by watchdog timer (wdt1) 15.1.4 register configuration table 15.2 summarizes the wdt register configuration. these registers control clock selection, wdt mode switching, and the reset signal. table 15.2 wdt registers address * 1 channel name abbreviation r/w initial value write * 2 read 0 timer control/status register 0 tcsr0 r/(w) * 3 h'18 h'ff74 h'ff74 timer counter 0 tcnt0 r/w h'00 h'ff74 h'ff75 reset control/status register rstcsr r/(w) * 3 h'1f h'ff76 h'ff77 1 timer control/status register 1 tcsr1 r/(w) * 3 h'00 h'ffa2 h'ffa2 timer counter 1 tcnt1 r/w h'00 h'ffa2 h'ffa3 all pin function control register pfcr r/w h'0d/h'00 h'fdeb notes: 1. lower 16 bits of the address. 2. for details of write operations, see section 15.2.5, notes on register access. 3. only a write of 0 is permitted to bit 7, to clear the flag.
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 601 of 1220 rej09b0186-0300o 15.2 register descriptions 15.2.1 timer counter (tcnt) bit:76543210 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w tcnt is an 8-bit readable/writable* up-counter. when the tme bit is set to 1 in tcsr, tcnt starts counting pulses generated from the internal clock source selected by bits cks2 to cks0 in tcsr. when the count overflows (changes from h'ff to h'00), either the watchdog timer overflow signal ( wdtovf ) or an interval timer interrupt (wovi) is generated, depending on the mode selected by the wt/ it bit in tcsr. tcnt is initialized to h'00 by a reset, in hardware standby mode, or when the tme bit is cleared to 0. it is not initialized in software standby mode. note: * tcnt is write-protected by a password to prevent accidental overwriting. for details see section 15.2.5, notes on register access. 15.2.2 timer control/status register (tcsr) tcsr0 bit:76543210 ovf wt/ it tme ? ? cks2 cks1 cks0 initial value:00011000 r/w : r/(w) * r/w r/w ? ? r/w r/w r/w note: * only 0 can be written, for flag clearing.
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 602 of 1220 rej09b0186-0300o tcsr1 bit:76543210 ovf wt/ it tme pss rst/ nmi cks2 cks1 cks0 initial value:00000000 r/w : r/(w) * r/w r/w r/w r/w r/w r/w r/w note: * only 0 can be written, for flag clearing. tcsr is an 8-bit readable/writable* register. its functions include selecting the clock source to be input to tcnt, and the timer mode. tcsr0 (tcsr1) is initialized to h'18 (h'00) by a reset and in hardware standby mode. it is not initialized in software standby mode. note: * tcsr is write-protected by a password to prevent accidental overwriting. for details see section 15.2.5, notes on register access. bit 7?overflow flag (ovf): indicates that tcnt has overflowed from h'ff to h'00. bit 7 ovf description 0 [clearing conditions] (initial value) ? cleared when 0 is written to the tme bit (only applies to wdt1) ? cleared by reading tcsr when ovf = 1, then writing 0 to ovf 1 [setting condition] ? when tcnt overflows (changes from h'ff to h'00) when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset. bit 6?timer mode select (wt/ it ): selects whether the wdt is used as a watchdog timer or interval timer. when tcnt overflows, wdt0 generates the wdtovf signal when in watchdog timer mode, or a wovi interrupt request to the cpu when in interval timer mode. wdt1 generates a reset or nmi interrupt request when in watchdog timer mode, or a wovi interrupt request to the cpu when in interval timer mode.
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 603 of 1220 rej09b0186-0300o wdt0 mode select wdt0 wt/ it description 0 interval timer mode: wdt0 requests an interval timer interrupt (wovi) from the cpu when the tcnt overflows. (initial value) 1 watchdog timer mode: wdt0 outputs a wdtovf signal when the tcnt overflows. * note: * for details on a tcnt overflow in watchdog timer mode, see section 15.2.3, reset control/status register (rstcsr). wdt1 mode select wdt1 wt/ it description 0 interval timer mode: wdt1 requests an interval timer interrupt (wovi) from the cpu when the tcnt overflows. (initial value) 1 watchdog timer mode: wdt1 requests a reset or an nmi interrupt from the cpu when the tcnt overflows. bit 5?timer enable (tme): selects whether tcnt runs or is halted. bit 5 tme description 0 tcnt is initialized to h'00 and halted (initial value) 1 tcnt counts wdt0 tcsr bit 4?reserved bit: this bit is always read as 1 and cannot be modified. wdt1 tcsr bit 4?prescaler select (pss): this bit is used to select an input clock source for the tcnt of wdt1. see the descriptions of clock select 2 to 0 for details.
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 604 of 1220 rej09b0186-0300o wdt1 tcsr bit 4 pss description 0 the tcnt counts frequency-division clock pulses of the based prescaler (psm). (initial value) 1 the tcnt counts frequency-division clock pulses of the sub-based prescaler (pss). wdt0 tcsr bit 3?reserved bit: this bit is always read as 1 and cannot be modified. wdt1 tcsr bit 3?reset or nmi (rst/ nmi ): this bit is used to choose between an internal reset request and an nmi request when the tcnt overflows during the watchdog timer mode. bit 3 rts/ nmi description 0 nmi request. (initial value) 1 internal reset request. bits 2 to 0: clock select 2 to 0 (cks2 to cks0): these bits select one of eight internal clock sources, obtained by dividing the system clock ( ) or subclock ( sub), for input to tcnt. wdt0 input clock select bit 2 bit 1 bit 0 description cks2 cks1 cks0 clock overflow period * (where = 25 mhz) 000 /2 (initial value) 20.4 s 1 /64 655.3 s 10 /128 1.3 ms 1 /512 5.2 ms 100 /2048 20.9 ms 1 /8192 83.8 ms 10 /32768 335.5 ms 1 /131072 1.34 s note: * an overflow period is the time interval between the start of counting up from h'00 on the tcnt and the occurrence of a tcnt overflow.
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 605 of 1220 rej09b0186-0300o wdt1 input clock select bit 4 bit 2 bit 1 bit 0 description pss cks2 cks1 cks0 clock * 2 overflow period * 1 (where = 25 mhz) (where sub = 32.768 khz) 0000 /2 (initial value) 20.4 s 1 /64 655.3 s 10 /128 1.3 ms 1 /512 5.2 ms 100 /2048 20.9 ms 1 /8192 83.8 ms 10 /32768 335.5 ms 1 /131072 1.34 s 1000 sub/2 15.6 ms 1 sub/4 31.3 ms 10 sub/8 62.5 ms 1 sub/16 125 ms 100 sub/32 250 ms 1 sub/64 500 ms 10 sub/128 1 s 1 sub/256 2 s notes: 1. an overflow period is the time interval between the start of counting up from h'00 on the tcnt and the occurrence of a tcnt overflow. 2. the in the subactive and subsleep modes is sub.
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 606 of 1220 rej09b0186-0300o 15.2.3 reset control/status register (rstcsr) bit:76543210 wovf rste rsts ? ? ? ? ? initial value:00011111 r/w : r/(w) * r/wr/w????? note: * only 0 can be written, for flag clearing. rstcsr is an 8-bit readable/writable* register that controls the generation of the internal reset signal when tcnt overflows, and selects the type of internal reset signal. rstcsr is initialized to h'1f by a reset signal from the res pin, but not by the wdt internal reset signal caused by overflows. note: * rstcsr is write-protected by a password to prevent accidental overwriting. for details see section 15.2.5, notes on register access. bit 7?watchdog overflow flag (wovf): indicates that tcnt has overflowed (changed from h'ff to h'00) during watchdog timer operation. this bit is not set in interval timer mode. bit 7 wovf description 0 [clearing condition] (initial value) ? cleared by reading tcsr when wovf = 1, then writing 0 to wovf 1 [setting condition] ? set when tcnt overflows (changed from h'ff to h'00) during watchdog timer operation bit 6?reset enable (rste): specifies whether or not a reset signal is generated in the h8s/2643 group if tcnt overflows during watchdog timer operation. bit 6 rste description 0 reset signal is not generated if tcnt overflows * (initial value) 1 reset signal is generated if tcnt overflows note: * the modules within the h8s/2643 group are not reset, but tcnt and tcsr within the wdt are reset.
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 607 of 1220 rej09b0186-0300o bit 5?reset select (rsts): selects the type of internal reset generated if tcnt overflows during watchdog timer operation. for details of the types of reset, see section 4, exception handling. bit 5 rsts description 0 power-on reset (initial value) 1 manual reset bits 4 to 0?reserved: these bits are always read as 1 and cannot be modified. 15.2.4 pin function control register (pfcr) 7 css07 0 r/w 6 css36 0 r/w 5 buzze 0 r/w 4 lcass 0 r/w 3 ae3 1/0 r/w 0 ae0 1/0 r/w 2 ae2 1/0 r/w 1 ae1 0 r/w bit initial value r/w : : : pfcr is an 8-bit readable/writable register that performs address output control in external expanded mode. only bit 5 is described here. for details of the other bits, see section 7.2.6, pin function control register (pfcr). bit 5?buzz output enable (buzze): enables or disables buzz output from the pf1 pin. the wdt1 input clock selected with bits pss and cks2 to cks0 is output as the buzz signal. bit 5 buzze description 0 functions as pf1 i/o pin (initial value) 1 functions as buzz output pin
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 608 of 1220 rej09b0186-0300o 15.2.5 notes on register access the watchdog timer?s tcnt, tcsr, and rstcsr registers differ from other registers in being more difficult to write to. the procedures for writing to and reading these registers are given below. (1) writing to tcnt and tcsr these registers must be written to by a word transfer instruction. they cannot be written to with byte instructions. figure 15.2 shows the format of data written to tcnt and tcsr. tcnt and tcsr both have the same write address. for a write to tcnt, the upper byte of the written word must contain h'5a and the lower byte must contain the write data. for a write to tcsr, the upper byte of the written word must contain h'a5 and the lower byte must contain the write data. this transfers the write data from the lower byte to tcnt or tcsr. tcnt write tcsr write address: h'ff74 address: h'ff74 h'5a write data 15 8 7 0 h'a5 write data 15 8 7 0 figure 15.2 format of data written to tcnt and tcsr
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 609 of 1220 rej09b0186-0300o (2) writing to rstcsr rstcsr must be written to by word transfer instruction to address h'ff76. it cannot be written to with byte instructions. figure 15.3 shows the format of data written to rstcsr. the method of writing 0 to the wovf bit differs from that for writing to the rste and rsts bits. to write 0 to the wovf bit, the write data must have h'a5 in the upper byte and h'00 in the lower byte. this clears the wovf bit to 0, but has no effect on the rste and rsts bits. to write to the rste and rsts bits, the upper byte must contain h'5a and the lower byte must contain the write data. this writes the values in bits 6 and 5 of the lower byte into the rste and rsts bits, but has no effect on the wovf bit. h'a5 h'00 15 8 7 0 h'5a write data 15 8 7 0 writing 0 to wovf bit writing to rste and rsts bits address: h'ff76 address: h'ff76 figure 15.3 format of data written to rstcsr (3) reading tcnt, tcsr, and rstcsr (wdt0) these registers are read in the same way as other registers. the read addresses are h'ff74 for tcsr, h'ff75 for tcnt, and h'ff77 for rstcsr.
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 610 of 1220 rej09b0186-0300o 15.3 operation 15.3.1 watchdog timer operation to use the wdt as a watchdog timer, set the wt/ it bit in tcsr and tme bit to 1. software must prevent tcnt overflows by rewriting the tcnt value (normally be writing h'00) before overflows occurs. this ensures that tcnt does not overflow while the system is operating normally. if tcnt overflows without being rewritten because of a system crash or other error, in the wdt0 the wdtovf signal is output. this is shown in figure 15.4 (a). this wdtovf signal can be used to reset the system. the wdtovf signal is output for 132 states when rste = 1, and for 130 states when rste = 0. if tcnt overflows when 1 is set in the rste bit in rstcsr, a signal that resets the h8s/2643 group internally is generated at the same time as the wdtovf signal. this reset can be selected as a power-on reset or a manual reset, depending on the setting of the rsts bit in rstcsr. the internal reset signal is output for 518 states. if a reset caused by a signal input to the res pin occurs at the same time as a reset caused by a wdt overflow, the res pin reset has priority and the wovf bit in rstcsr is cleared to 0. in the case of wdt1, the chip is reset, or an nmi interrupt request is generated, for 516 system clock periods (516 ) (515 or 516 states when the clock source is sub (pss = 1)). this is illustrated in figure 15.4 (b). an nmi request from the watchdog timer and an interrupt request from the nmi pin are both treated as having the same vector. so, avoid handling an nmi request from the watchdog timer and an interrupt request from the nmi pin at the same time.
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 611 of 1220 rej09b0186-0300o tcnt count h'00 time h'ff wt/ it = 1 tme = 1 h'00 written to tcnt wt/ it = 1 tme = 1 h'00 written to tcnt 132 states * 2 518 states wdtovf signal internal reset signal * 1 wt/ it : tme: notes: 1. the internal reset signal is generated only if the rste bit is set to 1. 2. 130 states when the rste bit is cleared to 0. overflow wdtovf and internal reset are generated wovf = 1 timer mode select bit timer enable bit legend: figure 15.4 (a) wdt0 watchdog timer operation
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 612 of 1220 rej09b0186-0300o tcnt value h'00 time h'ff wt/it = 1 tme = 1 write h'00 to tcnt wt/it = 1 tme = 1 write h'00 to tcnt 515/516 states internal reset signal wt/it: tme: overflow occurrence of internal reset wovf = 1 * timer mode select bit timer enable bit note: * the wovf bit is set to 1 and then cleared to 0 by an internal reset. legend: figure 15.4 (b) wdt1 operation in watchdog timer mode
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 613 of 1220 rej09b0186-0300o 15.3.2 interval timer operation to use the wdt as an interval timer, clear the wt/ it bit in tcsr to 0 and set the tme bit to 1. an interval timer interrupt (wovi) is generated each time tcnt overflows, provided that the wdt is operating as an interval timer, as shown in figure 15.5. this function can be used to generate interrupt requests at regular intervals. tcnt count h'00 time h'ff wt/ it = 0 tme = 1 wovi overflow overflow overflow overflow legend: wovi: interval timer interrupt re q uest g eneration wovi wovi wovi figure 15.5 interval timer operation 15.3.3 timing of setting overflow flag (ovf) the ovf flag is set to 1 if tcnt overflows during interval timer operation. at the same time, an interval timer interrupt (wovi) is requested. this timing is shown in figure 15.6. with wdt1, the ovf bit of the tcsr is set to 1 and a simultaneous nmi interrupt is requested when the tcnt overflows if the nmi request has been chosen in the watchdog timer mode.
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 614 of 1220 rej09b0186-0300o figure 15.6 timing of setting of ovf 15.3.4 timing of setting of watchdog timer overflow flag (wovf) in the wdt0, the wovf flag is set to 1 if tcnt overflows during watchdog timer operation. at the same time, the wdtovf signal goes low. if tcnt overflows while the rste bit in rstcsr is set to 1, an internal reset signal is generated for the entire h8s/2643 group chip. figure 15.7 shows the timing in this case. figure 15.7 timing of setting of wovf
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 615 of 1220 rej09b0186-0300o 15.4 interrupts during interval timer mode operation, an overflow generates an interval timer interrupt (wovi). the interval timer interrupt is requested whenever the ovf flag is set to 1 in tcsr. ovf must be cleared to 0 in the interrupt handling routine. if an nmi request has been chosen in the watchdog timer mode, an nmi request is generated when a tcnt overflow occurs. 15.5 usage notes 15.5.1 contention between timer counter (tcnt) write and increment if a timer counter clock pulse is generated during the t 2 state of a tcnt write cycle, the write takes priority and the timer counter is not incremented. figure 15.8 shows this operation. address figure 15.8 contention between tcnt write and increment
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 616 of 1220 rej09b0186-0300o 15.5.2 changing value of pss and cks2 to cks0 if bits pss and cks2 to cks0 in tcsr are written to while the wdt is operating, errors could occur in the incrementation. software must stop the watchdog timer (by clearing the tme bit to 0) before changing the value of bits pss and cks2 to cks0. 15.5.3 switching between watchdog timer mode and interval timer mode if the mode is switched from watchdog timer to interval timer, or vice versa, while the wdt is operating, errors could occur in the incrementation. software must stop the watchdog timer (by clearing the tme bit to 0) before switching the mode. 15.5.4 system reset by wdtovf signal if the wdtovf output signal is input to the res pin of the h8s/2643 group, the h8s/2643 group w ill not be initialized correctly. make sure that the wdtovf signal is not input logically to the res pin. to reset the entire system by means of the wdtovf signal, use the circuit shown in figure 15.9. reset input reset signal to entire system h8s/2643 group res wdtovf figure 15.9 circuit for system reset by wdtovf signal (example) 15.5.5 internal reset in watchdog timer mode the h8s/2643 group is not reset internally if tcnt overflows while the rste bit is cleared to 0 during watchdog timer operation, but tcnt and tcsr of the wdt are reset. tcnt, tcsr, and rstcsr cannot be written to while the wdtovf signal is low. also note that a read of the wovf flag is not recognized during this period. to clear the wovf falg, therefore, read tcsr after the wdtovf signal goes high, then write 0 to the wovf flag.
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 617 of 1220 rej09b0186-0300o 15.5.6 ovf flag clearing in interval timer mode if conflict occurs between ovf flag clearing and ovf flag reading in interval timer mode, the flag may not be cleared by writing 0 to ovf even though the ovf = 1 state has been read. when interval timer interrupts are disabled and the ovf flag is polled, for instance, and there is a possibility of conflict between ovf flag setting and reading, the ovf = 1 state s hould be read at least twice before writing 0 to ovf in order to clear the flag.
section 15 watchdog timer rev. 3.00 jan 11, 2005 page 618 of 1220 rej09b0186-0300o
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 619 of 1220 rej09b0186-0300o section 16 serial communication interface (sci, irda) 16.1 overview the h8s/2643 is equipped with 5 independent serial communication interface (sci) channels. the sci can handle both asynchronous and clocked synchronous serial communication. a function is also provided for serial communication between processors (multiprocessor communication function). one of the five sci channels is capable of sending and receiving irda communications waveforms (based on irda version 1.0). 16.1.1 features sci features are listed below. ? choice of asynchronous or clocked synchronous serial communication mode asynchronous mode ? serial data communication executed using asynchronous system in which synchronization is achieved character by character serial data communication can be carried out with standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or asynchronous communication interface adapter (acia) ? a multiprocessor communication function is provided that enables serial data communication with a number of processors ? choice of 12 serial data transfer formats data length : 7 or 8 bits stop bit length : 1 or 2 bits parity : even, odd, or none multiprocessor bit : 1 or 0 ? receive error detection : parity, overrun, and framing errors ? break detection : break can be detected by reading the rxd pin level directly in case of a framing error clocked synchronous mode ? serial data communication synchronized with a clock serial data communication can be carried out with other chips that have a synchronous communication function
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 620 of 1220 rej09b0186-0300o ? one serial data transfer format ? data length : 8 bits ? receive error detection : overrun errors detected ? full-duplex communication capab ility ? the transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously ? double-buffering is used in both the trans mitter and the r eceiver, enabling continuous transmission and continuous reception of serial data ? choice of lsb-first or msb-first transfer ? can be selected regardless of the communication mode* (except in the case of asynchronous mode 7-bit data) note: * descriptions in this section refer to lsb-first transfer. ? on-chip baud rate generator allows any bit rate to be selected ? choice of serial clock source: internal clock from baud rate generator or external clock from sck pin ? four interrupt sources ? four interrupt sources ? transmit-data-empty, transmit-end, receive-data-full, and receive error ? that can issue requests independently ? the transmit-data-empty interrupt and receive data full interrupts can activate the dma controller (dmac) or data transfer controller (dtc) to execute data transfer ? module stop mode can be set ? as the initial setting, sci operation is halted. register access is enabled by exiting module stop mode.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 621 of 1220 rej09b0186-0300o 16.1.2 block diagram figure 16.1 shows a block diagram of the sci. bus interface tdr rsr rdr module data bus tsr scmr ssr scr transmission/ reception control brr baud rate generator internal data bus rxd txd sck parity generation parity check clock external clock /4 /16 /64 txi tei rxi eri smr legend: rsr: rdr: tsr: tdr: smr: scr: ssr: scmr: brr: receive shift register receive data register transmit shift register transmit data register serial mode register serial control register serial status register smart card mode register bit rate register figure 16.1 block diagram of sci
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 622 of 1220 rej09b0186-0300o 16.1.3 pin configuration table 16.1 shows the serial pins for each sci channel. table 16.1 sci pins channel pin name symbol * i/o function 0 serial clock pin 0 sck0 i/o sci0 clock input/output receive data pin 0 rxd0/irrxd input sci0 receive data input (normal/irda) transmit data pin 0 txd0/irtxd output sci0 transmit data output (normal/irda) 1 serial clock pin 1 sck1 i/o sci1 clock input/output receive data pin 1 rxd1 input sci1 receive data input transmit data pin 1 txd1 output sci1 transmit data output 2 serial clock pin 2 sck2 i/o sci2 clock input/output receive data pin 2 rxd2 input sci2 receive data input transmit data pin 2 txd2 output sci2 transmit data output 3 serial clock pin 3 sck3 i/o sci3 clock input/output receive data pin 3 rxd3 input sci3 receive data input transmit data pin 3 txd3 output sci3 transmit data output 4 serial clock pin 4 sck4 i/o sci4 clock input/output receive data pin 4 rxd4 input sci4 receive data input transmit data pin 4 txd4 output sci4 transmit data output note: * pin names sck, rxd, and txd are used in the text for all channels, omitting the channel designation.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 623 of 1220 rej09b0186-0300o 16.1.4 register configuration the sci has the internal registers shown in table 16.2. these registers are used to specify asynchronous mode or clocked synchronous mode, the data format , and the bit rate, and to control transmitter/r eceiver. table 16.2 sci registers channel name abbreviation r/w initial value address * 1 0 serial mode register 0 smr0 r/w h'00 h'ff78 * 3 bit rate register 0 brr0 r/w h'ff h'ff79 * 3 serial control register 0 scr0 r/w h'00 h'ff7a * 3 transmit data register 0 tdr0 r/w h'ff h'ff7b * 3 serial status register 0 ssr0 r/(w) * 2 h'84 h'ff7c * 3 receive data register 0 rdr0 r h'00 h 'ff7d * 3 smart card mode register 0 scmr0 r/w h'f2 h'ff7e * 3 irda control register ircr r/w h'00 h'fdb0 1 serial mode register 1 smr1 r/w h'00 h'ff80 * 3 bit rate register 1 brr1 r/w h'ff h'ff81 * 3 serial control register 1 scr1 r/w h'00 h'ff82 * 3 transmit data register 1 tdr1 r/w h'ff h'ff83 * 3 serial status register 1 ssr1 r/(w) * 2 h'84 h'ff84 * 3 receive data register 1 rdr1 r h'00 h 'ff85 * 3 smart card mode register 1 scmr1 r/w h'f2 h'ff86 * 3 2 serial mode register 2 smr2 r/w h'00 h'ff88 bit rate register 2 brr2 r/w h'ff h'ff89 serial control register 2 scr2 r/w h'00 h'ff8a transmit data register 2 tdr2 r/w h'ff h'ff8b serial status register 2 ssr2 r/(w) * 2 h'84 h'ff8c receive data register 2 rdr2 r h'00 h 'ff8d smart card mode register 2 scmr2 r/w h'f2 h'ff8e
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 624 of 1220 rej09b0186-0300o channel name abbreviation r/w initial value address * 1 3 serial mode register 3 smr3 r/w h'00 h'fdd0 bit rate register 3 brr3 r/w h'ff h'fdd1 serial control register 3 scr3 r/w h'00 h'fdd2 transmit data register 3 tdr3 r/w h'ff h'fdd3 serial status register 3 ssr3 r/(w) * 2 h'84 h'fdd4 receive data register 3 rdr3 r h'00 h'fdd5 smart card mode register 3 scmr3 r/w h'f2 h'fdd6 4 serial mode register 4 smr4 r/w h'00 h'fdd8 bit rate register 4 brr4 r/w h'ff h'fdd9 serial control register 4 scr4 r/w h'00 h'fdda transmit data register 4 tdr4 r/w h'ff h'fddb serial status register 4 ssr4 r/(w) * 2 h'84 h'fddc receive data register 4 rdr4 r h'00 h'fddd smart card mode register 4 scmr4 r/w h'f2 h'fdde all module stop control register b mstpcrb r/w h'ff h'fde9 module stop control register c mstpcrc r/w h'ff h'fdea notes: 1. lower 16 bits of the address. 2. only 0 can be written, for flag clearing. 3. some of the sci registers are allocated to the same addresses as other registers. the iice bit of the serial timer control register x (scrx) selects the respective registers.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 625 of 1220 rej09b0186-0300o 16.2 register descriptions 16.2.1 receive shift register (rsr) 7 ? 6 ? 5 ? 4 ? 3 ? 0 ? 2 ? 1 ? bit r/w : : rsr is a register used to receive serial data. the sci sets serial data input from the rxd pin in rsr in the order received, starting with the lsb (bit 0), and converts it to parallel data. when one byte of data has been received, it is transferred to rdr automatically. rsr cannot be directly read or written to by the cpu. 16.2.2 receive data register (rdr) 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value r/w : : : rdr is a register that stores received serial data. when the sci has received one byte of serial data, it transfers the received serial data from rsr to rdr where it is stored, and completes the receive operation. after this, rsr is receive-enabled. since rsr and rdr function as a double buffer in this way, enables continuous receive operations to be performed. rdr is a read-only register, and cannot be written to by the cpu. rdr is initialized to h'00 by a reset, in standby mode, watch mode, subactive mode, and subsleep mode or module stop mode.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 626 of 1220 rej09b0186-0300o 16.2.3 transmit shift register (tsr) 7 ? 6 ? 5 ? 4 ? 3 ? 0 ? 2 ? 1 ? bit r/w : : tsr is a register used to transmit serial data. to perform serial data transmission, the sci first transfers transmit data from tdr to tsr, then sends the data to the txd pin starting with the lsb (bit 0). when transmission of one byte is completed, the next transmit data is transferred from tdr to tsr, and transmission started, automatically. however, data transfer from tdr to tsr is not performed if the tdre bit in ssr is set to 1. tsr cannot be directly read or written to by the cpu. 16.2.4 transmit data register (tdr) 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : : tdr is an 8-bit register that stores data for serial transmission. when the sci detects that tsr is empty, it transfers the transmit data written in tdr to tsr and starts serial transmission. continuous serial transmission can be carried out by writing the next transmit data to tdr during serial transmission of the data in tsr. tdr can be read or written to by the cpu at all times. tdr is initialized to h'ff by a reset, in standby mode, watch mode, subactive mode, and subsleep mode or module stop mode.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 627 of 1220 rej09b0186-0300o 16.2.5 serial mode register (smr) 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w bit initial value r/w : : : smr is an 8-bit register used to set the sci?s serial transfer format and select the baud rate generator clock source. smr can be read or written to by the cpu at all times. smr is initialized to h'00 by a reset and in hardware standby mode. bit 7?communication mode (c/ a ): selects asynchronous mode or clocked synchronous mode as the sci operating mode. bit 7 c/ a description 0 asynchronous mode (initial value) 1 clocked synchronous mode bit 6?character length (chr): selects 7 or 8 bits as the data length in asynchronous mode. in clocked synchronous mode, a fixed data length of 8 bits is used regardless of the chr setting. bit 6 chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted, and it is not possible to choose between lsb-first or msb-first transfer.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 628 of 1220 rej09b0186-0300o bit 5?parity enable (pe): in asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. in clocked synchronous mode with a multiprocessor format, parity bit addition and checking is not performed, regardless of the pe bit setting. bit 5 pe description 0 parity bit addition and checking disabled (initial value) 1 parity bit addition and checking enabled * note: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/ e bit. bit 4?parity mode (o/ e ): selects either even or odd parity for use in parity addition and checking. the o/ e bit setting is only valid when the pe bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. the o/ e bit setting is invalid in clocked synchronous mode, when parity addition and checking is disabled in asynchronous mode, and when a multiprocessor format is used. bit 4 o/ e description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. when even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 629 of 1220 rej09b0186-0300o bit 3?stop bit length (stop): selects 1 or 2 bits as the stop bit length in asynchronous mode. the stop bits setting is only valid in asynchronous mode. if clocked synchronous mode is set the stop bit setting is invalid since stop bits are not added. bit 3 stop description 0 1 stop bit: in transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. (initial value) 1 2 stop bits: in transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. in reception, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. bit 2?multiprocessor mode (mp): selects multiprocessor format. when multiprocessor format is selected, the pe bit and o/ e bit parity settings are invalid. the mp bit setting is only valid in asynchronous mode; it is invalid in clocked synchronous mode. for details of the multiprocessor communication function, see section 16.3.3, multiprocessor communication function. bit 2 mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 630 of 1220 rej09b0186-0300o bits 1 and 0?clock select 1 and 0 (cks1, cks0): these bits select the clock source for the baud rate generator. the clock source can be selected from , /4, /16, and /64, according to the setting of bits cks1 and cks0. for the relation between the clock source, the bit rate register setting, and the baud rate, see section 16.2.8, bit rate register. bit 1 bit 0 cks1 cks0 description 00 clock (initial value) 1 /4 clock 10 /16 clock 1 /64 clock 16.2.6 serial control register (scr) 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value r/w : : : scr is a register that performs enabling or disabling of sci transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. scr can be read or written to by the cpu at all times. scr is initialized to h'00 by a reset and in standby mode. bit 7?transmit interrupt enable (tie): enables or disables transmit data empty interrupt (txi) request generation when serial transmit data is transferred from tdr to tsr and the tdre flag in ssr is set to 1. bit 7 tie description 0 transmit data empty interrupt (txi) requests disabled (initial value) 1 transmit data empty interrupt (txi) requests enabled note: txi interrupt request cancellation can be performed by reading 1 from the tdre flag, then clearing it to 0, or clearing the tie bit to 0.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 631 of 1220 rej09b0186-0300o bit 6?receive interrupt enable (rie): enables or disables receive data full interrupt (rxi) request and receive error interrupt (eri) request generation when serial receive data is transferred from rsr to rdr and the rdrf flag in ssr is set to 1. bit 6 rie description 0 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled * (initial value) 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled note: * rxi and eri interrupt request cancellation can be performed by reading 1 from the rdrf flag, or the fer, per, or orer flag, then clearing the flag to 0, or clearing the rie bit to 0. bit 5?transmit enable (te): enables or disables the start of serial transmission by the sci. bit 5 te description 0 transmission disabled * 1 (initial value) 1 transmission enabled * 2 notes: 1. the tdre flag in ssr is fixed at 1. 2. in this state, serial transmission is started when transmit data is written to tdr and the tdre flag in ssr is cleared to 0. smr setting must be performed to decide the transfer format before setting the te bit to 1. bit 4?receive enable (re): enables or disables the start of serial reception by the sci. bit 4 re description 0 reception disabled * 1 (initial value) 1 reception enabled * 2 notes: 1. clearing the re bit to 0 does not affect the rdrf, fer, per, and orer flags, which retain their states. 2. serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. smr setting must be performed to decide the transfer format before setting the re bit to 1.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 632 of 1220 rej09b0186-0300o bit 3?multiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie bit setting is only valid in asynchronous mode when the mp bit in smr is set to 1. the mpie bit setting is invalid in clocked synchronous mode or when the mp bit is cleared to 0. bit 3 mpie description 0 multiprocessor interrupts disabled (normal reception performed) (initial value) [clearing conditions] ? when the mpie bit is cleared to 0 ? when mpb= 1 data is received 1 multiprocessor interrupts enabled * receive interrupt (rxi) requests, receive error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. note: * when receive data including mpb = 0 is received, receive data transfer from rsr to rdr, receive error detection, and setting of the rdrf, fer, and orer flags in ssr , is not performed. when receive data including mpb = 1 is received, the mpb bit in ssr is set to 1, the mpie bit is cleared to 0 automatically, and generation of rxi and eri interrupts (when the tie and rie bits in scr are set to 1) and fer and orer flag setting is enabled. bit 2?transmit end interrupt enable (teie): enables or disables transmit end interrupt (tei) request generation when there is no valid transmit data in tdr in msb data transmission. bit 2 teie description 0 transmit end interrupt (tei) request disabled * (initial value) 1 transmit end interrupt (tei) request enabled * note: * tei cancellation can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0 and clearing the tend flag to 0, or clearing the teie bit to 0.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 633 of 1220 rej09b0186-0300o bits 1 and 0?clock enable 1 and 0 (cke1, cke0): these bits are used to select the sci clock source and enable or disable clock output from the sck pin. the combination of the cke1 and cke0 bits determines whether the sck pin functions as an i/o port, the serial clock output pin, or the serial clock input pin. the setting of the cke0 bit, however, is only valid for internal clock operation (cke1 = 0) in asynchronous mode. the cke0 bit setting is invalid in clocked synchronous mode, and in the case of external clock operation (cke1 = 1). note that the sci?s operating mode must be decided using smr before setting the cke1 and cke0 bits. for details of clock source selection, see table 16.9. bit 1 bit 0 cke1 cke0 description 0 0 asynchronous mode internal clock/sck pin functions as i/o port * 1 clocked synchronous mode internal clock/sck pin functions as serial clock output * 1 1 asynchronous mode internal clock/sck pin functions as clock output * 2 clocked synchronous mode internal clock/sck pin functions as serial clock output 1 0 asynchronous mode external clock/sck pin functions as clock input * 3 clocked synchronous mode external clock/sck pin functions as serial clock input 1 asynchronous mode external clock/sck pin functions as clock input * 3 clocked synchronous mode external clock/sck pin functions as serial clock input notes: 1. initial value 2. outputs a clock of the same frequency as the bit rate. 3. inputs a clock with a frequency 16 times the bit rate.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 634 of 1220 rej09b0186-0300o 16.2.7 serial status register (ssr) 7 tdre 1 r/ ( w ) * 6 rdrf 0 r/ ( w ) * 5 orer 0 r/ ( w ) * 4 fer 0 r/ ( w ) * 3 per 0 r/ ( w ) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value r/w : : : note: * only 0 can be written, to clear the flag. ssr is an 8-bit register containing status flags that indicate the operating status of the sci, and multiprocessor bits. ssr can be read or written to by the cpu at all times. however, 1 cannot be written to flags tdre, rdrf, orer, per, and fer. also note that in order to clear these flags they must be read as 1 beforehand. the tend flag and mpb flag are read-only flags and cannot be modified. ssr is initialized to h'84 by a reset, in standby mode, watch mode, subactive mode, and subsleep mode or module stop mode. bit 7?transmit data register empty (tdre): indicates that data has been transferred from tdr to tsr and the next serial data can be written to tdr. bit 7 tdre description 0 [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dmac or dtc is activated by a txi interrupt and writes data to tdr 1 [setting conditions] (initial value) ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr and data can be written to tdr
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 635 of 1220 rej09b0186-0300o bit 6?receive data register full (rdrf): indicates that the received data is stored in rdr. bit 6 rdrf description 0 [clearing conditions] (initial value) ? when 0 is written to rdrf after reading rdrf = 1 ? when the dmac or dtc is activated by an rxi interrupt and reads data from rdr 1 [setting condition] ? when serial reception ends normally and receive data is transferred from rsr to rdr note: rdr and the rdrf flag are not affected and retain their previous values when an error is detected during reception or when the re bit in scr is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost. bit 5?overrun error (orer): indicates that an overrun error occurred during reception, causing abnormal termination. bit 5 orer description 0 [clearing condition] (initial value) * 1 ? when 0 is written to orer after reading orer = 1 1 [setting condition] ? when the next serial reception is completed while rdrf = 1 notes: 1. the orer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. the receive data prior to the overrun error is retained in rdr, and the data received subsequently is lost. also, subsequent serial reception cannot be continued while the orer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 636 of 1220 rej09b0186-0300o bit 4?framing error (fer): indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. bit 4 fer description 0 [clearing condition] (initial value) * 1 ? when 0 is written to fer after reading fer = 1 1 [setting condition] ? when the sci checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 * 2 notes: 1. the fer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. in 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. if a framing error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the fer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. bit 3?parity error (per): indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. bit 3 per description 0 [clearing condition] (initial value) * 1 ? when 0 is written to per after reading per = 1 1 [setting condition] ? when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr * 2 notes: 1. the per flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the per flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 637 of 1220 rej09b0186-0300o bit 2?transmit end (tend): indicates that there is no valid data in tdr when the last bit of the transmit character is sent, and transmission has been ended. the tend flag is read-only and cannot be modified. bit 2 tend description 0 [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dmac or dtc is activated by a txi interrupt and writes data to tdr 1 [setting conditions] (initial value) ? when the te bit in scr is 0 ? when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character bit 1?multiprocessor bit (mpb): when reception is performed using multiprocessor format in asynchronous mode, mpb stores the multiprocessor bit in the receive data. mpb is a read-only bit, and cannot be modified. bit 1 mpb description 0 [clearing condition] (initial value) * ? when data with a 0 multiprocessor bit is received 1 [setting condition] ? when data with a 1 multiprocessor bit is received note: * retains its previous state when the re bit in scr is cleared to 0 with multiprocessor format. bit 0?multiprocessor bit transfer (mpbt): when transmission is performed using multiprocessor format in asynchronous mode, mpbt stores the multiprocessor bit to be added to the transmit data. the mpbt bit setting is invalid when multiprocessor format is not used, when not transmitting, and in clocked synchronous mode. bit 0 mpbt description 0 data with a 0 multiprocessor bit is transmitted (initial value) 1 data with a 1 multiprocessor bit is transmitted
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 638 of 1220 rej09b0186-0300o 16.2.8 bit rate register (brr) 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : : brr is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 in smr. brr can be read or written to by the cpu at all times. brr is initialized to h'ff by a reset and in standby mode. as baud rate generator control is performed independently for each channel, different values can be set for each channel. table 16.3 shows sample brr settings in asynchronous mode, and table 16.4 shows sample brr settings in clocked synchronous mode.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 639 of 1220 rej09b0186-0300o table 16.3 brr settings for various bit rates (asynchronous mode) = 2 mhz = 2.097152 mhz = 2.4576 mhz = 3 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 141 0.03 1 148 ? 0.04 1 174 ? 0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 ? 0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 ? 2.48 0 15 0.00 0 19 ? 2.34 9600 ??? 06 ? 2.48 0 7 0.00 0 9 ? 2.34 19200 ?????? 0 3 0.00 0 4 ? 2.34 31250 0 1 0.00 ?????? 0 2 0.00 38400 ?????? 0 1 0.00 ??? = 3.6864 mhz = 4 mhz = 4.9152 mhz = 5 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 ? 0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ? 1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 ??? 0 7 0.00 0 7 1.73 31250 ??? 030.0004 ? 1.70 0 4 0.00 38400 0 2 0.00 ??? 0 3 0.00 0 3 1.73
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 640 of 1220 rej09b0186-0300o = 6 mhz = 6.144 mhz = 7.3728 mhz = 8 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 106 ? 0.44 2 108 0.08 2 130 ? 0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 ? 2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 ? 2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 ??? 0 7 0.00 38400 0 4 ? 2.34 0 4 0.00 0 5 0.00 ??? = 9.8304 mhz = 10 mhz = 12 mhz = 12.288 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 174 ? 0.26 2 177 ? 0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 ? 1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 ? 2.34 0 19 0.00 31250 0 9 ? 1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 ? 2.34 0 9 0.00
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 641 of 1220 rej09b0186-0300o = 14 mhz = 14.7456 mhz = 16 mhz = 17.2032 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 248 ? 0.17 3 64 0.70 3 70 0.03 3 75 0.48 150 2 181 0.16 2 191 0.00 2 207 0.16 2 223 0.00 300 2 90 0.16 2 95 0.00 2 103 0.16 2 111 0.00 600 1 181 0.16 1 191 0.00 1 207 0.16 1 223 0.00 1200 1 90 0.16 1 95 0.00 1 103 0.16 1 111 0.00 2400 0 181 0.16 0 191 0.00 0 207 0.16 0 223 0.00 4800 0 90 0.16 0 95 0.00 0 103 0.16 0 111 0.00 9600 0 45 ? 0.93 0 47 0.00 0 51 0.16 0 55 0.00 19200 0 22 ? 0.93 0 23 0.00 0 25 0.16 0 27 0.00 31250 0 13 0.00 0 14 ? 1.70 0 15 0.00 0 16 1.20 38400 ??? 0 11 0.00 0 12 0.13 0 13 0.00 = 18 mhz = 19.6608 mhz = 20 mhz = 25 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 3 79 ? 0.12 3 86 0.31 3 88 ? 0.25 3 110 ? 0.02 150 2 233 0.16 2 255 0.00 3 64 0.16 3 80 ? 0.47 300 2 116 0.16 2 127 0.00 2 129 0.16 2 162 0.15 600 1 233 0.16 1 255 0.00 2 64 0.16 2 80 ? 0.47 1200 1 116 0.16 1 127 0.00 1 129 0.16 1 162 0.15 2400 0 233 0.16 0 255 0.00 1 64 0.16 1 80 ? 0.47 4800 0 116 0.16 0 127 0.00 0 129 0.16 0 162 0.15 9600 0 58 ? 0.69 0 63 0.00 0 64 0.16 0 80 ? 0.47 19200 0 28 1.02 0 31 0.00 0 32 ? 1.36 0 40 ? 0.76 31250 0 17 0.00 0 19 ? 1.70 0 19 0.00 0 24 0.00 38400 0 14 ? 2.34 0 15 0.00 0 15 1.73 0 19 1.73
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 642 of 1220 rej09b0186-0300o table 16.4 brr settings for various bit rates (clocked synchronous mode) bit rate = 2 mhz = 4 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz = 25 mhz (bit/s) n n n n n n n n n n n n n n 110 3 70 ?? 250 2 124 2 249 3 124 ?? 3249 500 1 249 2 124 2 249 ?? 3124 ?? 1 k 1 124 1 249 2 124 ?? 2249 ?? 397 2.5 k 0 199 1 99 1 199 1 249 2 99 2 124 2 155 5 k 0 99 0 199 1 99 1 124 1 199 1 249 2 77 10 k 0 49 0 99 0 199 0 249 1 99 1 124 1 155 25 k 0 19 0 39 0 79 0 99 0 159 0 199 0 249 50 k 0 9 0 19 0 39 0 49 0 79 0 99 0 124 100 k 0 4 0 9 0 19 0 24 0 39 0 49 0 62 250 k 0 1 0 3 0 7 0 9 0 15 0 19 0 24 500 k 0 0 * 01 03 04 07 09 ?? 1 m 0 0 * 01 03 04 ?? 2.5 m 0 0 * 01 ?? 5 m 00 * ?? note: as far as possible, the setting should be made so that the error is no more than 1%. legend: blank: cannot be set. ? : can be set, but there will be a degree of error. * : continuous transfer is not possible.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 643 of 1220 rej09b0186-0300o the brr setting is found from the following formulas. asynchronous mode: n = 64 2 2n ? 1 b 10 6 ? 1 clocked synchronous mode: n = 8 2 2n ? 1 b 10 6 ? 1 where b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) : operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the table below for the relation between n and the clock.) smr setting n clock cks1 cks0 0 00 1 /4 0 1 2 /16 1 0 3 /64 1 1 the bit rate error in asynchronous mode is found from the following formula: error (%) = { 10 6 (n + 1) b 64 2 2n ? 1 ? 1 } 100
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 644 of 1220 rej09b0186-0300o table 16.5 shows the maximum bit rate for each frequency in asynchronous mode. tables 16.6 and 16.7 show the maximum bit rates with external clock input. table 16.5 maximum bit rate for each frequency (asynchronous mode) (mhz) maximum bit rate (bit/s) n n 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 19.6608 614400 0 0 20 625000 0 0 25 781250 0 0
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 645 of 1220 rej09b0186-0300o table 16.6 maximum bit rate with external clock input (asynchronous mode) (mhz) external input clock (mhz) maximum bit rate (bit/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 19.6608 4.9152 307200 20 5.0000 312500 25 6.2500 390625
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 646 of 1220 rej09b0186-0300o table 16.7 maximum bit rate with external clock input (clocked synchronous mode) (mhz) external input clock (mhz) maximum bit rate (bit/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 25 4.1667 4166666.7
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 647 of 1220 rej09b0186-0300o 16.2.9 smart card mode register (scmr) 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 ? 1 ? bit initial value r/w : : : scmr selects lsb-first or msb-first by means of bit sdir. except in the case of asynchronous mode 7-bit data, lsb-first or msb-first can be selected regardless of the serial communication mode. the descriptions in this chapter refer to lsb-first transfer. for details of the other bits in scmr, see section 17.2.1, smart card mode register (scmr). scmr is initialized to h'f2 by a reset and in standby mode. bits 7 to 4?reserved: these bits are always read as 1 and cannot be modified. bit 3?smart card data transfer direction (sdir): selects the serial/parallel conversion format. this bit is valid when 8-bit data is used as the transmit/receive format. bit 3 sdir description 0 tdr contents are transmitted lsb-first (initial value) receive data is stored in rdr lsb-first 1 tdr contents are transmitted msb-first receive data is stored in rdr msb-first
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 648 of 1220 rej09b0186-0300o bit 2?smart card data invert (sinv): specifies inversion of the data logic level. the sinv bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the o/ e bit in smr. bit 2 sinv description 0 tdr contents are transmitted without modification (initial value) receive data is stored in rdr without modification 1 tdr contents are inverted before being transmitted receive data is stored in rdr in inverted form bit 1?reserved: this bit is always read as 1 and cannot be modified. bit 0?smart card interface mode select (smif): when the smart card interface operates as a normal sci, 0 should be written in this bit. bit 0 smif description 0 operates as normal sci (smart card interface function disabled) (initial value) 1 smart card interface function enabled 16.2.10 irda control register (ircr) bit:76543210 ire ircks2 ircks1 ircks0 ???? initial value:00000000 r/w : r/w r/w r/w r/w ???? ircr is an 8-bit read/write register that selects the sci0 function. ircr is initialized to h'00 when in hardware standby mode.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 649 of 1220 rej09b0186-0300o bit 7?irda enable (ire): sets sci0 input and output for normal sci operation or irda operation. bit 7 ire description 0 txd0/irtxd and rxd0/irrxd pins operate as txd0 and rxd0 (initial value) 1 txd0/irtxd and rxd0/irrxd pins operate as irtxd and irrxd bits 6 to 4?irda clock select 2 to 0 (ircks2 to ircks0): when the irda function is enabled, these bits set the width of the high pulse when encoding the irtxd output pulse. bit 6 bit 5 bit 4 ircks2 ircks1 ircks0 description 000b 3/16 (three sixteenths of bit rate) (initial value) 1 /2 10 /4 1 /8 100 /16 1 /32 10 /64 1 /128 bits 3 to 0?reserved: these bits are always read as 0 and cannot be modified.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 650 of 1220 rej09b0186-0300o 16.2.11 module stop control registers b and c (mstpcrb, mstpcrc) 7 mstpb7 1 r/w 6 mstpb6 1 r/w 5 mstpb5 1 r/w 4 mstpb4 1 r/w 3 mstpb3 1 r/w 0 mstpb0 1 r/w 2 mstpb2 1 r/w 1 mstpb1 1 r/w bit initial value r/w : : : mstpcrb 7 mstpc7 1 r/w 6 mstpc6 1 r/w 5 mstpc5 1 r/w 4 mstpc4 1 r/w 3 mstpc3 1 r/w 0 mstpc0 1 r/w 2 mstpc2 1 r/w 1 mstpc1 1 r/w bit initial value r/w : : : mstpcrc mstpcrb and mstpcrc are 8-bit readable/writable registers that perform module stop mode control. setting any of bits mstpb7 to mstbp5 and mstpc7 and mstpc6 to 1 stops sci0 to sci4 operating and enter module stop mode on completion of the bus cycle. for details, see section 24.5, module stop mode. mstpcrb and mstpcrc are initialized to h'ff by a reset and in hardware standby mode. they are not initialized by a manual reset and in software standby mode. (1) module stop control register b (mstpcrb) bit 7?module stop (mstpb7): specifies the sci0 module stop mode. bit 7 mstpb7 description 0 sci0 module stop mode is cleared 1 sci0 module stop mode is set (initial value)
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 651 of 1220 rej09b0186-0300o bit 6?module stop (mstpb6): specifies the sci1 module stop mode. bit 6 mstpb6 description 0 sci1 module stop mode is cleared 1 sci1 module stop mode is set (initial value) bit 5?module stop (mstpb5): specifies the sci2 module stop mode. bit 5 mstpb5 description 0 sci2 module stop mode is cleared 1 sci2 module stop mode is set (initial value) (2) module stop control register c (mstpcrc) bit 7?module stop (mstpc7): specifies the sci3 module stop mode. bit 7 mstpc7 description 0 sci3 module stop mode is cleared 1 sci3 module stop mode is set (initial value) bit 6?module stop (mstpc6): specifies the sci4 module stop mode. bit 6 mstpc6 description 0 sci4 module stop mode is cleared 1 sci4 module stop mode is set (initial value)
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 652 of 1220 rej09b0186-0300o 16.3 operation 16.3.1 overview the sci can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and clocked synchronous mode in which synchronization is achieved with clock pulses. selection of asynchronous or clocked synchronous mode and the transmission format is made using smr as shown in table 16.8. the sci clock is determined by a combination of the c/ a bit in smr and the cke1 and cke0 bits in scr, as shown in table 16.9. (1) asynchronous mode ? data length: choice of 7 or 8 bits ? choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) ? detection of framing, parity, and overrun errors, and breaks, during reception ? choice of internal or external clock as sci clock source ? when internal clock is selected: the sci operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output ? when external clock is selected: a clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used) (2) clocked synchronous mode ? transfer format: fixed 8-bit data ? detection of overrun errors during reception ? choice of internal or external clock as sci clock source ? when internal clock is selected: the sci operates on the baud rate generator clock and a serial clock is output off-chip ? when external clock is selected: the on-chip baud rate generator is not used, and the sci operates on the input serial clock
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 653 of 1220 rej09b0186-0300o table 16.8 smr settings and serial transfer format selection smr settings sci transfer format bit 7 bit 6 bit 2 bit 5 bit 3 c/ a chr mp pe stop mode data length multi processor bit parity bit stop bit length 0 0 0 0 0 8-bit data no no 1 bit 1 2 bits 10 yes1 bit 1 2 bits 1 0 0 7-bit data no 1 bit 1 2 bits 10 yes1 bit 1 asynchronous mode 2 bits 01 ? 0 8-bit data yes no 1 bit ? 1 2 bits 1 ? 0 7-bit data 1 bit ? 1 asynchronous mode (multi- processor format) 2 bits 1 ???? clocked synchronous mode 8-bit data no none table 16.9 smr and scr settings and sci clock source selection smr scr setting sci transmit/receive clock bit 7 bit 1 bit 0 c/ a cke1 cke0 mode clock source sck pin function 0 0 0 internal sci does not use sck pin 1 outputs clock with same frequency as bit rate 1 0 external 1 asynchronous mode inputs clock with frequency of 16 times the bit rate 1 0 0 internal outputs serial clock 1 1 0 external inputs serial clock 1 clocked synchronous mode
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 654 of 1220 rej09b0186-0300o 16.3.2 operation in asynchronous mode in asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and stop bits indicating the end of communication. serial communication is thus carried out with synchronization established on a character-by-character basis. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication. both the transmitter and the r eceiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. figure 16.2 shows the general format for asynchronous serial communication. in asynchronous serial communication, the transmission line is usually held in the mark state (high level). the sci monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. one serial communication character consists of a start bit (low level), followed by data (in lsb- first order), a parity bit (high or low level), and finally stop bits (high level). in asynchronous mode, the sci performs synchronization at the fa lling edge of the start bit in reception. the sci samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. lsb start bit msb idle state (mark state) stop bit 0 transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 1 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit or none one unit of transfer data (character or frame) figure 16.2 data format in asynchronous communication (example with 8-bit data, parity, two stop bits)
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 655 of 1220 rej09b0186-0300o (1) data transfer format table 16.10 shows the data transfer formats that can be used in asynchronous mode. any of 12 transfer formats can be selected according to the smr setting. table 16.10 serial transfer formats (asynchronous mode) pe 0 0 1 1 0 0 1 1 ? ? ? ? s 8-bit data stop s 7-bit data stop s 8-bit data stop stop s 8-bit data p stop s 7-bit data stop p s 8-bit data mpb stop s 8-bit data mpb stop stop s 7-bit data stop mpb s 7-bit data stop mpb stop s 7-bit data stop stop chr 0 0 0 0 1 1 1 1 0 0 1 1 mp 0 0 0 0 0 0 0 0 1 1 1 1 stop 0 1 0 1 0 1 0 1 0 1 0 1 smr settings 123456789101112 serial transfer format and frame length stop s 8-bit data p stop s 7-bit data stop p stop legend: s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 656 of 1220 rej09b0186-0300o (2) clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck pin can be selected as the sci ? s serial clock, according to the setting of the c/ a bit in smr and the cke1 and cke0 bits in scr. for details of sci clock source selection, see table 16.9. when an external clock is input at the sck pin, the clock frequency should be 16 times the bit rate used. when the sci is operated on an internal clock, the clock can be output from the sck pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 16.3. 0 1 frame d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 figure 16.3 relation between output clock and transfer data phase (asynchronous mode) (3) data transfer operation ? sci initialization (asynchronous mode) before transmitting and receiving data, you should first clear the te and re bits in scr to 0, then initialize the sci as described below. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and tsr is initialized. note that clearing the re bit to 0 does not change the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. when an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 657 of 1220 rej09b0186-0300o figure 16.4 shows a sample sci initialization flowchart. wait start initialization set data transfer format in smr and scmr [1] set cke1 and cke0 bits in scr (te, re bits 0) no yes set value in brr clear te and re bits in scr to 0 [2] [3] set te and re bits in scr to 1, and set rie, tie, teie, and mpie bits [4] 1-bit interval elapsed? [1] set the clock selection in scr. be sure to clear bits rie, tie, teie, and mpie, and bits te and re, to 0. when the clock is selected in asynchronous mode, it is output immediately after scr settings are made. [2] set the data transfer format in smr and scmr. [3] write a value corresponding to the bit rate to brr. not necessary if an external clock is used. [4] wait at least one bit interval, then set the te bit or re bit in scr to 1. also set the rie, tie, teie, and mpie bits. setting the te and re bits enables the txd and rxd pins to be used. figure 16.4 sample sci initialization flowchart ? serial data transmission (asynchronous mode) figure 16.5 shows a sample flowchart for serial transmission. the following procedure should be used for serial data transmission.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 658 of 1220 rej09b0186-0300o no [1] yes initialization start transmission read tdre flag in ssr [2] write transmit data to tdr and clear tdre flag in ssr to 0 no yes no yes read tend flag in ssr [3] no yes [4] clear dr to 0 and set ddr to 1 clear te bit in scr to 0 tdre = 1 all data transmitted? tend = 1 break output? [1] sci initialization: the txd pin is automatically designated as the transmit data output pin. after the te bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. [3] serial transmission continuation procedure: to continue serial transmission, read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. checking and clearing of the tdre flag is automatic when the dmac or dtc is activated by a transmit data empty interrupt (txi) request, and date is written to tdr. [4] break output at the end of serial transmission: to output a break in serial transmission, set ddr for the port corresponding to the txd pin to 1, clear dr to 0, then clear the te bit in scr to 0. figure 16.5 sample serial transmission flowchart
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 659 of 1220 rej09b0186-0300o in serial transmission, the sci operates as described below. [1] the sci monitors the tdre flag in ssr, and if is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. [2] after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit data empty interrupt (txi) is generated. the serial transmit data is sent from the txd pin in the following order. [a] start bit: one 0-bit is output. [b] transmit data: 8-bit or 7-bit data is output in lsb-first order. [c] parity bit or multiprocessor bit: one parity bit (even or odd parity), or one multiprocessor bit is output. a format in which neither a parity bit nor a multiprocessor bit is output can also be selected. [d] stop bit(s): one or two 1-bits (stop bits) are output. [e] mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] the sci checks the tdre flag at the timing for sending the stop bit. if the tdre flag is cleared to 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the ? mark state ? is entered in which 1 is output continuously. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 660 of 1220 rej09b0186-0300o figure 16.6 shows an example of the operation for transmission in asynchronous mode. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt service routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 16.6 example of operation in transmission in asynchronous mode (example with 8-bit data, parity, one stop bit)
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 661 of 1220 rej09b0186-0300o ? serial data reception (asynchronous mode) figure 16.7 shows a sample flowchart for serial reception. the following procedure should be used for serial data reception. yes [1] no initialization start reception [2] no yes read rdrf flag in ssr [4] [5] clear re bit in scr to 0 read orer, per, and fer flags in ssr error processing (continued on next page) [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes per ? fer ? orer = 1 rdrf = 1 all data received? sci initialization: the rxd pin is automatically designated as the receive data input pin. receive error processing and break detection: if a receive error occurs, read the orer, per, and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the orer, per, and fer flags are all cleared to 0. reception cannot be resumed if any of these flags are set to 1. in the case of a framing error, a break can be detected by reading the value of the input port corresponding to the rxd pin. sci status check and receive data read : read ssr and check that rdrf = 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. serial reception continuation procedure: to continue serial reception, before the stop bit for the current frame is received, read the rdrf flag, read rdr, and clear the rdrf flag to 0. the rdrf flag is cleared automatically when dmac or dtc is activated by an rxi interrupt and the rdr value is read. [1] [2] [3] [4] [5] figure 16.7 sample serial reception data flowchart (1)
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 662 of 1220 rej09b0186-0300o [3] error processing parity error processing yes no clear orer, per, and fer flags in ssr to 0 no yes no yes framing error processing no yes overrun error processing orer = 1 fer = 1 break? per = 1 clear re bit in scr to 0 figure 16.7 sample serial reception data flowchart (2)
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 663 of 1220 rej09b0186-0300o in serial reception, the sci operates as described below. [1] the sci monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] the received data is stored in rsr in lsb-to-msb order. [3] the parity bit and stop bit are received. after receiving these bits, the sci carries out the following checks. [a] parity check: the sci checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the o/ e bit in smr. [b] stop bit check: the sci checks whether the stop bit is 1. if there are two stop bits, only the first is checked. [c] status check: the sci checks whether the rdrf flag is 0, indicating that the receive data can be transferred from rsr to rdr. if all the above checks are passed, the rdrf flag is set to 1, and the receive data is stored in rdr. if a receive error* is detected in the error check, the operation is as shown in table 16.11. note: * subsequent receive operations cannot be performed when a receive error has occurred. also note that the rdrf flag is not set to 1 in reception, and so the error flags must be cleared to 0. [4] if the rie bit in scr is set to 1 when the rdrf flag changes to 1, a receive data full interrupt (rxi) request is generated. also, if the rie bit in scr is set to 1 when the orer, per, or fer flag changes to 1, a receive error interrupt (eri) request is generated.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 664 of 1220 rej09b0186-0300o table 16.11 receive errors and conditions for occurrence receive error abbreviation occurrence condition data transfer overrun error orer when the next data reception is completed while the rdrf flag in ssr is set to 1 receive data is not transferred from rsr to rdr framing error fer when the stop bit is 0 receive data is transferred from rsr to rdr parity error per when the received data differs from the parity (even or odd) set in smr receive data is transferred from rsr to rdr figure 16.8 shows an example of the operation for reception in asynchronous mode. rdrf fer 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 0 1 1 data start bit parity bit stop bit start bit data parity bit stop bit rxi interrupt request generated eri interrupt request generated by framing error idle state (mark state) rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine figure 16.8 example of sci operation in reception (example with 8-bit data, parity, one stop bit)
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 665 of 1220 rej09b0186-0300o 16.3.3 multiprocessor communication function the multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. use of this function enables data transfer to be performed among a number of processors sharing transmission lines. when multiprocessor communication is carried out, each receiving station is addressed by a unique id code. the serial communication cycle consists of two component cycles: an id transmission cycle which specifies the receiving station , and a data transmission cycle. the multiprocessor bit is used to differentiate between the id transmission cycle and the data transmission cycle. the transmitting station first sends the id of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. the receiving station skips the data until data with a 1 multiprocessor bit is sent. when data with a 1 multiprocessor bit is received, the receiving station compares that data with its own id. the station whose id matches then receives the data sent next. stations whose id does not match continue to skip the data until data with a 1 multiprocessor bit is again received. in this way, data communication is carried out among a number of processors. figure 16.9 shows an example of inter-processor communication using the multiprocessor format. (1) data transfer format there are four data transfer formats. when the multiprocessor format is specified, the parity bit specification is invalid. for details, see table 16.10.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 666 of 1220 rej09b0186-0300o (2) clock see the section on asynchronous mode. transmitting station receiving station a (id = 01) receiving station b (id = 02) receiving station c (id = 03) receiving station d (id = 04) serial transmission line serial data id transmission cycle = receiving station specification data transmission cycle = data transmission to receiving station specified by id (mpb = 1) (mpb = 0) h'01 h'aa legend: mpb: multiprocessor bit figure 16.9 example of inter-processor communication using multiprocessor format (transmission of data h'aa to receiving station a) (3) data transfer operations ? multiprocessor serial data transmission figure 16.10 shows a sample flowchart for multiprocessor serial data transmission. the following procedure should be used for multiprocessor serial data transmission.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 667 of 1220 rej09b0186-0300o no [1] yes initialization start transmission read tdre flag in ssr [2] write transmit data to tdr and set mpbt bit in ssr no yes no yes read tend flag in ssr [3] no yes [4] clear dr to 0 and set ddr to 1 clear te bit in scr to 0 tdre = 1 all data transmitted? tend = 1 break output? clear tdre flag to 0 sci initialization: the txd pin is automatically designated as the transmit data output pin. after the te bit is set to 1, a frame of 1s is output, and transmission is enabled. sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. set the mpbt bit in ssr to 0 or 1. finally, clear the tdre flag to 0. serial transmission continuation procedure: to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. checking and clearing of the tdre flag is automatic when the dmac or dtc is activated by a transmit data empty interrupt (txi) request, and data is written to tdr. break output at the end of serial transmission: to output a break in serial transmission, set the port ddr to 1, clear dr to 0, then clear the te bit in scr to 0. [1] [2] [3] [4] figure 16.10 sample multiprocessor serial transmission flowchart
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 668 of 1220 rej09b0186-0300o in serial transmission, the sci operates as described below. [1] the sci monitors the tdre flag in ssr, and if is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. [2] after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a transmit data empty interrupt (txi) is generated. the serial transmit data is sent from the txd pin in the following order. [a] start bit: one 0-bit is output. [b] transmit data: 8-bit or 7-bit data is output in lsb-first order. [c] multiprocessor bit one multiprocessor bit (mpbt value) is output. [d] stop bit(s): one or two 1-bits (stop bits) are output. [e] mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] the sci checks the tdre flag at the timing for sending the stop bit. if the tdre flag is cleared to 0, data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. if the teie bit in scr is set to 1 at this time, a transmission end interrupt (tei) request is generated.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 669 of 1220 rej09b0186-0300o figure 16.11 shows an example of sci operation for transmission using the multiprocessor format. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit multi- proce- ssor bit stop bit start bit data multi- proces- sor bit stop bit txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt service routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 16.11 example of sci operation in transmission (example with 8-bit data, multiprocessor bit, one stop bit) ? multiprocessor serial data reception figure 16.12 shows a sample flowchart for multiprocessor serial reception. the following procedure should be used for multiprocessor serial data reception.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 670 of 1220 rej09b0186-0300o yes [1] no initialization start reception no yes [4] clear re bit in scr to 0 error processing (continued on next page) [5] no yes fer ? orer = 1 rdrf = 1 all data received? read mpie bit in scr [2] read orer and fer flags in ssr read rdrf flag in ssr [3] read receive data in rdr no yes this station ? s id? read orer and fer flags in ssr yes no read rdrf flag in ssr no yes fer ? orer = 1 read receive data in rdr rdrf = 1 sci initialization: the rxd pin is automatically designated as the receive data input pin. id reception cycle: set the mpie bit in scr to 1. sci status check, id reception and comparison: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and compare it with this station ? s id. if the data is not this station ? s id, set the mpie bit to 1 again, and clear the rdrf flag to 0. if the data is this station ? s id, clear the rdrf flag to 0. sci status check and data reception: read ssr and check that the rdrf flag is set to 1, then read the data in rdr. receive error processing and break detection: if a receive error occurs, read the orer and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the orer and fer flags are all cleared to 0. reception cannot be resumed if either of these flags is set to 1. in the case of a framing error, a break can be detected by reading the rxd pin value. [1] [2] [3] [4] [5] figure 16.12 sample multiprocessor serial reception flowchart (1)
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 671 of 1220 rej09b0186-0300o error processing yes no clear orer, per, and fer flags in ssr to 0 no yes no yes framing error processing overrun error processing orer = 1 fer = 1 break? clear re bit in scr to 0 [5] figure 16.12 sample multiprocessor serial reception flowchart (2)
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 672 of 1220 rej09b0186-0300o figure 16.13 shows an example of sci operation for multiprocessor format reception. mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 data (id1) start bit mpb stop bit start bit data (data1) mpb stop bit rxi interrupt request (multiprocessor interrupt) generated mpie = 0 idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine if not this station ? s id, mpie bit is set to 1 again rxi interrupt request is not generated, and rdr retains its state id1 (a) data does not match station ? s id mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 data (id2) start bit mpb stop bit start bit data (data2) mpb stop bit rxi interrupt request (multiprocessor interrupt) generated mpie = 0 idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine matches this station ? s id, so reception continues, and data is received in rxi interrupt service routine mpie bit set to 1 again id2 (b) data matches station ? s id data2 id1 figure 16.13 example of sci operation in reception (example with 8-bit data, multiprocessor bit, one stop bit)
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 673 of 1220 rej09b0186-0300o 16.3.4 operation in clocked synchronous mode in clocked synchronous mode, data is trans mitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. figure 16.14 shows the general format for clocked synchronous serial communication. don ? t car e don ? t care one unit of transfer data (character or frame) bit 0 serial data serial clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * note: * high except in continuous transfer * figure 16.14 data format in synchronous communication in clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. data confirmation is guaranteed at the rising edge of the serial clock. in clocked serial communication, one character consists of data output starting with the lsb and ending with the msb. after the msb is output, the transmission line holds the msb state. in clocked synchronous mode, the sci receives data in synchronization with the rising edge of the serial clock. (1) data transfer format a fixed 8-bit data format is used. no parity or multiprocessor bits are added.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 674 of 1220 rej09b0186-0300o (2) clock either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the sck pin can be selected, according to the setting of the c/ a bit in smr and the cke1 and cke0 bits in scr. for details of sci clock source selection, see table 16.9. when the sci is operated on an internal clock, the serial clock is output from the sck pin. eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. when only receive operations are performed, however, the serial clock is output until an overrun error occurs or the re bit is cleared to 0. if you want to perform receive operations in units of one character, you should select an external clock as the clock source.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 675 of 1220 rej09b0186-0300o (3) data transfer operations ? sci initialization (clocked synchronous mode) before transmitting and receiving data, you should first clear the te and re bits in scr to 0, then initialize the sci as described below. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and tsr is initialized. note that clearing the re bit to 0 does not change the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. figure 16.15 shows a sample sci initialization flowchart. wait note: in simultaneous transmit and receive operations, the te and re bits should both be cleared to 0 or set to 1 simultaneously. start initialization set data transfer format in smr and scmr no yes set value in brr clear te and re bits in scr to 0 [2] [3] set te and re bits in scr to 1, and set rie, tie, teie, and mpie bits [4] 1-bit interval elapsed? [1] [1] set the clock selection in scr. be sure to clear bits rie, tie, teie, and mpie, te and re, to 0. [2] set the data transfer format in smr and scmr. [3] write a value corresponding to the bit rate to brr. not necessary if an external clock is used. [4] wait at least one bit interval, then set the te bit or re bit in scr to 1. also set the rie, tie, teie, and mpie bits. setting the te and re bits enables the txd and rxd pins to be used. set cke1 and cke0 bits in scr (te, re bits 0) figure 16.15 sample sci initialization flowchart
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 676 of 1220 rej09b0186-0300o ? serial data transmission (clocked synchronous mode) figure 16.16 shows a sample flowchart for serial transmission. the following procedure should be used for serial data transmission. no [1] yes initialization start transmission read tdre flag in ssr [2] write transmit data to tdr and clear tdre flag in ssr to 0 no yes no yes read tend flag in ssr [3] clear te bit in scr to 0 tdre = 1 all data transmitted? tend = 1 [1] sci initialization: the txd pin is automatically designated as the transmit data output pin. [2] sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. [3] serial transmission continuation procedure: to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. checking and clearing of the tdre flag is automatic when the dmac or dtc is activated by a transmit data empty interrupt (txi) request and data is written to tdr. figure 16.16 sample serial transmission flowchart
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 677 of 1220 rej09b0186-0300o in serial transmission, the sci operates as described below. [1] the sci monitors the tdre flag in ssr, and if is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. [2] after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a transmit data empty interrupt (txi) is generated. when clock output mode has been set, the sci outputs 8 serial clock pulses. when use of an external clock has been specified, data is output synchronized with the input clock. the serial transmit data is sent from the txd pin starting with the lsb (bit 0) and ending with the msb (bit 7). [3] the sci checks the tdre flag at the timing for sending the msb (bit 7). if the tdre flag is cleared to 0, data is transferred from tdr to tsr, and serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the msb (bit 7) is sent, and the txd pin maintains its state. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. [4] after completion of serial transmission, the sck pin is fixed high. figure 16.17 shows an example of sci operation in transmission. transfer direction bit 0 serial data serial clock 1 frame tdre tend bit 1 bit 7 bit 0 bit 1 bit 7 bit 6 data written to tdr and tdre flag cleared to 0 in txi interrupt service routine tei interrupt request generated txi interrupt request generated txi interrupt request generated figure 16.17 example of sci operation in transmission
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 678 of 1220 rej09b0186-0300o ? serial data reception (clocked synchronous mode) figure 16.18 shows a sample flowchart for serial reception. the following procedure should be used for serial data reception. when changing the operating mode from asynchronous to clocked synchronous, be sure to check that the orer, per, and fer flags are all cleared to 0. the rdrf flag will not be set if the fer or per flag is set to 1, and neither transmit nor receive operations will be possible.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 679 of 1220 rej09b0186-0300o yes [1] no initialization start reception [2] no yes read rdrf flag in ssr [4] [5] clear re bit in scr to 0 error processing (continued below) [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes orer = 1 rdrf = 1 all data received? read orer flag in ssr [1] [2] [3] [4] [5] sci initialization: the rxd pin is automatically designated as the receive data input pin. receive error processing: if a receive error occurs, read the orer flag in ssr , and after performing the appropriate error processing, clear the orer flag to 0. transfer cannot be resumed if the orer flag is set to 1. sci status check and receive data read: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. serial reception continuation procedure: to continue serial reception, before the msb (bit 7) of the current frame is received, finish reading the rdrf flag, reading rdr, and clearing the rdrf flag to 0. the rdrf flag is cleared automatically when the dmac or dtc is activated by a receive data full interrupt (rxi) request and the rdr value is read. error processing overrun error processing [3] clear orer flag in ssr to 0 figure 16.18 sample serial reception flowchart
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 680 of 1220 rej09b0186-0300o in serial reception, the sci operates as described below. [1] the sci performs internal initialization in synchronization with serial clock input or output. [2] the received data is stored in rsr in lsb-to-msb order. after reception, the sci checks whether the rdrf flag is 0 and the receive data can be transferred from rsr to rdr. if this check is passed, the rdrf flag is set to 1, and the receive data is stored in rdr. if a receive error is detected in the error check, the operation is as shown in table 16.11. neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. [3] if the rie bit in scr is set to 1 when the rdrf flag changes to 1, a receive data full interrupt (rxi) request is generated. also, if the rie bit in scr is set to 1 when the orer flag changes to 1, a receive error interrupt (eri) request is generated. figure 16.19 shows an example of sci operation in reception. bit 7 serial data serial clock 1 frame rdrf orer bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 rxi interrupt request generated rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine rxi interrupt request generated eri interrupt request generated by overrun error figure 16.19 example of sci operation in reception ? simultaneous serial data transmission and reception (clocked synchronous mode) figure 16.20 shows a sample flowchart for simultaneous serial transmit and receive operations. the following procedure should be used for simultaneous serial data transmit and receive operations.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 681 of 1220 rej09b0186-0300o yes [1] no initialization start transmission/reception [5] error processing [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes orer = 1 all data received? [2] read tdre flag in ssr no yes tdre = 1 write transmit data to tdr and clear tdre flag in ssr to 0 no yes rdrf = 1 read orer flag in ssr [4] read rdrf flag in ssr clear te and re bits in scr to 0 note: when switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the te bit and re bit to 0, then set both these bits to 1 simultaneously. [1] [2] [3] [4] [5] sci initialization: the txd pin is designated as the transmit data output pin, and the rxd pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. transition of the tdre flag from 0 to 1 can also be identified by a txi interrupt. receive error processing: if a receive error occurs, read the orer flag in ssr , and after performing the appropriate error processing, clear the orer flag to 0. transmission/reception cannot be resumed if the orer flag is set to 1. sci status check and receive data read: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. serial transmission/reception continuation procedure: to continue serial transmission/ reception, before the msb (bit 7) of the current frame is received, finish reading the rdrf flag, reading rdr, and clearing the rdrf flag to 0. also, before the msb (bit 7) of the current frame is transmitted, read 1 from the tdre flag to confirm that writing is possible. then write data to tdr and clear the tdre flag to 0. checking and clearing of the tdre flag is automatic when the dtc is activated by a transmit data empty interrupt (txi) request and data is written to tdr. also, the rdrf flag is cleared automatically when the dmac or dtc is activated by a receive data full interrupt (rxi) request and the rdr value is read. figure 16.20 sample flowchart of simultaneous serial transmit and receive operations
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 682 of 1220 rej09b0186-0300o 16.3.5 irda operation figure 16.21 is a block diagram of the irda. when the ire bit of ircr is set to enable the irda function, the txd0/rxd0 signals of sci channel 0 are encoded and decoded with waveforms conforming to the irda standard version 1.0 (irtxd/irrxd pins). connecting these to an infrared transmitter/receiver allows the realization of infrared transmission and reception conforming to an irda standard version 1.0 system. in an irda standard version 1.0 system, communication is initiated at a transfer rate of 9600 bps. the rate is subsequently varied as required. the irda interface of this lsi does not have an internal function for automatically varying the transfer rate. the transfer rate must be varied using software. irda pulse encoder pulse decoder ircr txd0/irtxd rxd0/irrxd sci0 txd rxd figure 16.21 irda block diagram (1) transmission when transmitting, the signal (uart frame) output from the sci is converted by the irda interface into an ir frame (see figure 16.22). when the value of the serial data is ? 0 ? , a high pulse that has 3/16ths the width of the bit rate (the duration of 1 bit width) is output (default). note that the high pulse can also be changed by altering the settings of ircr ircks2 to ircks0.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 683 of 1220 rej09b0186-0300o as per the standard, the high pulse width is a minimum of 1.41 s, the maximum is (3/16 + 2.5%) bit rate, or (3/16 bit rate) + 1.08 s. with a 20 mhz system clock , the minimum high pulse width can be set to 1.6 s, which is greater than the 1.41 s required by the standard. when the value of the serial data is ? 1 ? , no pulse is output. uart frame data ir frame data 0000 0 11 111 0000 0 11 111 start bit transmitting receiving start bit start bit start bit bit c y cle pulse width = 1.6 s to 3/16ths bit c y cle figure 16.22 irda transmit and receive operations (2) receiving when receiving, the ir frame data is converted into uart frames by the irda interface and input to the sci. when a high pulse is detected, ? 0 ? is output. if there is no pulse for the duration of 1 bit, ? 1 ? is output. pulses of less than the minimum pulse width of 1.41 s are also recognized as ? 0 ? data. (3) selecting high pulse width table 16.12 shows the settings of ircks2 to ircks0 (for the minimum pulse width), at various lsi operating frequencies, and various bit rates to set the pulse width when transmitting with a pulse width less than 3/16ths of the bit rate.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 684 of 1220 rej09b0186-0300o table 16.12 setting bits ircks2 to ircks0 bit rate (bps) (upper row) / bit cycle 3/16 (s) (lower row) 2400 9600 19200 38400 57600 115200 operating frequency (mhz) 78.13 19.53 9.77 4.88 3.26 1.63 2 010 010 010 010 010 ? 2.097152 010 010 010 010 010 ? 2.4576 010 010 010 010 010 ? 3 011 011 011 011 011 ? 3.6864 011 011 011 011 011 011 4.9152 011 011 011 011 011 011 5 011 011 011 011 011 011 6 100 100 100 100 100 100 6.144 100 100 100 100 100 100 7.3728 100 100 100 100 100 100 8 100 100 100 100 100 100 9.8304 100 100 100 100 100 100 10 100 100 100 100 100 100 12 101 101 101 101 101 101 12.288 101 101 101 101 101 101 14 101 101 101 101 101 101 14.7456 101 101 101 101 101 101 16 101 101 101 101 101 101 16.9344 101 101 101 101 101 101 17.2032 101 101 101 101 101 101 18 101 101 101 101 101 101 19.6608 101 101 101 101 101 101 20 101 101 101 101 101 101 25 110 110 110 110 110 110 legend: ? : sci cannot be set to this bit rate.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 685 of 1220 rej09b0186-0300o 16.4 sci interrupts the sci has four interrupt sources: the transmit-end interrupt (tei) request, receive-error interrupt (eri) request, receive-data-full interrupt (rxi) request, and transmit-data-empty interrupt (txi) request. table 16.13 shows the interrupt sources and their relative priorities. individual interrupt sources can be enabled or disabled with the tie, rie, and teie bits in the scr. each kind of interrupt request is sent to the interrupt controller independently. when the tdre flag in ssr is set to 1, a txi interrupt request is generated. when the tend flag in ssr is set to 1, a tei interrupt request is generated. a txi interrupt can activate the dmac or dtc to perform data transfer. the tdre flag is cleared to 0 automatically when data transfer is performed by the dtc. the dmac or dtc cannot be activated by a tei interrupt request. when the rdrf flag in ssr is set to 1, an rxi interrupt request is generated. when the orer, per, or fer flag in ssr is set to 1, an eri interrupt request is generated. an rxi interrupt can activate the dmac or dtc to perform data transfer. the rdrf flag is cleared to 0 automatically when data transfer is performed by the dmac or dtc. the dmac or dtc cannot be activated by an eri interrupt request. note that the dmac cannot be activated by interrupts of sci channels 2 to 4.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 686 of 1220 rej09b0186-0300o table 16.13 sci interrupt sources channel interrupt source description dtc activation dmac activation priority * 0 eri interrupt due to receive error (orer, fer, or per) not possible not possible high rxi interrupt due to receive data full state (rdrf) possible possible txi interrupt due to transmit data empty state (tdre) possible possible tei interrupt due to transmission end (tend) not possible not possible 1 eri interrupt due to receive error (orer, fer, or per) not possible not possible rxi interrupt due to receive data full state (rdrf) possible possible txi interrupt due to transmit data empty state (tdre) possible possible tei interrupt due to transmission end (tend) not possible not possible 2 eri interrupt due to receive error (orer, fer, or per) not possible not possible rxi interrupt due to receive data full state (rdrf) possible not possible txi interrupt due to transmit data empty state (tdre) possible not possible tei interrupt due to transmission end (tend) not possible not possible 3 eri interrupt due to receive error (orer, fer, or per) not possible not possible rxi interrupt due to receive data full state (rdrf) possible not possible txi interrupt due to transmit data empty state (tdre) possible not possible tei interrupt due to transmission end (tend) not possible not possible 4 eri interrupt due to receive error (orer, fer, or per) not possible not possible rxi interrupt due to receive data full state (rdrf) possible not possible txi interrupt due to transmit data empty state (tdre) possible not possible tei interrupt due to transmission end (tend) not possible not possible low note: * this table shows the initial state immediately after a reset. relative priorities among channels can be changed by means of the interrupt controller.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 687 of 1220 rej09b0186-0300o a tei interrupt is requested when the tend flag is set to 1 while the teie bit is set to 1. the tend flag is cleared at the same time as the tdre flag. consequently, if a tei interrupt and a txi interrupt are requested simultaneously, the txi interrupt may have priority for acceptance, with the result that the tdre and tend flags are cleared. note that the tei interrupt will not be accepted in this case. 16.5 usage notes the following points should be noted when using the sci. (1) relation between writes to tdr and the tdre flag the tdre flag in ssr is a status flag that indicates that transmit data has been transferred from tdr to tsr. when the sci transfers data from tdr to tsr, the tdre flag is set to 1. data can be written to tdr regardless of the state of the tdre flag. however, if new data is written to tdr when the tdre flag is cleared to 0, the data stored in tdr will be lost since it has not yet been transferred to tsr. it is therefore essential to check that the tdre flag is set to 1 before writing transmit data to tdr. (2) operation when multiple receive errors occur simultaneously if a number of receive errors occur at the same time, the state of the status flags in ssr is as shown in table 16.14. if there is an overrun error, data is not transferred from rsr to rdr, and the receive data is lost. table 16.14 state of ssr status flags and transfer of receive data ssr status flags receive data transfer rdrf orer fer per rsr to rdr receive error status 1100x overrun error 0010 o framing error 0001 o parity error 1110x overrun error + framing error 1101x overrun error + parity error 0011 o framing error + parity error 1111x overrun error + framing error + parity error legend: o: receive data is transferred from rsr to rdr. x: receive data is not transferred from rsr to rdr.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 688 of 1220 rej09b0186-0300o (3) break detection and processing (asynchronous mode only) when framing error (fer) detection is performed, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0s, and so the fer flag is set, and the parity error flag (per) may also be set. note that, since the sci continues the receive operation after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. (4) sending a break (asynchronous mode only) the txd pin has a dual function as an i/o port whose direction (input or output) is determined by dr and ddr. this can be used to send a break. between serial transmission initialization and setting of the te bit to 1, the mark state is replaced by the value of dr (the pin does not function as the txd pin until the te bit is set to 1). consequently, ddr and dr for the port corresponding to the txd pin are first set to 1. to send a break during serial transmission, first clear dr to 0, then clear the te bit to 0. when the te bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the txd pin becomes an i/o port, and 0 is output from the txd pin. (5) receive error flags and transmit operations (clocked synchronous mode only) transmission cannot be started when a receive error flag (orer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to clear the receive error flags to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if the re bit is cleared to 0. (6) receive data sampling timing and reception margin in asynchronous mode in asynchronous mode, the sci operates on a basic clock with a frequency of 16 times the transfer rate. in reception, the sci samples the fa lling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 8th pulse of the basic clock. this is illustrated in figure 16.23.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 689 of 1220 rej09b0186-0300o internal basic clock 16 clocks 8 clocks receive data (rxd) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 07 figure 16.23 receive data sampling timing in asynchronous mode thus the reception margin in asynchronous mode is given by formula (1) below. m = | (0.5 ? 1 2n ) ? (l ? 0.5) f ? | d ? 0.5 | n (1 + f) | 100% ... formula (1) where m : reception margin (%) n : ratio of bit rate to clock (n = 16) d : clock duty (d = 0 to 1.0) l : frame length (l = 9 to 12) f : absolute value of clock rate deviation assuming values of f = 0 and d = 0.5 in formula (1), a reception margin of 46.875% is given by formula (2) below. when d = 0.5 and f = 0, m = (0.5 ? 1 2 16 ) 100% = 46.875% ... formula (2) however, this is only the computed value, and a margin of 20% to 30% should be allowed in system design.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 690 of 1220 rej09b0186-0300o (7) restrictions on use of dmac or dtc ? when an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 clock cycles after tdr is updated by the dmac or dtc. misoperation may occur if the transmit clock is input within 4 clocks after tdr is updated. (figure 16.24) ? when rdr is read by the dmac or dtc, be sure to set the activation source to the relevant sci reception end interrupt (rxi). t d0 lsb serial data sck d1 d3 d4 d5 d2 d6 d7 note: when operating on an external clock, set t >4 clocks. tdre figure 16.24 example of clocked synchronous transmission by dtc (8) operation in case of mode transition ? transmission operation should be stopped (by clearing te, tie, and teie to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. tsr, tdr, and ssr are reset. the output pin states in module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and becomes high-level output after the relevant mode is cleared. if a transition is made during transmission, the data being transmitted w ill be undefined. when trans mitting wit hout changing the transmit mode after the relevant mode is cleared, transmission can be started by setting te to 1 again, and performing the following sequence: ssr read -> tdr write -> tdre clearance. to transmit with a different transmit mode after clearing the relevant mode, the procedure must be started again from initialization. figure 16.25 shows a sample flowchart for mode transition during transmission. port pin states are shown in figures 16.26 and 16.27. operation should also be stopped (by clearing te, tie, and teie to 0) before making a transition from transmission by dtc transfer to module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. to perform transmission with the dtc after the relevant mode is cleared, setting te and tie to 1 will set the txi flag and start dtc transmission.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 691 of 1220 rej09b0186-0300o ? reception receive operation should be stopped (by clearing re to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. rsr, rdr, and ssr are reset. if a transition is made without stopping operation, the data being received will be invalid. to continue receiving without changing the reception mode after the relevant mode is cleared, set re to 1 before starting reception. to receive with a different receive mode, the procedure must be started again from initialization. figure 16.28 shows a sample flowchart for mode transition during reception.
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 692 of 1220 rej09b0186-0300o read tend flag in ssr te = 0 transition to software standby mode, etc. exit from software standby mode, etc. change operating mode? no all data transmitted? tend = 1 yes yes yes no no [1] [3] [2] te = 1 initialization [1] data being transmitted is interrupt- ed. after exiting software standby mode, etc., normal cpu transmis- sion is possible by setting te to 1, reading ssr, writing tdr, and clearing tdre to 0, but note that if the dtc has been activated, the remaining data in dtcram will be transmitted when te and tie are set to 1. [2] if tie and teie are set to 1, clear them to 0 in the same way. [3] includes module stop mode, watch mode, subactive mode, and sub- sleep mode. figure 16.25 sample flowchart for mode transition during transmission
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 693 of 1220 rej09b0186-0300o sck output pin te bit txd output pin port input/output high output port input/output high output start stop start of transmission end of transmission port input/output sci txd output port sci txd output port transition to software standby exit from software standby figure 16.26 asynchronous transmission using internal clock port input/output last txd bit held high output * port input/output marking output port input/output sci txd output port port note: * initialized b y software standb y . sck output pin te bit txd output pin sci txd output start of transmission end of transmission transition to software standby exit from software standby figure 16.27 synchronous transmission using internal clock
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 694 of 1220 rej09b0186-0300o re = 0 transition to software standby mode, etc. read receive data in rdr read rdrf flag in ssr exit from software standby mode, etc. change operating mode? no rdrf = 1 yes yes no [1] [2] re = 1 initialization [1] receive data being received be- comes invalid. [2] includes module stop mode, watch mode, subactive mode, and sub- sleep mode. figure 16.28 sample flowchart for mode transition during reception
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 695 of 1220 rej09b0186-0300o (9) switching from sck pin function to port pin function: ? problem in operation: when switching the sck pin function to the output port function (high- level output) by making the following settings while ddr = 1, dr = 1, c/ a = 1, cke1 = 0, cke0 = 0, and te = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. end of serial data transmission 2. te bit = 0 3. c/ a bit = 0 ... switchover to port output 4. occurrence of low-level output (see figure 16.29) sck/port data te c/ a cke1 cke0 bit 7 bit 6 1. end of transmission 4. low-level output 3.c/ a = 0 2.te = 0 half-cycle low-level output figure 16.29 operation when switching from sck pin function to port pin function ? sample procedure for avoiding low-level output: as this sample procedure temporarily places the sck pin in the input state, the sck/port pin should be pulled up beforehand with an external circuit. with ddr = 1, dr = 1, c/ a = 1, cke1 = 0, cke0 = 0, and te = 1, make the following settings in the order shown. 1. end of serial data transmission 2. te bit = 0 3. cke1 bit = 1 4. c/ a bit = 0 ... switchover to port output 5. cke1 bit = 0
section 16 serial communication interface (sci, irda) rev. 3.00 jan 11, 2005 page 696 of 1220 rej09b0186-0300o sck/port data te c/ a cke1 cke0 bit 7 bit 6 1. end of transmission 3.cke1 = 1 5.cke1 = 0 4.c/ a = 0 2.te = 0 high-level outputte figure 16.30 operation when switching from sck pin function to port pin function (example of preventing low-level output)
section 17 smart card interface rev. 3.00 jan 11, 2005 page 697 of 1220 rej09b0186-0300o section 17 smart card interface 17.1 overview sci supports an ic card (smart card) interface conforming to iso/iec 7816-3 (identification card) as a serial communication interface extension function. switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting. 17.1.1 features features of the smart card interface supported by the h8s/2643 group are as follows. ? asynchronous mode ? data length: 8 bits ? parity bit generation and checking ? transmission of error signal (parity error) in receive mode ? error signal detection and automatic data retransmission in transmit mode ? direct convention and inverse convention both supported ? on-chip baud rate generator allows any bit rate to be selected ? three interrupt sources ? three interrupt sources (transmit data empty, receive data full, and transmit/receive error) that can issue requests independently ? the transmit data empty interrupt and receive data full interrupt can activate the dma controller (dmac) or data transfer controller (dtc) to execute data transfer
section 17 smart card interface rev. 3.00 jan 11, 2005 page 698 of 1220 rej09b0186-0300o 17.1.2 block diagram figure 17.1 shows a block diagram of the smart card interface. bus interface tdr rsr rdr module data bus tsr scmr ssr scr transmission/ reception control brr baud rate generator internal data bus rxd txd sck parity generation parity check clock /4 /16 /64 txi rxi eri smr legend: scmr: rsr: rdr: tsr: tdr: smr: scr: ssr: brr: smart card mode register receive shift register receive data register transmit shift register transmit data register serial mode register serial control register serial status register bit rate register figure 17.1 block diagram of smart card interface
section 17 smart card interface rev. 3.00 jan 11, 2005 page 699 of 1220 rej09b0186-0300o 17.1.3 pin configuration table 17.1 shows the smart card interface pin configuration. table 17.1 smart card interface pins channel pin name symbol i/o function 0 serial clock pin 0 sck0 i/o sci0 clock input/output receive data pin 0 rxd0 input sci0 receive data input transmit data pin 0 txd0 output sci0 transmit data output 1 serial clock pin 1 sck1 i/o sci1 clock input/output receive data pin 1 rxd1 input sci1 receive data input transmit data pin 1 txd1 output sci1 transmit data output 2 serial clock pin 2 sck2 i/o sci2 clock input/output receive data pin 2 rxd2 input sci2 receive data input transmit data pin 2 txd2 output sci2 transmit data output 3 serial clock pin 3 sck3 i/o sci3 clock input/output receive data pin 3 rxd3 input sci3 receive data input transmit data pin 3 txd3 output sci3 transmit data output 4 serial clock pin 4 sck4 i/o sci4 clock input/output receive data pin 4 rxd4 input sci4 receive data input transmit data pin 4 txd4 output sci4 transmit data output
section 17 smart card interface rev. 3.00 jan 11, 2005 page 700 of 1220 rej09b0186-0300o 17.1.4 register configuration table 17.2 shows the registers used by the smart card interface. details of brr, tdr, rdr, and mstpcr are the same as for the normal sci function: see the register descriptions in section 16, serial communication interface. table 17.2 smart card interface registers channel name abbreviation r/w initial value address * 1 0 serial mode register 0 smr0 r/w h'00 h'ff78 bit rate register 0 brr0 r/w h'ff h'ff79 serial control register 0 scr0 r/w h'00 h'ff7a transmit data register 0 tdr0 r/w h'ff h'ff7b serial status register 0 ssr0 r/(w) * 2 h'84 h'ff7c receive data register 0 rdr0 r h'00 h 'ff7d smart card mode register 0 scmr0 r/w h'f2 h'ff7e 1 serial mode register 1 smr1 r/w h'00 h'ff80 bit rate register 1 brr1 r/w h'ff h'ff81 serial control register 1 scr1 r/w h'00 h'ff82 transmit data register 1 tdr1 r/w h'ff h'ff83 serial status register 1 ssr1 r/(w) * 2 h'84 h'ff84 receive data register 1 rdr1 r h'00 h 'ff85 smart card mode register 1 scmr1 r/w h'f2 h'ff86 2 serial mode register 2 smr2 r/w h'00 h'ff88 bit rate register 2 brr2 r/w h'ff h'ff89 serial control register 2 scr2 r/w h'00 h'ff8a transmit data register 2 tdr2 r/w h'ff h'ff8b serial status register 2 ssr2 r/(w) * 2 h'84 h'ff8c receive data register 2 rdr2 r h'00 h 'ff8d smart card mode register 2 scmr2 r/w h'f2 h'ff8e
section 17 smart card interface rev. 3.00 jan 11, 2005 page 701 of 1220 rej09b0186-0300o channel name abbreviation r/w initial value address * 1 3 serial mode register 3 smr3 r/w h'00 h'fdd0 bit rate register 3 brr3 r/w h'ff h'fdd1 serial control register 3 scr3 r/w h'00 h'fdd2 transmit data register 3 tdr3 r/w h'ff h'fdd3 serial status register 3 ssr3 r/(w) * 2 h'84 h'fdd4 receive data register 3 rdr3 r h'00 h'fdd5 smart card mode register 3 scmr3 r/w h'f2 h'fdd6 4 serial mode register 4 smr4 r/w h'00 h'fdd8 bit rate register 4 brr4 r/w h'ff h'fdd9 serial control register 4 scr4 r/w h'00 h'fdda transmit data register 4 tdr4 r/w h'ff h'fddb serial status register 4 ssr4 r/(w) * 2 h'84 h'fddc receive data register 4 rdr4 r h'00 h'fddd smart card mode register 4 scmr4 r/w h'f2 h'fdde all module stop control mstpcrb r/w h'ff h'fde9 register b, c mstpcrc r/w h'ff h'fdea notes: 1. lower 16 bits of the address. 2. can only be written with 0 for flag clearing.
section 17 smart card interface rev. 3.00 jan 11, 2005 page 702 of 1220 rej09b0186-0300o 17.2 register descriptions registers added with the smart card interface and bits for which the function changes are described here. 17.2.1 smart card mode register (scmr) bit:76543210 ????sdirsinv?smif initial value:11110010 r/w:????r/wr/w?r/w scmr is an 8-bit readable/writable register that selects the smart card interface function. scmr is initialized to h'f2 by a reset and in standby mode. bits 7 to 4?reserved: these bits are always read as 1 and cannot be modified. bit 3?smart card data transfer direction (sdir): selects the serial/parallel conversion format. bit 3 sdir description 0 tdr contents are transmitted lsb-first (initial value) receive data is stored in rdr lsb-first 1 tdr contents are transmitted msb-first receive data is stored in rdr msb-first
section 17 smart card interface rev. 3.00 jan 11, 2005 page 703 of 1220 rej09b0186-0300o bit 2?smart card data invert (sinv): specifies inversion of the data logic level. this function is used together with the sdir bit for communication with an inverse convention card. the sinv bit does not affect the logic level of the parity bit. for parity-related setting procedures, see section 17.3.4, register settings. bit 2 sinv description 0 tdr contents are transmitted as they are (initial value) receive data is stored as it is in rdr 1 tdr contents are inverted before being transmitted receive data is stored in inverted form in rdr bit 1?reserved: this bit is always read as 1 and cannot be modified. bit 0?smart card interface mode select (smif): enables or disables the smart card interface function. bit 0 smif description 0 smart card interface function is disabled (initial value) 1 smart card interface function is enabled
section 17 smart card interface rev. 3.00 jan 11, 2005 page 704 of 1220 rej09b0186-0300o 17.2.2 serial status register (ssr) bit:76543210 tdre rdrf orer ers per tend mpb mpbt initial value:10000100 r/w : r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * rrr/w note: * only 0 can be written, to clear these flags. bit 4 of ssr has a different function in smart card interface mode. coupled with this, the setting conditions for bit 2, tend, are also different. bits 7 to 5? operate in the same way as for the normal sci. for details, see section 16.2.7, serial status register (ssr). bit 4?error signal status (ers): in smart card interface mode, bit 4 indicates the status of the error signal sent back from the receiving end in transmission. framing errors are not detected in smart card interface mode. bit 4 ers description 0 normal reception, with no error signal [clearing conditions] (initial value) ? upon reset, and in standby mode or module stop mode ? when 0 is written to ers after reading ers = 1 1 error signal sent from receiver indicating detection of parity error [setting condition] ? when the low level of the error signal is sampled note: clearing the te bit in scr to 0 does not affect the ers flag, which retains its previous state.
section 17 smart card interface rev. 3.00 jan 11, 2005 page 705 of 1220 rej09b0186-0300o bits 3 to 0? operate in the same way as for the normal sci. for details, see section 16.2.7, serial status register (ssr). however, the setting conditions for the tend bit, are as shown below. bit 2 tend description 0 transmission is in progress [clearing conditions] (initial value) ? when 0 is written to tdre after reading tdre = 1 ? when the dmac or dtc is activated by a txi interrupt and write data to tdr 1 transmission has ended [setting conditions] ? upon reset, and in standby mode or module stop mode ? when the te bit in scr is 0 and the ers bit is also 0 ? when tdre = 1 and ers = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when gm = 0 and blk = 0 ? when tdre = 1 and ers = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when gm = 0 and blk = 1 ? when tdre = 1 and ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 0 ? when tdre = 1 and ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 1 note: etu: elementary time unit (time for transfer of 1 bit)
section 17 smart card interface rev. 3.00 jan 11, 2005 page 706 of 1220 rej09b0186-0300o 17.2.3 serial mode register (smr) bit:76543210 gm blk pe o/ e bcp1 bcp0 cks1 cks0 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w note: when the smart card interface is used, be sure to make the 1 setting shown for bit 5. the function of bits 7, 6, 3, and 2 of smr changes in smart card interface mode. bit 7?gsm mode (gm): sets the smart card interface function to gsm mode. this bit is cleared to 0 when the normal smart card interface is used. in gsm mode, this bit is set to 1, the timing of setting of the tend flag that indicates transmission completion is advanced and clock output control mode addition is performed. the contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control register (scr). bit 7 gm description 0 normal smart card interface mode operation (initial value) ? tend flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit ? clock output on/off control only 1 gsm mode smart card interface mode operation ? tend flag generation 11.0 etu after beginning of start bit ? high/low fixing control possible in addition to clock output on/off control (set by scr) note: etu: elementary time unit (time for transfer of 1 bit)
section 17 smart card interface rev. 3.00 jan 11, 2005 page 707 of 1220 rej09b0186-0300o bit 6?block transfer mode (blk): selects block transfer mode. bit 6 blk description 0 normal smart card interface mode operation ? error signal transmission/detection and automatic data retransmission performed ? txi interrupt generated by tend flag ? tend flag set 12.5 etu after start of transmission (11.0 etu in gsm mode) 1 block transfer mode operation ? error signal transmission/detection and automatic data retransmission not performed ? txi interrupt generated by tdre flag ? tend flag set 11.5 etu after start of transmission (11.0 etu in gsm mode) bits 3 and 2?basic clock pulse 1 and 2 (bcp1, bcp0): these bits specify the number of basic clock periods in a 1-bit transfer interval on the smart card interface. bit 3 bit 2 bcp1 bcp0 description 0 1 32 clock periods (initial value) 0 64 clock periods 1 1 372 clock periods 0 256 clock periods bits 5, 4, 1, and 0: operate in the same way as for the normal sci. for details, see section 16.2.5, serial mode register (smr).
section 17 smart card interface rev. 3.00 jan 11, 2005 page 708 of 1220 rej09b0186-0300o 17.2.4 serial control register (scr) bit:76543210 tie rie te re mpie teie cke1 cke0 initial value:00000000 r/w : r/w r/w r/w r/w r/w r/w r/w r/w in smart card interface mode, the function of bits 1 and 0 of scr changes when bit 7 of the serial mode register (smr) is set to 1. bits 7 to 2 ?operate in the same way as for the normal sci. for details, see section 16.2.6, serial control register (scr). bits 1 and 0?clock enable 1 and 0 (cke1, cke0): these bits are used to select the sci clock source and enable or disable clock output from the sck pin. in smart card interface mode, in addition to the normal switching between clock output enabling and disabling, the clock output can be specified as to be fixed high or low. scmr smr scr setting smif c/ a , gm cke1 cke0 sck pin function 0 see the sci 1 0 0 0 operates as port i/o pin 1 0 0 1 outputs clock as sck output pin 1 1 0 0 operates as sck output pin, with output fixed low 1 1 0 1 outputs clock as sck output pin 1110 operates as sck output pin, with output fixed high 1 1 1 1 outputs clock as sck output pin
section 17 smart card interface rev. 3.00 jan 11, 2005 page 709 of 1220 rej09b0186-0300o 17.3 operation 17.3.1 overview the main functions of the smart card interface are as follows. ? one frame consists of 8-bit data plus a parity bit. ? in transmission, a guard time of at least 2 etu (elementary time unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. ? if a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. ? if the error signal is sampled during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. (except in block transfer mode). ? only asynchronous communication is supported; there is no clocked synchronous communication function. 17.3.2 pin connections figure 17.2 shows a schematic diagram of smart card interface related pin connections. in communication with an ic card, since both transmission and reception are carried out on a single data transmission line, the txd pin and rxd pin should be connected with the lsi pin. the data transmission line should be pulled up to the v cc power supply with a resistor. when the clock generated on the smart card interface is used by an ic card, the sck pin output is input to the clk pin of the ic card. no connection is needed if the ic card uses an internal clock. lsi port output is used as the reset signal. other pins must normally be connected to the power supply or ground.
section 17 smart card interface rev. 3.00 jan 11, 2005 page 710 of 1220 rej09b0186-0300o txd rxd sck rx (port) h8s/2643 group i/o clk rst v cc connected equipment ic card data line clock line reset line figure 17.2 schematic diagram of smart card interface pin connections note: if an ic card is not connected, and the te and re bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out.
section 17 smart card interface rev. 3.00 jan 11, 2005 page 711 of 1220 rej09b0186-0300o 17.3.3 data format (1) normal transfer mode figure 17.3 shows the normal smart card interface data format. in reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting e nd, and retransmission of the data is requested. if an error signal is sampled during transmission, the same data is retrans mitted. ds d0 d1 d2 d3 d4 d5 d6 d7 dp when there is no parity error transmitting station output ds d0 d1 d2 d3 d4 d5 d6 d7 dp when a parity error occurs transmitting station output de receiving station output start bit data bits parity bit error signal legend: ds: d0 to d7: dp: de: figure 17.3 normal smart card interface data format
section 17 smart card interface rev. 3.00 jan 11, 2005 page 712 of 1220 rej09b0186-0300o the operation sequence is as follows. [1] when the data line is not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. [2] the transmitting station starts transfer of one frame of data. the data frame starts with a start bit (ds, low-level), followed by 8 data bits (d0 to d7) and a parity bit (dp). [3] with the smart card interface, the data line then returns to the high-impedance state. the data line is pulled high with a pull-up resistor. [4] the receiving station carries out a parity check. if there is no parity error and the data is received normally, the receiving station waits for reception of the next data. if a parity error occurs, however, the receiving station outputs an error signal (de, low-level) to request retransmission of the data. after outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. the signal line is pulled high again by a pull-up resistor. [5] if the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. if it does receive an error signal, however, it returns to step [2] and retransmits the erroneous data. (2) block transfer mode the operation sequence in block transfer mode is as follows. [1] when the data line in not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. [2] the transmitting station starts transfer of one frame of data. the data frame starts with a start bit (ds, low-level), followed by 8 data bits (d0 to d7) and a parity bit (dp). [3] with the smart card interface, the data line then returns to the high-impedance state. the data line is pulled high with a pull-up resistor. [4] after reception, a parity error check is carried out, but an error signal is not output even if an error has occurred. when an error occurs reception cannot be continued, so the error flag should be cleared to 0 before the parity bit of the next frame is received. [5] the transmitting station proceeds to transmit the next data frame.
section 17 smart card interface rev. 3.00 jan 11, 2005 page 713 of 1220 rej09b0186-0300o 17.3.4 register settings table 17.3 shows a bit map of the registers used by the smart card interface. bits indicated as 0 or 1 must be set to the value shown. the setting of other bits is described below. table 17.3 smart card interface register settings bit register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 smr gm blk 1 o/ e bcp1 bcp0 cks1 cks0 brr brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scr tie rie te re 0 0 cke1 * cke0 tdr tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 ssr tdre rdrf orer ers per tend 0 0 rdr rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 scmr ???? sdir sinv ? smif legend: ? : unused bit. * : the cke1 bit must be cleared to 0 when the gm bit in smr is cleared to 0. (1) smr setting the gm bit is cleared to 0 in normal smart card interface mode, and set to 1 in gsm mode. the o/ e bit is cleared to 0 if the ic card is of the direct convention type, and set to 1 if of the inverse convention type. bits cks1 and cks0 select the clock source of the on-chip baud rate generator. bits bcp1 and bcp0 select the number of basic clock periods in a 1-bit transfer interval. for details, see section 17.3.5, clock. the blk bit is cleared to 0 in normal smart card interface mode, and set to 1 in block transfer mode. (2) brr setting brr is used to set the bit rate. see section 17.3.5, clock, for the method of calculating the value to be set.
section 17 smart card interface rev. 3.00 jan 11, 2005 page 714 of 1220 rej09b0186-0300o (3) scr setting the function of the tie, rie, te, and re bits is the same as for the normal sci. for details, see section 16, serial communication interface. bits cke1 and cke0 specify the clock output. when the gm bit in smr is cleared to 0, set these bits to b'00 if a clock is not to be output, or to b'01 if a clock is to be output. when the gm bit in smr is set to 1, clock output is performed. the clock output can also be fixed high or low. (4) smart card mode register (scmr) setting the sdir bit is cleared to 0 if the ic card is of the direct convention type, and set to 1 if of the inverse convention type. the sinv bit is cleared to 0 if the ic card is of the direct convention type, and set to 1 if of the inverse convention type. the smif bit is set to 1 in the case of the smart card interface. examples of register settings and the waveform of the start character are shown below for the two types of ic card (direct convention and inverse convention). ? direct convention (sdir = sinv = o/ e = 0) ds d0 d1 d2 d3 d4 d5 d6 d7 dp azzazzzaaz (z) (z) state with the direct convention type, the logic 1 level corresponds to state z and the logic 0 level to state a, and transfer is performed in lsb-first order. the start character data above is h'3b. the parity bit is 1 since even parity is stipulated for the smart card. ? inverse convention (sdir = sinv = o/ e = 1) ds d7 d6 d5 d4 d3 d2 d1 d0 dp azzaaaaaaz (z) (z) state with the inverse convention type, the logic 1 level corresponds to state a and the logic 0 level to state z, and transfer is performed in msb-first order. the start character data above is h'3f. the parity bit is 0, corresponding to state z, since even parity is stipulated for the smart card.
section 17 smart card interface rev. 3.00 jan 11, 2005 page 715 of 1220 rej09b0186-0300o with the h8s/2643 group, inversion specified by the sinv bit applies only to the data bits, d7 to d0. for parity bit inversion, the o/ e bit in smr is set to odd parity mode (the same applies to both transmission and reception). 17.3.5 clock only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. the bit rate is set with brr and the cks1, cks0, bcp1 and bcp0 bits in smr. the formula for calculating the bit rate is as shown below. table 17.5 shows some sample bit rates. if clock output is selected by setting cke0 to 1, a clock is output from the sck pin. the clock frequency is determined by the bit rate and the setting of bits bcp1 and bcp0. b = s 2 2n+1 (n + 1) 10 6 where: n = value set in brr (0 n 255) b = bit rate (bit/s) = operating frequency (mhz) n = see table 17.4 s = number of internal clocks in 1-bit period, set by bcp1 and bcp0 table 17.4 correspondence between n and cks1, cks0 n cks1 cks0 000 11 210 31
section 17 smart card interface rev. 3.00 jan 11, 2005 page 716 of 1220 rej09b0186-0300o table 17.5 examples of bit rate b (bit/s) for various brr settings (when n = 0 and s = 372) (mhz) n 10.00 10.714 13.00 14.285 16.00 18.00 20.00 25.00 0 13441 14400 17473 19200 21505 24194 26882 33602 1 6720 7200 8737 9600 10753 12097 13441 16801 2 4480 4800 5824 6400 7168 8065 8961 11201 note: bit rates are rounded to the nearest whole number. the method of calculating the value to be set in the bit rate register (brr) from the operating frequency and bit rate, on the other hand, is shown below. n is an integer, 0 n 255, and the smaller error is specified. n = s 2 2n+1 b 10 6 ? 1 table 17.6 examples of brr settings for bit rate b (bit/s) (when n = 0 and s = 372) (mhz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 25.00 bit/s n error n error n error n error n error n error n error n error n error 9600 0 0.00 1 30 1 25 1 8.99 1 0.00 1 12.01 2 15.99 2 6.60 3 12.49
section 17 smart card interface rev. 3.00 jan 11, 2005 page 717 of 1220 rej09b0186-0300o table 17.7 maximum bit rate at various frequencies (smart card interface mode) (when s = 372) (mhz) maximum bit rate (bit/s) n n 7.1424 9600 0 0 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 14.2848 19200 0 0 16.00 21505 0 0 18.00 24194 0 0 20.00 26882 0 0 25.00 33602 0 0 the bit rate error is given by the following formula: error (%) = ( s 2 2n+1 b (n + 1) 10 6 ? 1) 100 17.3.6 data transfer operations (1) initialization before transmitting and receiving data, initialize the sci as described below. initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] clear the te and re bits in scr to 0. [2] clear the error flags ers, per, and orer in ssr to 0. [3] set the gm, blk, o/e, bcp1, bcp0, cks1, cks0 bits in smr. set the pe bit to 1. [4] set the smif, sdir, and sinv bits in scmr. when the smif bit is set to 1, the txd and rxd pins are both switched from ports to sci pins, and are placed in the high-impedance state. [5] set the value corresponding to the bit rate in brr. [6] set the cke0 and cke1 bits in scr. clear the tie, rie, te, re, mpie, and teie bits to 0. if the cke0 bit is set to 1, the clock is output from the sck pin. [7] wait at least one bit interval, then set the tie, rie, te, and re bits in scr. do not set the te bit and re bit at the same time, except for self-diagnosis.
section 17 smart card interface rev. 3.00 jan 11, 2005 page 718 of 1220 rej09b0186-0300o (2) serial data transmission as data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal sci. figure 17.4 shows a flowchart for transmitting, and figure 1 7.5 shows the relation between a transmit operation and the internal registers. [1] perform smart card interface mode initialization as described above in initialization. [2] check that the ers error flag in ssr is cleared to 0. [3] repeat steps [2] and [3] until it can be confirmed that the tend flag in ssr is set to 1. [4] write the transmit data to tdr, clear the tdre flag to 0, and perform the transmit operation. the tend flag is cleared to 0. [5] when transmitting data continuously, go back to step [2]. [6] to end transmission, clear the te bit to 0. with the above processing, interrupt servicing or data transfer by the dmac or dtc is possible. if transmission ends and the tend flag is set to 1 while the tie bit is set to 1 and interrupt requests are enabled, a transmit data empty interrupt (txi) request will be generated. if an error occurs in transmission and the ers flag is set to 1 while the rie bit is set to 1 and interrupt requests are enabled, a transfer error interrupt (eri) request will be generated. the timing for setting the tend flag depends on the value of the gm bit in smr. the tend flag set timing is shown in figure 17.6. if the dmac or dtc is activated by a txi request, the number of bytes set in the dmac or dtc can be transmitted automatically, including automatic retransmission. for details, see (6), interrupt operation (except block transfer mode), and (7), data transfer operation by dmac or dtc. note: for block transfer mode, see section 16.3.2, operation in asynchronous mode.
section 17 smart card interface rev. 3.00 jan 11, 2005 page 719 of 1220 rej09b0186-0300o initialization no yes clear te bit to 0 start transmission start no no no yes yes yes yes no end write data to tdr, and clear tdre flag in ssr to 0 error processing error processing tend = 1? all data transmitted? tend = 1? ers = 0? ers = 0? figure 17.4 example of transmission processing flow
section 17 smart card interface rev. 3.00 jan 11, 2005 page 720 of 1220 rej09b0186-0300o (1) data write tdr tsr (shift register) data 1 (2) transfer from tdr to tsr data 1 data 1 ; data remains in tdr (3) serial data output note: when the ers flag is set, it should be cleared until transfer of the last bit (d7 in lsb-first transmission, d0 in msb-first transmission) of the next transfer data to be transmitted has been completed. in case of normal transmission: tend flag is set in case of transmit error: ers flag is set steps (2) and (3) above are repeated until the tend flag is se t i/o signal line output data 1 data 1 figure 17.5 relation between transmit operation and internal registers ds d0 d1 d2 d3 d4 d5 d6 d7 dp i/o data 12.5etu txi (tend interrupt) 11.0etu de guard time when gm = 1 legend: ds: start bit d0 to d7: data bits dp: parity bit de: error si g nal when gm = 0 figure 17.6 tend flag generation timing in transmission operation
section 17 smart card interface rev. 3.00 jan 11, 2005 page 721 of 1220 rej09b0186-0300o (3) serial data reception (except block transfer mode) data reception in smart card mode uses the same processing procedure as for the normal sci. figure 17.7 shows an example of the transmission processing flow. [1] perform smart card interface mode initialization as described above in initialization. [2] check that the orer flag and per flag in ssr are cleared to 0. if either is set, perform the appropriate receive error processing, then clear both the orer and the per flag to 0. [3] repeat steps [2] and [3] until it can be confirmed that the rdrf flag is set to 1. [4] read the receive data from rdr. [5] when receiving data continuously, clear the rdrf flag to 0 and go back to step [2]. [6] to end reception, clear the re bit to 0. initialization read rdr and clear rdrf flag in ssr to 0 clear re bit to 0 start reception start error processing no no no yes yes orer = 0 and per = 0 rdrf = 1? all data received? yes figure 17.7 example of reception processing flow
section 17 smart card interface rev. 3.00 jan 11, 2005 page 722 of 1220 rej09b0186-0300o with the above processing, interrupt servicing or data transfer by the dmac or dtc is possible. if reception ends and the rdrf flag is set to 1 while the rie bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (rxi) request will be generated. if an error occurs in reception and either the orer flag or the per flag is set to 1, a transfer error interrupt (eri) request will be generated. if the dmac or dtc is activated by an rxi request, the receive data in which the error occurred is skipped, and only the number of bytes of receive data set in the dmac or dtc are transferred. for details, see (6), interrupt operation (except block transfer mode), and (7), data transfer operation by dmac or dtc. if a parity error occurs during reception and the per is set to 1, the received data is still transferred to rdr, and therefore this data can be read. note: for block transfer mode, see section 16.3.2, operation in asynchronous mode. (4) mode switching operation when switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing re bit to 0 and setting te bit to 1. the rdrf flag or the per and orer flags can be used to check that the receive operation has been completed. when switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing te bit to 0 and setting re bit to 1. the tend flag can be used to check that the transmit operation has been completed. (5) fixing clock output level when the gm bit in smr is set to 1, the clock output level can be fixed with bits cke1 and cke0 in scr. at this time, the minimum clock pulse width can be made the specified width. figure 17.8 shows the t iming for fixing the clock output level. in this example, gm is set to 1, cke1 is cleared to 0, and the cke0 bit is controlled.
section 17 smart card interface rev. 3.00 jan 11, 2005 page 723 of 1220 rej09b0186-0300o sck specified pulse width scr write ( cke0 = 0 ) scr write ( cke0 = 1 ) specified pulse width figure 17.8 timing for fixing clock output level (6) interrupt operation (except block transfer mode) there are three interrupt sources in smart card interface mode: transmit data empty interrupt (txi) requests, transfer error interrupt (eri) requests, and receive data full interrupt (rxi) requests. the transmit end interrupt (tei) request is not used in this mode. when the tend flag in ssr is set to 1, a txi interrupt request is generated. when the rdrf flag in ssr is set to 1, an rxi interrupt request is generated. when any of flags orer, per, and ers in ssr is set to 1, an eri interrupt request is generated. the relationship between the operating states and interrupt sources is shown in table 17.8. note: for block transfer mode, see section 16.4, sci interrupts. table 17.8 smart card mode operating states and interrupt sources operating state flag enable bit interrupt source dmac activation dtc activation transmit mode normal operation tend tie txi possible possible error ers rie eri not possible not possible receive mode normal operation rdrf rie rxi possible possible error per, orer rie eri not possible not possible (7) data transfer operation by dmac or dtc in smart card mode, as with the normal sci, transfer can be carried out using the dmac or dtc. in a transmit operation, the tdre flag is also set to 1 at the same time as the tend flag in ssr, and a txi interrupt is generated. if the txi request is designated beforehand as a dmac or dtc activation source, the dmac or dtc will be activated by the txi request, and transfer of the
section 17 smart card interface rev. 3.00 jan 11, 2005 page 724 of 1220 rej09b0186-0300o transmit data will be carried out. the tdre and tend flags are automatically cleared to 0 when data transfer is performed by the dtc. in the event of an error, the sci retransmits the same data automatically. during this period, tend remains cleared to 0 and the dmac is not activated. therefore, the sci and dmac will automatically transmit the specified number of bytes, including retransmission in the event of an error. however, the ers flag is not cleared automatically when an error occurs, and so the rie bit should be set to 1 beforehand so that an eri request will be generated in the event of an error, and the ers flag will be cleared. when performing transfer using the dmac or dtc, it is essential to set and enable the dmac or dtc before carrying out sci setting. for details of the dmac or dtc setting procedures, see section 8, dma controller (dmac) and section 9, data transfer controller (dtc). in a receive operation, an rxi interrupt request is generated when the rdrf flag in ssr is set to 1. if the rxi request is designated beforehand as a dmac or dtc activation source, the dmac or dtc will be activated by the rxi request, and transfer of the receive data will be carried out. the rdrf flag is cleared to 0 automatically when data transfer is performed by the dmac or dtc. if an error occurs, an error flag is set but the rdrf flag is not. consequently, the dmac or dtc is not activated, but instead, an eri interrupt request is sent to the cpu. therefore, the error flag should be cleared. note: for block transfer mode, see section 16.4, sci interrupts. 17.3.7 operation in gsm mode (1) switching the mode when switching between smart card interface mode and software standby mode, the following switching procedure should be followed in order to maintain the clock duty. ? when changing from smart card interface mode to software standby mode [1] set the data register (dr) and data direction register (ddr) corresponding to the sck pin to the value for the fixed output state in software standby mode. [2] write 0 to the te bit and re bit in the serial control register (scr) to halt transmit/receive operation. at the same time, set the cke1 bit to the value for the fixed output state in software standby mode. [3] write 0 to the cke0 bit in scr to halt the clock. [4] wait for one serial clock period. during this interval, clock output is fixed at the specified level, with the duty preserved. [5] make the transition to the software standby state.
section 17 smart card interface rev. 3.00 jan 11, 2005 page 725 of 1220 rej09b0186-0300o ? when returning to smart card interface mode from software standby mode [6] exit the software standby state. [7] write 1 to the cke0 bit in scr and output the clock. signal generation is started with the normal duty. [1] [2] [3] [4] [5] [6] [7] software standby normal operation normal operation figure 17.9 clock halt and restart procedure (2) powering on to secure the clock duty from power-on, the following switching procedure should be followed. [1] the initial state is port input and high impedance. use a pull-up resistor or pull-down resistor to fix the potential. [2] fix the sck pin to the specified output level with the cke1 bit in scr. [3] set smr and scmr, and switch to smart card mode operation. [4] set the cke0 bit in scr to 1 to start clock output. 17.3.8 operation in block transfer mode operation in block transfer mode is the same as in sci asynchronous mode, except for the following points. for details, see section 16.3.2, operation in asynchronous mode. (1) data format the data format is 8 bits with parity. there is no stop bit, but there is a 2-bit (1-bit or more in reception) error guard time. also, except during transmission (with start bit, data bits, and parity bit), the transmission pins go to the high-impedance state, so the signal lines must be fixed high with a pull-up resistor.
section 17 smart card interface rev. 3.00 jan 11, 2005 page 726 of 1220 rej09b0186-0300o (2) transmit/receive clock only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock. the number of basic clock periods in a 1-bit transfer interval can be set to 32, 64, 372, or 256 with bits bcp1 and bcp0. for details, see section 17.3.5, clock. (3) ers (fer) flag as with the normal smart card interface, the ers flag indicates the error signal status, but since error signal transmission and reception is not performed, this flag is always cleared to 0.
section 17 smart card interface rev. 3.00 jan 11, 2005 page 727 of 1220 rej09b0186-0300o 17.4 usage notes the following points should be noted when using the sci as a smart card interface. (1) receive data sampling timing and reception margin in smart card interface mode in smart card interface mode, the sci operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (as determined by bits bcp1 and bcp0). in reception, the sci samples the fa lling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock. figure 17.10 shows the receive data sampling t iming when using a clock of 372 times the transfer rate. internal basic clock 372 clocks 186 clocks receive data (rxd) synchro- nization sampling timing d0 d1 data sampling timin g 185 371 0 371 185 0 0 start bit figure 17.10 receive data sampling timing in smart card mode (using clock of 372 times the transfer rate)
section 17 smart card interface rev. 3.00 jan 11, 2005 page 728 of 1220 rej09b0186-0300o thus the reception margin in asynchronous mode is given by the following formula. formula for reception margin in smart card interface mode m = ? (0.5 ? 1 2n ) ? (l ? 0.5) f ? ? d ? 0.5 ? n (1 + f ) ? 100% where m: reception margin (%) n: ratio of bit rate to clock (n = 32, 64, 372, and 256) d: clock duty (d = 0 to 1.0) l: frame length (l = 10) f: absolute value of clock frequency deviation assuming values of f = 0, d = 0.5 and n = 372 in the above formula, the reception margin formula is as follows. when d = 0.5 and f = 0, m = (0.5 ? 1/2 372) 100% = 49.866% (2) retransfer operations (except block transfer mode) retransfer operations are performed by the sci in receive mode and transmit mode as described below. ? retransfer operation when sci is in receive mode figure 17.11 illustrates the retransfer operation when the sci is in receive mode. [1] if an error is found when the received parity bit is checked, the per bit in ssr is automatically set to 1. if the rie bit in scr is enabled at this time, an eri interrupt request is generated. the per bit in ssr should be kept cleared to 0 until the next parity bit is sampled. [2] the rdrf bit in ssr is not set for a frame in which an error has occurred. [3] if no error is found when the received parity bit is checked, the per bit in ssr is not set to 1. [4] if no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the rdrf flag in ssr is automatically set to 1. if the rie bit in scr is enabled at this time, an rxi interrupt request is generated. if dmac or dtc data transfer by an rxi source is enabled, the contents of rdr can be read automatically. when the rdr data is read by the dmac or dtc, the rdrf flag is automatically cleared to 0. [5] when a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission.
section 17 smart card interface rev. 3.00 jan 11, 2005 page 729 of 1220 rej09b0186-0300o d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds transfer frame n+1 retransferred frame nth transfer frame rdrf [1] per [2] [3] [4] figure 17.11 retransfer operation in sci receive mode ? retransfer operation when sci is in transmit mode figure 17.12 illustrates the retransfer operation when the sci is in transmit mode. [6] if an error signal is sent back from the receiving end after transmission of one frame is completed, the ers bit in ssr is set to 1. if the rie bit in scr is enabled at this time, an eri interrupt request is generated. the ers bit in ssr should be kept cleared to 0 until the next parity bit is sampled. [7] the tend bit in ssr is not set for a frame for which an error signal indicating an abnormality is received. [8] if an error signal is not sent back from the receiving end, the ers bit in ssr is not set. [9] if an error signal is not sent back from the receiving end, transmission of one frame, including a retransfer, is judged to have been completed, and the tend bit in ssr is set to 1. if the tie bit in scr is enabled at this time, a txi interrupt request is generated. if data transfer by the dmac and dtc by means of the txi source is enabled, the next data can be written to tdr automatically. when data is written to tdr by the dmac or dtc, the tdre bit is automatically cleared to 0. d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds transfer frame n+1 retransferred frame nth transfer frame tdre tend [6] fer/ers transfer to tsr from tdr [7] [9] [8] transfer to tsr from tdr transfer to tsr from tdr figure 17.12 retransfer operation in sci transmit mode
section 17 smart card interface rev. 3.00 jan 11, 2005 page 730 of 1220 rej09b0186-0300o
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 731 of 1220 rej09b0186-0300o section 18 i 2 c bus interface [option] a two-channel i 2 c bus interface is available as an option in the h8s/2643 group. the i 2 c bus interface is not available for the h8s/2643 group. observe the following notes when using this option. for mask-rom versions, a ?w? is added to the part number in products in which this optional function is used. examples: HD6432643wf 18.1 overview a two-channel i 2 c bus interface is available for the h8s/2643 group as an option. the i 2 c bus interface conforms to and provides a subset of the philips i 2 c bus (inter-ic bus) interface functions. the register configuration that controls the i 2 c bus differs partly from the philips configuration, however. each i 2 c bus interface channel uses only one data line (sda) and one clock line (scl) to transfer data, saving board and connector space. 18.1.1 features ? selection of addressing format or non-addressing format ? i 2 c bus format: addressing format with acknowledge bit, for master/slave operation ? serial format: non-addressing format without acknowledge bit, for master operation only ? conforms to philips i 2 c bus interface (i 2 c bus format) ? two ways of setting slave address (i 2 c bus format) ? start and stop conditions generated automatically in master mode (i 2 c bus format) ? selection of acknowledge output levels when receiving (i 2 c bus format) ? automatic loading of acknowledge bit when transmitting (i 2 c bus format) ? wait function in master mode (i 2 c bus format) ? a wait can be inserted by driving the scl pin low after data transfer, excluding acknowledgement. the wait can be cleared by clearing the interrupt flag. ? wait function in slave mode (i 2 c bus format) ? a wait request can be generated by driving the scl pin low after data transfer, excluding acknowledgement. the wait request is cleared when the next transfer becomes possible.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 732 of 1220 rej09b0186-0300o ? three interrupt sources ? data transfer end (including transmission mode transition with i 2 c bus format and address reception after loss of master arbitration) ? address match: when any slave address matches or the general call address is received in slave receive mode (i 2 c bus format) ? stop condition detection ? selection of 16 internal clocks (in master mode) ? direct bus drive (with scl and sda pins) ? two pins?p35/scl0 and p34/sda0?(normally nmos push-pull outputs) function as nmos open-drain outputs when the bus drive function is selected. ? two pins?p33/scl1 and p32/sda1?(normally cmos pins) function as nmos-only outputs when the bus drive function is selected. 18.1.2 block diagram figure 18.1 shows a block diagram of the i 2 c bus interface. figure 18.2 shows an example of i/o pin connections to external circuits. channel 0 i/o pins are nmos open drains, and it is possible to apply voltages in excess of the power supply (pv cc ) voltage for this lsi. set the upper limit of voltage applied to the power supply (pv cc ) power supply range + 0.3 v, i.e. 5.8 v. channel 1 i/o pins are driven solely by nmos, so in terms of appearance they carry out the same operations as an nmos open drain. however, the voltage which can be applied to the i/o pins depends on the voltage of the power supply (pv cc ) of this lsi.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 733 of 1220 rej09b0186-0300o ps noise canceler noise canceler clock control bus state decision circuit arbitration decision circuit output data control circuit address comparator sar, sarx interrupt generator icdrs icdrr icdrt icsr icmr iccr internal data bus interrupt request scl sda legend: iccr: icmr: icsr: icdr: sar: sarx: ps: i 2 c bus control register i 2 c bus mode register i 2 c bus status register i 2 c bus data register slave address register second slave address register x prescaler figure 18.1 block diagram of i 2 c bus interface
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 734 of 1220 rej09b0186-0300o scl in scl out sda in sda out (slave 1) scl sda scl in scl out sda in sda out (slave 2) scl sda scl in scl out sda in sda out (master) h8s/2643 group chip scl sda v dd pvcc2 scl sda figure 18.2 i 2 c bus interface connections (example: h8s/2643 group chip as master) 18.1.3 input/output pins table 18.1 summarizes the input/output pins used by the i 2 c bus interface. table 18.1 i 2 c bus interface pins channel name abbreviation i/o function 0 serial clock scl0 i/o iic0 serial clock input/output serial data sda0 i/o iic0 serial data input/output 1 serial clock scl1 i/o iic1 serial clock input/output serial data sda1 i/o iic1 serial data input/output note: in the text, the channel subscript is omitted, and only scl and sda are used. 18.1.4 register configuration table 18.2 summarizes the registers of the i 2 c bus interface.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 735 of 1220 rej09b0186-0300o table 18.2 register configuration channel name abbreviation r/w initial value address * 1 0i 2 c bus control register iccr0 r/w h'01 h 'ff78 * 3 i 2 c bus status register icsr0 r/w h'00 h'ff79 * 3 i 2 c bus data register icdr0 r/w ? h 'ff7e * 2 * 3 i 2 c bus mode register icmr0 r/w h'00 h'ff7f * 2 * 3 slave address register sar0 r/w h'00 h'ff7f * 2 * 3 second slave address register sarx0 r/w h'01 h'ff7e * 2 * 3 1i 2 c bus control register iccr1 r/w h'01 h 'ff80 * 3 i 2 c bus status register icsr1 r/w h'00 h'ff81 * 3 i 2 c bus data register icdr1 r/w ? h 'ff86 * 2 * 3 i 2 c bus mode register icmr1 r/w h'00 h'ff87 * 2 * 3 slave address register sar1 r/w h'00 h'ff87 * 2 * 3 second slave address register sarx1 r/w h'01 h'ff86 * 2 * 3 common serial control register x scrx r/w h'00 h'fdb4 ddc switch register ddcswr r/w h'0f h'fdb5 module stop control register b mstpcrb r/w h'ff h'fde9 notes: 1. lower 16 bits of the address. 2. the register that can be written or read depends on the ice bit in the i 2 c bus control register. the slave address register can be accessed when ice = 0, and the i 2 c bus mode register can be accessed when ice = 1. 3. the i 2 c bus interface registers are assigned to the same addresses as other registers. register selection is performed by means of the iice bit in the serial control register x (scrx).
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 736 of 1220 rej09b0186-0300o 18.2 register descriptions 18.2.1 i 2 c bus data register (icdr) bit : initial value : r/w : 7 icdr7 ? r/w 6 icdr6 ? r/w 5 icdr5 ? r/w 4 icdr4 ? r/w 3 icdr3 ? r/w 0 icdr0 ? r/w 2 icdr2 ? r/w 1 icdr1 ? r/w ? icdrr bit : initial value : r/w : 7 icdrr7 ? r 6 icdrr6 ? r 5 icdrr5 ? r 4 icdrr4 ? r 3 icdrr3 ? r 0 icdrr0 ? r 2 icdrr2 ? r 1 icdrr1 ? r ? icdrs bit : initial value : r/w : 7 icdrs7 ? ? 6 icdrs6 ? ? 5 icdrr5 ? ? 4 icdrs4 ? ? 3 icdrs3 ? ? 0 icdrs0 ? ? 2 icdrs2 ? ? 1 icdrs1 ? ? ? icdrt bit : initial value : r/w : 7 icdrt7 ? w 6 icdrt6 ? w 5 icdrt5 ? w 4 icdrt4 ? w 3 icdrt3 ? w 0 icdrt0 ? w 2 icdrt2 ? w 1 icdrt1 ? w ? tdre, rdrf (internal flags) bit : initial value : r/w : ? rdrf 0 ? ? tdre 0 ? icdr is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when r eceiving. icdr is divided internally into a shift register (icdrs), receive buffer (icdrr), and transmit buffer (icdrt). icdrs cannot be read or
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 737 of 1220 rej09b0186-0300o written by the cpu, icdrr is read-only, and icdrt is write-only. data transfers among the three registers are performed automatically in coordination with changes in the bus state, and affect the status of internal flags such as tdre and rdrf. if iic is in transmit mode and the next data is in icdrt (the tdre flag is 0) following transmission/reception of one frame of data using icdrs, data is transferred automatically from icdrt to icdrs. if iic is in receive mode and no previous data remains in icdrr (the rdrf flag is 0) following transmission/reception of one frame of data using icdrs, data is transferred automatically from icdrs to icdrr. if the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. transmit data should be written justified toward the msb side when mls = 0, and toward the lsb side when mls = 1. receive data bits read from the lsb side should be treated as valid when mls = 0, and bits read from the msb side when mls = 1. icdr is assigned to the same address as sarx, and can be written and read only when the ice bit is set to 1 in iccr. the value of icdr is undefined after a reset. the tdre and rdrf flags are set and cleared under the conditions shown below. setting the tdre and rdrf flags affects the status of the interrupt flags.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 738 of 1220 rej09b0186-0300o tdre description 0 the next transmit data is in icdr (icdrt), or transmission cannot (initial value) be started [clearing conditions] ? when transmit data is written in icdr (icdrt) in transmit mode (trs = 1) ? when a stop condition is detected in the bus line state after a stop condition is issued with the i 2 c bus format or serial format selected ? when a stop condition is detected with the i 2 c bus format selected ? in receive mode (trs = 0) (a 0 write to trs during transfer is valid after reception of a frame containing an acknowledge bit) 1 the next transmit data can be written in icdr (icdrt) [setting conditions] ? in transmit mode (trs = 1), when a start condition is detected in the bus line state after a start condition is issued in master mode with the i 2 c bus format or serial format selected ? when using formatless mode in transmit mode (trs = 1) ? when data is transferred from icdrt to icdrs (data transfer from icdrt to icdrs when trs = 1 and tdre = 0, and icdrs is empty) ? when a switch is made from receive mode (trs = 0) to transmit mode (trs = 1 ) after detection of a start condition rdrf description 0 the data in icdr (icdrr) is invalid (initial value) [clearing condition] ? when icdr (icdrr) receive data is read in receive mode 1 the icdr (icdrr) receive data can be read [setting condition] ? when data is transferred from icdrs to icdrr (data transfer from icdrs to icdrr in case of normal termination with trs = 0 and rdrf = 0)
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 739 of 1220 rej09b0186-0300o 18.2.2 slave address register (sar) bit : initial value : r/w : 7 sva6 0 r/w 6 sva5 0 r/w 5 sva4 0 r/w 4 sva3 0 r/w 3 sva2 0 r/w 0 fs 0 r/w 2 sva1 0 r/w 1 sva0 0 r/w sar is an 8-bit readable/writable register that stores the slave address and selects the communication format. when the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of sar match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. sar is assigned to the same address as icmr, and can be written and read only when the ice bit is cleared to 0 in iccr. sar is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 1?slave address (sva6 to sva0): set a unique address in bits sva6 to sva0, differing from the addresses of other slave devices connected to the i 2 c bus. bit 0?format select (fs): used together with the fsx bit in sarx to select the communication format. ? i 2 c bus format: addressing format with acknowledge bit ? synchronous serial format: non-addressing format without acknowledge bit, for master mode only the fs bit also specifies whether or not sar slave address recognition is performed in slave mode.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 740 of 1220 rej09b0186-0300o sar bit 0 sarx bit 0 fs fsx operating mode 00i 2 c bus format ? sar and sarx slave addresses recognized 1i 2 c bus format ? sar slave address recognized ? sarx slave address ignored (initial value) 10i 2 c bus format ? sar slave address ignored ? sarx slave address recognized 1 synchronous serial format ? sar and sarx slave addresses ignored 18.2.3 second slave address register (sarx) bit : initial value : r/w : 7 svax6 0 r/w 6 svax5 0 r/w 5 svax4 0 r/w 4 svax3 0 r/w 3 svax2 0 r/w 0 fsx 1 r/w 2 svax1 0 r/w 1 svax0 0 r/w sarx is an 8-bit readable/writable register that stores the second slave address and selects the communication format. when the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of sarx match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. sarx is assigned to the same address as icdr, and can be written and read only when the ice bit is cleared to 0 in iccr. sarx is initialized to h'01 by a reset and in hardware standby mode. bits 7 to 1?second slave address (svax6 to svax0): set a unique address in bits svax6 to svax0, differing from the addresses of other slave devices connected to the i 2 c bus. bit 0?format select x (fsx): used together with the fs bit in sar to select the communication format. ? i 2 c bus format: addressing format with acknowledge bit ? synchronous serial format: non-addressing format without acknowledge bit, for master mode only
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 741 of 1220 rej09b0186-0300o the fsx bit also specifies whether or not sarx slave address recognition is performed in slave mode. for details, see the description of the fs bit in sar. 18.2.4 i 2 c bus mode register (icmr) bit : initial value : r/w : 7 mls 0 r/w 6 wait 0 r/w 5 cks2 0 r/w 4 cks1 0 r/w 3 cks0 0 r/w 0 bc0 0 r/w 2 bc2 0 r/w 1 bc1 0 r/w icmr is an 8-bit readable/writable register that selects whether the msb or lsb is transferred first, performs master mode wait control, and selects the master mode transfer clock frequency and the transfer bit count. icmr is assigned to the same address as sar. icmr can be written and read only when the ice bit is set to 1 in iccr. icmr is initialized to h'00 by a reset and in hardware standby mode. bit 7?msb-first/lsb-first select (mls): selects whether data is transferred msb-first or lsb-first. if the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. transmit data should be written justified toward the msb side when mls = 0, and toward the lsb side when mls = 1. receive data bits read from the lsb side should be treated as valid when mls = 0, and bits read from the msb side when mls = 1. do not set this bit to 1 when the i 2 c bus format is used. bit 7 mls description 0 msb-first (initial value) 1 lsb-first
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 742 of 1220 rej09b0186-0300o bit 6?wait insertion bit (wait): selects whether to insert a wait between the transfer of data and the acknowledge bit, in master mode with the i 2 c bus format. when wait is set to 1, after the fall of the clock for the final data bit, the iric flag is set to 1 in iccr, and a wait state begins (with scl at the low level). when the iric flag is cleared to 0 in iccr, the wait ends and the acknowledge bit is transferred. if wait is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. the iric flag in iccr is set to 1 on completion of the acknowledge bit transfer, regardless of the wait setting. the setting of this bit is invalid in slave mode. bit 6 wait description 0 data and acknowledge bits transferred consecutively (initial value) 1 wait inserted between data and acknowledge bits
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 743 of 1220 rej09b0186-0300o bits 5 to 3?serial clock select (cks2 to cks0): these bits, together with the iicx1 (channel 1) or iicx0 (channel 0) bit in the scrx register, select the serial clock frequency in master mode. they should be set according to the required transfer rate. scrx bit 5 or 6 bit 5 bit 4 bit 3 transfer rate iicx cks2 cks1 cks0 clock = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz = 25 mhz 00 0 0 /28 179 khz 286 khz 357 khz 571 khz * 714 khz * 893 khz * 1 /40 125 khz 200 khz 250 khz 400 khz 500 khz * 625 khz * 10 /48 104 khz 167 khz 208 khz 333 khz 417 khz * 521 khz * 1 /64 78.1 khz 125 khz 156 khz 250 khz 313 khz 391 khz 100 /80 62.5 khz 100 khz 125 khz 200 khz 250 khz 313 khz 1 /100 50.0 khz 80.0 khz 100 khz 160 khz 200 khz 250 khz 10 /112 44.6 khz 71.4 khz 89.3 khz 143 khz 179 khz 223 khz 1 /128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 195 khz 10 0 0 /56 89.3 khz 143 khz 179 khz 286 khz 357 khz 446 khz 1 /80 62.5 khz 100 khz 125 khz 200 khz 250 khz 313 khz 10 /96 52.1 khz 83.3 khz 104 khz 167 khz 208 khz 260 khz 1 /128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 195 khz 100 /160 31.3 khz 50.0 khz 62.5 khz 100 khz 125 khz 156 khz 1 /200 25.0 khz 40.0 khz 50.0 khz 80.0 khz 100 khz 125 khz 10 /224 22.3 khz 35.7 khz 44.6 khz 71.4 khz 89.3 khz 112 khz 1 /256 19.5 khz 31.3 khz 39.1 khz 62.5 khz 78.1 khz 97.7 khz note: * outside the allowable range for the i 2 c bus interface standard (normal mode: max. 100 khz, high-speed mode: max. 400 khz). bits 2 to 0?bit counter (bc2 to bc0): bits bc2 to bc0 specify the number of bits to be transferred next. with the i 2 c bus format (when the fs bit in sar or the fsx bit in sarx is 0), the data is transferred with one addition acknowledge bit. bit bc2 to bc0 settings should be made during an interval between transfer frames. if bits bc2 to bc0 are set to a value other than 000, the setting should be made while the scl line is low. the bit counter is initialized to 000 by a reset and when a start condition is detected. the value returns to 000 at the end of a data transfer, including the acknowledge bit.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 744 of 1220 rej09b0186-0300o bit 2 bit 1 bit 0 bits/frame bc2 bc1 bc0 synchronous serial format i 2 c bus format 0 0 0 8 9 (initial value) 11 2 10 2 3 13 4 100 4 5 15 6 10 6 7 17 8 18.2.5 i 2 c bus control register (iccr) bit : initial value : r/w : note: * onl y 0 can be written, for fla g clearin g . 7 ice 0 r/w 6 ieic 0 r/w 5 mst 0 r/w 4 trs 0 r/w 3 acke 0 r/w 0 scp 1 w 2 bbsy 0 r/w 1 iric 0 r/(w) * iccr is an 8-bit readable/writable register that enables or disables the i 2 c bus interface, enables or disables interrupts, selects master or slave mode and transmission or reception, enables or disables acknowledgement, confirms the i 2 c bus interface bus status, issues start/stop conditions, and performs interrupt flag confirmation. iccr is initialized to h'01 by a reset and in hardware standby mode. bit 7?i 2 c bus interface enable (ice): selects whether or not the i 2 c bus interface is to be used. when ice is set to 1, port pins function as scl and sda input/output pins and transfer operations are enabled. when ice is cleared to 0, the i 2 c bus interface module is halted and its internal states are cleared. the sar and sarx registers can be accessed when ice is 0. the icmr and icdr registers can be accessed when ice is 1.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 745 of 1220 rej09b0186-0300o bit 7 ice description 0i 2 c bus interface module disabled, with scl and sda signal pins set to port function i 2 c bus interface module internal states initialized sar and sarx can be accessed (initial value) 1 i 2 c bus interface module enabled for transfer operations (pins scl and sda are driving the bus) icmr and icdr can be accessed bit 6?i 2 c bus interface interrupt enable (ieic): enables or disables interrupts from the i 2 c bus interface to the cpu. bit 6 ieic description 0 interrupts disabled (initial value) 1 interrupts enabled bit 5?master/slave select (mst) bit 4?transmit/receive select (trs) mst selects whether the i 2 c bus interface operates in master mode or slave mode. trs selects whether the i 2 c bus interface operates in transmit mode or receive mode. in master mode with the i 2 c bus format, when arbitration is lost, mst and trs are both reset by hardware, causing a transition to slave receive mode. in slave receive mode with the addressing format (fs = 0 or fsx = 0), hardware automatically selects transmit or receive mode according to the r/w bit in the first frame after a start condition. modification of the trs bit during transfer is deferred until transfer of the frame containing the acknowledge bit is completed, and the changeover is made after completion of the transfer. mst and trs select the operating mode as follows.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 746 of 1220 rej09b0186-0300o bit 5 bit 4 mst trs operating mode 0 0 slave receive mode (initial value) 1 slave transmit mode 1 0 master receive mode 1 master transmit mode bit 5 mst description 0 slave mode [clearing conditions] 1. when 0 is written by software 2. when bus arbitration is lost after transmission is started in i 2 c bus format master mode (initial value) 1 master mode [setting conditions] 1. when 1 is written by software (in cases other than clearing condition 2) 2. when 1 is written in mst after reading mst = 0 (in case of clearing condition 2) bit 4 trs description 0 receive mode [clearing conditions] 1. when 0 is written by software (in cases other than setting condition 3) 2. when 0 is written in trs after reading trs = 1 (in case of clearing condition 3) 3. when bus arbitration is lost after transmission is started in i 2 c bus format master mode (initial value) 1 transmit mode [setting conditions] 1. when 1 is written by software (in cases other than clearing condition 3) 2. when 1 is written in trs after reading trs = 0 (in case of clearing condition 3) 3. when a 1 is received as the r/w bit of the first frame in i 2 c bus format slave mode
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 747 of 1220 rej09b0186-0300o bit 3?acknowledge bit judgement selection (acke): specifies whether the value of the acknowledge bit returned from the receiving device when using the i 2 c bus format is to be ignored and continuous transfer is performed, or transfer is to be aborted and error handling, etc., performed if the acknowledge bit is 1. when the acke bit is 0, the value of the received acknowledge bit is not indicated by the ackb bit, which is always 0. in the h8s/2643 group, the dtc can be used to perform continuous transfer. the dtc is activated when the irtr interrupt flag is set to 1 (irtr is one of two interrupt flags, the other being iric). when the acke bit is 0, the tdre, iric, and irtr flags are set on completion of data transmission, regardless of the value of the acknowledge bit. when the acke bit is 1, the tdre, iric, and irtr flags are set on completion of data transmission when the acknowledge bit is 0, and the iric flag alone is set on completion of data transmission when the acknowledge bit is 1. when the dtc is activated, the tdre, iric, and irtr flags are cleared to 0 after the specified number of data transfers have been executed. consequently, interrupts are not generated during continuous data transfer, but if data transmission is completed with a 1 acknowledge bit when the acke bit is set to 1, the dtc is not activated and an interrupt is generated, if enabled. depending on the receiving device, the acknowledge bit may be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance. bit 3 acke description 0 the value of the acknowledge bit is ignored, and continuous transfer is performed (initial value) 1 if the acknowledge bit is 1, continuous transfer is interrupted bit 2?bus busy (bbsy): the bbsy flag can be read to check whether the i 2 c bus (scl, sda) is busy or free. in master mode, this bit is also used to issue start and stop conditions. a high-to-low transition of sda while scl is high is recognized as a start condition, setting bbsy to 1. a low-to-high transition of sda while scl is high is recognized as a stop condition, clearing bbsy to 0. to issue a start condition, use a mov instruction to write 1 in bbsy and 0 in scp. a retransmit start condition is issued in the same way. to issue a stop condition, use a mov instruction to write 0 in bbsy and 0 in scp. it is not possible to write to bbsy in slave mode; the i 2 c bus interface must be set to master transmit mode before issuing a start condition. mst and trs should both be set to 1 before writing 1 in bbsy and 0 in scp.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 748 of 1220 rej09b0186-0300o bit 2 bbsy description 0 bus is free [clearing condition] ? when a stop condition is detected (initial value) 1 bus is busy [setting condition] ? when a start condition is detected bit 1?i 2 c bus interface interrupt request flag (iric): indicates that the i 2 c bus interface has issued an interrupt request to the cpu. iric is set to 1 at the end of a data transfer, when a slave address or general call address is detected in slave receive mode, when bus arbitration is lost in master transmit mode, and when a stop condition is detected. iric is set at different times depending on the fs bit in sar and the wait bit in icmr. see section 18.3.6, iric setting timing and scl control. the c onditions under which iric is set also differ depending on the setting of the acke bit in iccr. iric is cleared by reading iric after it has been set to 1, then writing 0 in iric. when the dtc is used, iric is cleared automatically and transfer can be performed continuously without cpu intervention.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 749 of 1220 rej09b0186-0300o bit 1 iric description 0 waiting for transfer, or transfer in progress (initial value) [clearing conditions] ? when 0 is written in iric after reading iric = 1 ? when icdr is written or read by the dtc (when the tdre or rdrf flag is cleared to 0) (this is not always a clearing condition; see the description of dtc operation for details) 1 interrupt requested [setting conditions] i 2 c bus format master mode ? when a start condition is detected in the bus line state after a start condition is issued (when the tdre flag is set to 1 because of first frame transmission) ? when a wait is inserted between the data and acknowledge bit when wait = 1 ? at the end of data transfer (at the rise of the 9th transmit/receive clock pulse, or at the fall of the 8th transmit/receive clock pulse when using wait insertion) ? when a slave address is received after bus arbitration is lost (when the al flag is set to 1) ? when 1 is received as the acknowledge bit when the acke bit is 1 (when the ackb bit is set to 1) i 2 c bus format slave mode ? when the slave address ( sva, svax) matches (when the aas and aasx flags are set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the tdre or rdrf flag is set to 1) ? when the general call address is detected (when fs = 0 and the adz flag is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the tdre or rdrf flag is set to 1) ? when 1 is received as the acknowledge bit when the acke bit is 1 (when the ackb bit is set to 1) ? when a stop condition is detected (when the stop or estp flag is set to 1)
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 750 of 1220 rej09b0186-0300o bit 1 iric description 1 synchronous serial format ? at the end of data transfer (when the tdre or rdrf flag is set to 1) ? when a start condition is detected with serial format selected when any other condition arises in which the tdre or rdrf flag is set to 1 when, with the i 2 c bus format selected, iric is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set iric to 1. although each source has a corresponding flag, caution is needed at the end of a transfer. when the tdre or rdrf internal flag is set, the readable irtr flag may or may not be set. the irtr flag (the dtc start request flag) is not set at the end of a data transfer up to detection of a retransmission start condition or stop condition after a slave address (sva) or general call address match in i 2 c bus format slave mode. even when the iric flag and irtr flag are set, the tdre or rdrf internal flag may not be set. the iric and irtr flags are not cleared at the end of the specified number of transfers in continuous transfer using the dtc. the tdre or rdrf flag is cleared, however, since the specified number of icdr reads or writes have been completed. table 18.3 shows the relationship between the flags and the transfer states.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 751 of 1220 rej09b0186-0300o table 18.3 flags and transfer states mst trs bbsy estp stop irtr aasx al aas adz ackb state 1/0 1/0 0 0 0 0 0 0 0 0 0 idle state (flag clearing required) 11000000000 start condition issuance 11100100000 start condition established 1 1/0 1 0 0 0 0 0 0 0 0/1 master mode wait 11/0100100000/1master mode transmit/receive end 0 0 1 0 0 0 1/0 1 1/0 1/0 0 arbitration lost 00100000100 sar match by first frame in slave mode 0 0 1 0 0 0 0 0 1 1 0 general call address match 00100010000 sarx match 0 1/0 1 0 0 0 0 0 0 0 0/1 slave mode transmit/receive end (except after sarx match) 0 0 1/0 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 slave mode transmit/receive end (after sarx match) 0 1/0 0 1/0 1/0 0 0 0 0 0 0/1 stop condition detected bit 0?start condition/stop condition prohibit (scp): controls the issuing of start and stop conditions in master mode. to issue a start condition, write 1 in bbsy and 0 in scp. a retransmit start condition is issued in the same way. to issue a stop condition, write 0 in bbsy and 0 in scp. this bit is always read as 1. if 1 is written, the data is not stored. bit 0 scp description 0 writing 0 issues a start or stop condition, in combination with the bbsy flag 1 reading always returns a value of 1 writing is ignored (initial value)
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 752 of 1220 rej09b0186-0300o 18.2.6 i 2 c bus status register (icsr) bit : initial value : r/w : note: * onl y 0 can be written, for fla g clearin g . 7 estp 0 r/(w) * 6 stop 0 r/(w) * 5 irtr 0 r/(w) * 4 aasx 0 r/(w) * 3 al 0 r/(w) * 0 ackb 0 r/w 2 aas 0 r/(w) * 1 adz 0 r/(w) * icsr is an 8-bit readable/writable register that performs flag confirmation and acknowledge confirmation and control. icsr is initialized to h'00 by a reset and in hardware standby mode. bit 7?error stop condition detection flag (estp): indicates that a stop condition has been detected during frame transfer in i 2 c bus format slave mode. bit 7 estp description 0 no error stop condition [clearing conditions] ? when 0 is written in estp after reading estp = 1 ? when the iric flag is cleared to 0 (initial value) 1 ? in i 2 c bus format slave mode error stop condition detected [setting conditions] ? when a stop condition is detected during frame transfer ? in other modes no meaning
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 753 of 1220 rej09b0186-0300o bit 6?normal stop condition detection flag (stop): indicates that a stop condition has been detected after completion of frame transfer in i 2 c bus format slave mode. bit 6 stop description 0 no normal stop condition [clearing conditions] ? when 0 is written in stop after reading stop = 1 ? when the iric flag is cleared to 0 (initial value) 1 ? in i 2 c bus format slave mode normal stop condition detected [setting conditions] ? when a stop condition is detected after completion of frame transfer ? in other modes no meaning bit 5?i 2 c bus interface continuous transmission/reception interrupt request flag (irtr): indicates that the i 2 c bus interface has issued an interrupt request to the cpu, and the source is completion of reception/transmission of one frame in continuous transmission/reception for which dtc activation is possible. when the irtr flag is set to 1, the iric flag is also set to 1 at the same time. irtr flag setting is performed when the tdre or rdrf flag is set to 1. irtr is cleared by reading irtr after it has been set to 1, then writing 0 in irtr. irtr is also cleared automatically when the iric flag is cleared to 0.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 754 of 1220 rej09b0186-0300o bit 5 irtr description 0 waiting for transfer, or transfer in progress [clearing conditions] ? when 0 is written in irtr after reading irtr = 1 ? when the iric flag is cleared to 0 (initial value) 1 continuous transfer state [setting conditions] ? in i 2 c bus interface slave mode when the tdre or rdrf flag is set to 1 when aasx = 1 ? in other modes when the tdre or rdrf flag is set to 1 bit 4?second slave address recognition flag (aasx): in i 2 c bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits svax6 to svax0 in sarx. aasx is cleared by reading aasx after it has been set to 1, then writing 0 in aasx. aasx is also cleared automatically when a start condition is detected. bit 4 aasx description 0 second slave address not recognized [clearing conditions] ? when 0 is written in aasx after reading aasx = 1 ? when a start condition is detected ? in master mode (initial value) 1 second slave address recognized [setting condition] ? when the second slave address is detected in slave receive mode and fsx = 0
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 755 of 1220 rej09b0186-0300o bit 3?arbitration lost (al): this flag indicates that arbitration was lost in master mode. the i 2 c bus interface monitors the bus. when two or more master devices attempt to seize the bus at nearly the same time, if the i 2 c bus interface detects data differing from the data it sent, it sets al to 1 to indicate that the bus has been taken by another master. al is cleared by reading al after it has been set to 1, then writing 0 in al. in addition, al is reset automatically by write access to icdr in transmit mode, or read access to icdr in receive mode. bit 3 al description 0 bus arbitration won [clearing conditions] ? when icdr data is written (transmit mode) or read (receive mode) ? when 0 is written in al after reading al = 1 (initial value) 1 arbitration lost [setting conditions] ? if the internal sda and sda pin disagree at the rise of scl in master transmit mode ? if the internal scl line is high at the fall of scl in master transmit mode bit 2?slave address recognition flag (aas): in i 2 c bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits sva6 to sva0 in sar, or if the general call address (h'00) is detected. aas is cleared by reading aas after it has been set to 1, then writing 0 in aas. in addition, aas is reset automatically by write access to icdr in transmit mode, or read access to icdr in receive mode.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 756 of 1220 rej09b0186-0300o bit 2 aas description 0 slave address or general call address not recognized [clearing conditions] ? when icdr data is written (transmit mode) or read (receive mode) ? when 0 is written in aas after reading aas = 1 ? in master mode (initial value) 1 slave address or general call address recognized [setting condition] ? when the slave address or general call address is detected in slave receive mode and fs = 0 bit 1?general call address recognition flag (adz): in i 2 c bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (h'00). adz is cleared by reading adz after it has been set to 1, then writing 0 in adz. in addition, adz is reset automatically by write access to icdr in transmit mode, or read access to icdr in receive mode. bit 1 adz description 0 general call address not recognized [clearing conditions] ? when icdr data is written (transmit mode) or read (receive mode) ? when 0 is written in adz after reading adz = 1 ? in master mode (initial value) 1 general call address recognized [setting condition] ? when the general call address is detected in slave receive mode and (fsx = 0 or fs = 0) bit 0?acknowledge bit (ackb): stores acknowledge data. in transmit mode, after the receiving device receives data, it returns acknowledge data, and this data is loaded into ackb. in receive mode, after data has been received, the acknowledge data set in this bit is sent to the transmitting device.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 757 of 1220 rej09b0186-0300o when this bit is read, in transmission (when trs = 1), the value loaded from the bus line (returned by the receiving device) is read. in reception (when trs = 0), the value set by internal software is read. in addition, writing to this bit overwrites the setting for acknowledge data sent when receiving data, regardless of the trs value. in this case the value loaded from the receive device is maintained unchanged, so caution is necessary when using instructions that manipulate the bits in this register. bit 0 ackb description 0 receive mode: 0 is output at acknowledge output timing (initial value) transmit mode: indicates that the receiving device has acknowledged the data (signal is 0) 1 receive mode: 1 is output at acknowledge output timing transmit mode: indicates that the receiving device has not acknowledged the data (signal is 1) 18.2.7 serial control register x (scrx) bit : initial value : r/w : 7 ? 0 r/w 6 iicx1 0 r/w 5 iicx0 0 r/w 4 iice 0 r/w 3 flshe 0 r/w 0 ? 0 r/w 2 ? 0 r/w 1 ? 0 r/w scrx is an 8-bit readable/writable register that controls register access, the i 2 c interface operating mode (when the on-chip iic option is included), and on-chip flash memory control (f- ztat versions). if a module controlled by scrx is not used, do not write 1 to the corresponding bit. scrx is initialized to h'00 by a reset and in hardware standby mode. bit 7?reserved: do not set 1. bit 6?i 2 c transfer select 1 (iicx1): this bit, together with bits cks2 to cks0 in icmr of iic1, selects the transfer rate in master mode. for details, see section 18.2.4, i 2 c bus mode register (icmr).
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 758 of 1220 rej09b0186-0300o bit 5?i 2 c transfer select 0 (iicx0): this bit, together with bits cks2 to cks0 in icmr of iic0, selects the transfer rate in master mode. for details, see section 18.2.4, i 2 c bus mode register (icmr). bit 4?i 2 c master enable (iice): controls cpu access to the i 2 c bus interface data and control registers (iccr, icsr, icdr/sarx, icmr/sar). bit 4 iice description 0 cpu access to i 2 c bus interface data and control registers is disabled (initial value) 1 cpu access to i 2 c bus interface data and control registers is enabled bit 3?flash memory control register enable (flshe): controls the operation of the flash memory in f-ztat versions. for details, see section 22, rom. bits 2 to 0?reserved: do not set 1. 18.2.8 ddc switch register (ddcswr) bit : initial value : r/w : notes: 1. should always be written with 0. 2. always read as 1. 7 ? 0 r/(w) * 1 6 ? 0 r/(w) * 1 5 ? 0 r/(w) * 1 4 ? 0 r/(w) * 1 3 clr3 1 w * 2 0 clr0 1 w * 2 2 clr2 1 w * 2 1 clr1 1 w * 2 ddcswr is an 8-bit readable/writable register that is used to initialize the iic module. ddcswr is initialized to h'0f by a reset and in hardware standby mode. bits 7 to 4?reserved: should always be written with 0. bits 3 to 0?iic clear 3 to 0 (clr3 to clr0): these bits control initialization of the internal state of iic0 and iic1. these bits can only be written to; if read they will always return a value of 1. when a write operation is performed on these bits, a clear signal is generated for the internal latch circuit of the corresponding module(s), and the internal state of the iic module(s) is initialized.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 759 of 1220 rej09b0186-0300o the write data for these bits is not retained. to perform iic clearance, bits clr3 to clr0 must be written to simultaneously using an mov instruction. do not use a bit manipulation instruction such as bclr. when clearing is required again, all the bits must be written to in accordance with the setting. bit 3 bit 2 bit 1 bit 0 clr3 clr2 clr1 clr0 description 00 ?? setting prohibited 1 0 0 setting prohibited 1 iic0 internal latch cleared 1 0 iic1 internal latch cleared 1 iic0 and iic1 internal latches cleared 1 ??? invalid setting
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 760 of 1220 rej09b0186-0300o 18.2.9 module stop control register b (mstpcrb) 7 mstpb7 1 r/w bit : initial value : r/w : 6 mstpb6 1 r/w 5 mstpb5 1 r/w 4 mstpb4 1 r/w 3 mstpb3 1 r/w 2 mstpb2 1 r/w 1 mstpb1 1 r/w 0 mstpb0 1 r/w mstpcrb is an 8-bit readable/writable register that perform module stop mode control. when the mstpb4 or mstpb3 bit is set to 1, operation of the corresponding iic channel is halted at the end of the bus cycle, and a transition is made to module stop mode. for details, see section 24.5, module stop mode. mstpcrb is initialized to h'ff by a power-on reset and in hardware standby mode. it is not initialized by a manual reset and in software standby mode. bit 4?module stop (mstpb4): specifies iic channel 0 module stop mode. bit 4 mstpb4 description 0 iic channel 0 module stop mode is cleared 1 iic channel 0 module stop mode is set (initial value) bit 3?module stop (mstpb3): specifies iic channel 1 module stop mode. bit 3 mstpb3 description 0 iic channel 1 module stop mode is cleared 1 iic channel 1 module stop mode is set (initial value)
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 761 of 1220 rej09b0186-0300o 18.3 operation 18.3.1 i 2 c bus data format the i 2 c bus interface has serial and i 2 c bus formats. the i 2 c bus formats are addressing formats with an acknowledge bit. these are shown in figures 18.3. the first frame following a start condition always consists of 8 bits. the serial format is a non-addressing format with no acknowledge bit. although start and stop conditions must be issued, this format can be used as a synchronous serial format. this is shown in figure 18.4. figure 18.5 shows the i 2 c bus timing. the symbols used in figures 18.3 to 18.5 are explained in table 18.4. s sla r/ w a data a a/ a p 1111 n 7 1 m (a) i 2 c bus format (fs = 0 or fsx = 0) (b) i 2 c bus format (start condition retransmission, fs = 0 or fsx = 0) n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) s sla r/ w a data 111 n1 7 1 m1 s sla r/ w a data a/ a p 111 n2 7 1 m2 11 1 a/ a n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 1) 11 figure 18.3 i 2 c bus data formats (i 2 c bus formats)
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 762 of 1220 rej09b0186-0300o s data data p 11 n 8 1 m fs = 1 and fsx = 1 n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) figure 18.4 i 2 c bus data format (serial format) sda scl s 1-7 sla 8 r/ w 9 a 1-7 data 89 1-7 89 a data p a/ a figure 18.5 i 2 c bus timing table 18.4 i 2 c bus data format symbols legend s start condition. the master device drives sda from high to low while scl is high sla slave address, by which the master device selects a slave device r/ w indicates the direction of data transfer: from the slave device to the master device when r/ w is 1, or from the master device to the slave device when r/ w is 0 a acknowledge. the receiving device (the slave in master transmit mode, or the master in master receive mode) drives sda low to acknowledge a transfer data transferred data. the bit length is set by bits bc2 to bc0 in icmr. the msb-first or lsb-first format is selected by bit mls in icmr p stop condition. the master device drives sda from low to high while scl is high 18.3.2 master transmit operation in i 2 c bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. the transmission procedure and operations are described below. (1) set the ice bit in iccr to 1. set bits mls, wait, and cks2 to cks0 in icmr, and bit iicx in stcr, according to the operating mode.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 763 of 1220 rej09b0186-0300o (2) read the bbsy flag in iccr to confirm that the bus is free, then set bits mst and trs to 1 in iccr to select master transmit mode. next, write 1 to bbsy and 0 to scp. this changes sda from high to low when scl is high, and generates the start condition. the tdre internal flag is then set to 1, and the iric and irtr flags are also set to 1. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. (3) with the i 2 c bus format (when the fs bit in sar or the fsx bit in sarx is 0), the first frame data following the start condition indicates the 7-bit slave address and trans mit/r eceive direction. write the data (slave address + r/ w ) to icdr. the tdre internal flag is then cleared to 0. the written address data is transferred to icdrs, and the tdre internal flag is set to 1 again. this is identified as indicating the end of the transfer, and so the iric flag is cleared to 0. the master device sequentially sends the transmit clock and the data written to icdr using the timing shown in figure 18.6. the selected slave device (i.e. the slave device with the matching slave address) drives sda low at the 9th transmit clock pulse and returns an acknowledge signal. (4) when one frame of data has been transmitted, the iric flag is set to 1 at the rise of the 9th transmit clock pulse. if the tdre internal flag has been set to 1, after one frame has been transmitted scl is automatically fixed low in synchronization with the internal clock until the next transmit data is written. (5) to continue transfer, write the next data to be transmitted into icdr. after the data has been transferred to icdrs and the tdre internal flag has been set to 1, clear the iric flag to 0. transmission of the next frame is performed in synchronization with the internal clock. data can be transmitted sequentially by repeating steps (4) and (5). to end transmission, after clearing the iric flag and transmitting the final data (with no more transmit data in icdrt), write h'ff dummy data to icdr, and then write 0 to bbsy and scp in iccr when the iric flag is set again. this changes sda from low to high when scl is high, and generates the stop condition.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 764 of 1220 rej09b0186-0300o sda (master output) sda (slave output) 2 1 2 1 4 36 58 79 bit 7 slave address bit 6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iric icdrt icdrs tdre scl (master output) start condition issuance interrupt request generation interrupt request generation data 1 address + r/ w data 1 address + r/ w [2] write bbsy = 1 and scp = 0 ( start condition issuance ) [3] icdr write [5] icdr write [5] iric clearance [3] iric clearance user processing slave address data 1 r/w [4] a figure 18.6 example of master transmit mode operation timing (mls = wait = 0) to transmit data continuously: (6) before the rise of the 9th transmit clock pulse for the data being transmitted, clear the iric flag to 0 and then write the next transmit data to icdr. (7) when one frame of data has been transmitted, the iric flag in iccr is set to 1 at the rise of the 9th transmit clock pulse. at the same time, the next transmit data written into icdr (icdrt) is transferred to icdrs, the tdre internal flag is set to 1, and then the next frame is transmitted in synchronization with the internal clock. data can be transmitted continuously by repeating steps (6) and (7).
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 765 of 1220 rej09b0186-0300o sda (master output) sda (slave output) 2 1 23 1 4 36 58 79 bit 7 bit 6 bit 5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iric icdrt icdrs tdre scl (master output) interrupt request generation data 2 data 1 [6] icdr write icdr write [6] icdr write [6] iric clearance [6] iric clearance user processing data 1 data 1 data 2 data 3 data 2 [7] [7] a figure 18.7 example of master transmit mode continuous transmit operation timing (mls = wait = 0) 18.3.3 master receive operation in master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. the slave device transmits data. the reception procedure and operations in master receive mode are described below. (1) clear the trs bit in iccr to 0 to switch from transmit mode to receive mode. also clear the ackb bit in icsr to 0 (acknowledge data setting). (2) when icdr is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. in order to determine the end of reception, the iric flag in iccr must be cleared beforehand. (3) the master device drives sda at the 9th receive clock pulse to return an acknowledge signal. when one frame of data has been received, the iric flag in iccr is set to 1 at the rise of the 9th receive clock pulse. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. if the rdrf internal flag has been cleared to 0, it is set to 1, and the receive operation continues. if reception of the next frame ends before the icdr read/iric flag clearing in (4) is performed, scl is automatically fixed low in synchronization with the internal clock.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 766 of 1220 rej09b0186-0300o (4) read icdr and clear the iric flag in iccr to 0. the rdrf flag is cleared to 0. data can be received continuously by repeating steps (3) and (4). as the rdrf internal flag is cleared to 0 when reception is started after initially switching from master transmit mode to master receive mode, reception of the next frame of data is started automatically. to halt reception, the trs bit must be set to 1 before the rise of the receive clock for the next frame. to halt reception, set the tsr bit to 1, read icdr, then write 0 to bbsy and scp in iccr. this changes sda from low to high when scl is high, and generates the stop condition. sda (master output) sda (slave output) 2 1 2 1 4 36 58 79 9 bit 7 bit 6 bit 5 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 0 iric icdrs icdrr rdrf scl (master output) interrupt request generation master transmit mode master receive mode data 1 [1] trs cleared to 0 [2] icdr read (dummy read) [4] icdr read [4] iric clearance [2] iric clearance user processing data 1 data 1 data 2 [3] a a interrupt request generation figure 18.8 example of master receive mode operation timing (mls = wait = ackb = 0)
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 767 of 1220 rej09b0186-0300o 18.3.4 slave receive operation in slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. the reception procedure and operations in slave receive mode are described below. (1) set the ice bit in iccr to 1. set the mls bit in icmr and the mst and trs bits in iccr according to the operating mode. (2) when the start condition output by the master device is detected, the bbsy flag in iccr is set to 1. (3) when the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. if the 8th data bit (r/ w ) is 0, the trs bit in iccr remains cleared to 0, and slave receive operation is performed. (4) at the 9th clock pulse of the receive frame, the slave device drives sda low and returns an acknowledge signal. at the same time, the iric flag in iccr is set to 1. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. if the rdrf internal flag has been cleared to 0, it is set to 1, and the receive operation continues. if the rdrf internal flag has been set to 1, the slave device drives scl low from the fall of the receive clock until data is read into icdr. (5) read icdr and clear the iric flag in iccr to 0. the rdrf flag is cleared to 0. receive operations can be performed continuously by repeating steps (4) and (5). when sda is changed from low to high when scl is high, and the stop condition is detected, the bbsy flag in iccr is cleared to 0.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 768 of 1220 rej09b0186-0300o sda (master output) sda (slave output) 2 1 2 1 4 36 58 79 bit 7 bit 6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iric icdrs icdrr rdrf scl (master output) start condition issuance scl (slave output) interrupt request generation address + r/ w address + r/ w [5] icdr read [5] iric clearance user processing slave address data 1 [4] a r/ w figure 18.9 example of slave receive mode operation timing (1) (mls = ackb = 0)
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 769 of 1220 rej09b0186-0300o sda (master output) sda (slave output) 2 14 36 58 79 8 79 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 1 bit 0 iric icdrs icdrr rdrf scl (master output) scl (slave output) interrupt request generatio n interrupt request generation data 2 data 2 data 1 data 1 [5] icdr read [5] iric clearance user processing data 2 data 1 [4] [4] a a figure 18.10 example of slave receive mode operation timing (2) (mls = ackb = 0) 18.3.5 slave transmit operation in slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. the transmission procedure and operations in slave transmit mode are described below. (1) set the ice bit in iccr to 1. set the mls bit in icmr and the mst and trs bits in iccr according to the operating mode. (2) when the slave address matches in the first frame following detection of the start condition, the slave device drives sda low at the 9th clock pulse and returns an acknowledge signal. at the same time, the iric flag in iccr is set to 1. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. if the 8th data bit (r/ w ) is 1, the trs bit in iccr is set to 1, and the mode changes to slave transmit mode automatically. the tdrf flag is set to 1. the slave device drives scl low from the fall of the transmit clock until icdr data is written.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 770 of 1220 rej09b0186-0300o (3) after clearing the iric flag to 0, write data to icdr. the tdre internal flag is cleared to 0. the written data is transferred to icdrs, and the tdre internal flag and the iric and irtr flags are set to 1 again. after clearing the iric flag to 0, write the next data to icdr. the slave device sequentially sends the data written into icdr in accordance with the clock output by the master device at the timing shown in figure 18.11. (4) when one frame of data has been transmitted, the iric flag in iccr is set to 1 at the rise of the 9th transmit clock pulse. if the tdre internal flag has been set to 1, this slave device drives scl low from the fall of the transmit clock until data is written to icdr. the master device drives sda low at the 9th clock pulse, and returns an acknowledge signal. as this acknowledge signal is stored in the ackb bit in icsr, this bit can be used to determine whether the transfer operation was performed normally. when the tdre internal flag is 0, the data written into icdr is transferred to icdrs, transmission is started, and the tdre internal flag and the iric and irtr flags are set to 1 again. (5) to continue transmission, clear the iric flag to 0, then write the next data to be transmitted into icdr. the tdre flag is cleared to 0. transmit operations can be performed continuously by repeating steps (4) and (5). to end transmission, write h'ff to icdr to release sda on the slave side. when sda is changed from low to high when scl is high, and the stop condition is detected, the bbsy flag in iccr is cleared to 0.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 771 of 1220 rej09b0186-0300o sda (slave output) sda (slave output) scl (slave output) 2 1 2 1 4 36 58 79 9 8 bit 7 bit 6 bit 5 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 0 iric icdrs icdrt tdre scl (master output) interrupt request generation interrupt request generation interrupt request generation slave receive mode slave transmit mode data 1 data 2 [3] iric clearance [5] iric clearance [3] icdr write [3] icdr write [3] icdr write user processing data 1 data 1 data 2 data 2 a r/ w a [3] [2] figure 18.11 example of slave transmit mode operation timing (mls = 0)
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 772 of 1220 rej09b0186-0300o 18.3.6 iric setting timing and scl control the interrupt request flag (iric) is set at different times depending on the wait bit in icmr, the fs bit in sar, and the fsx bit in sarx. if the tdre or rdrf internal flag is set to 1, scl is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. figure 18.12 shows the iric set t iming and scl control. (a) when wait = 0, and fs = 0 or fsx = 0 (i 2 c bus format, no wait) scl sda iric user processing clear iric write to icdr (transmit) or read icdr (receive) 1 a 8 1 1 a 7 1 89 7 (b) when wait = 1, and fs = 0 or fsx = 0 (i 2 c bus format, wait inserted) scl sda iric user processing clear iric clear iric write to icdr (transmit) or read icdr (receive) scl sda iric user processing (c) when fs = 1 and fsx = 1 (synchronous serial format) clear iric write to icdr (transmit) or read icdr (receive) 8 89 8 7 1 8 7 1 figure 18.12 iric setting timing and scl control
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 773 of 1220 rej09b0186-0300o 18.3.7 operation using the dtc the i 2 c bus format provides for selection of the slave device and transfer direction by means of the slave address and the r/ w bit, confirmation of reception with the acknowledge bit, indication of the last frame, and so on. therefore, continuous data transfer using the dtc must be carried out in conjunction with cpu processing by means of interrupts. table 18.5 shows some examples of processing using the dtc. these examples assume that the number of transfer data bytes is known in slave mode. table 18.5 examples of operation using the dtc item master transmit mode master receive mode slave transmit mode slave receive mode slave address + r/ w bit transmission/ reception transmission by dtc (icdr write) transmission by cpu (icdr write) reception by cpu (icdr read) reception by cpu (icdr read) dummy data read ? processing by cpu (icdr read) ?? actual data transmission/ reception transmission by dtc (icdr write) reception by dtc (icdr read) transmission by dtc (icdr write) reception by dtc (icdr read) dummy data (h'ff) write ?? processing by dtc (icdr write) ? last frame processing not necessary reception by cpu (icdr read) not necessary reception by cpu (icdr read) transfer request processing after last frame processing 1st time: clearing by cpu 2nd time: end condition issuance by cpu not necessary automatic clearing on detection of end condition during transmission of dummy data (h'ff) not necessary setting of number of dtc transfer data frames transmission: actual data count + 1 (+1 equivalent to slave address + r/ w bits) reception: actual data count transmission: actual data count + 1 (+1 equivalent to dummy data (h'ff)) reception: actual data count
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 774 of 1220 rej09b0186-0300o 18.3.8 noise canceler the logic levels at the scl and sda pins are routed through noise cancelers before being latched internally. figure 18.13 shows a block diagram of the noise canceler circuit. the noise canceler consists of two cascaded latches and a match detector. the scl (or sda) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. if they do not agree, the previous value is held. system clock period sampling clock c dq latch c dq latch scl or sda input signal match detector internal scl or sda signal sampling clock figure 18.13 block diagram of noise canceler 18.3.9 sample flowcharts figures 18.14 to 18.17 show sample flowcharts for using the i 2 c bus interface in each mode.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 775 of 1220 rej09b0186-0300o [2] test the status of the scl and sda lines. [1] initialize. [3] select master transmit mode. [4] generate a start condition. [5] wait for start condition to be generated. [6] set first transmit data for the first byte (slave address + r/ w ). (icdr write and iric flag clear operations consecutively.) [7] wait for 1 byte to be transmitted. [8] test for acknowledgement by the designated slave device. [9] set transmit data for the second and subsequent bytes. (perform icdr write and iric flag clear operations consecutively.) [10] wait for 1 byte to be transmitted. [11] test for end of transfer. [12] generate a stop condition. start initialize read bbsy in iccr read iric in iccr no bbsy = 0? yes set mst = 1 and trs = 1 in iccr write bbsy = 1 and scp = 0 in iccr clear iric in iccr read iric in iccr no yes iric = 1? write transmit data in icdr read ackb in icsr ackb = 0? no yes no yes transmit mode? write transmit data in icdr read iric in iccr iric = 1? no yes clear iric in iccr read ackb in icsr clear iric in iccr end of transmission (ackb = 1)? no yes write bbsy = 0 and scp = 0 in iccr end master receive mode no iric = 1? yes figure 18.14 flowchart for master transmit mode (example)
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 776 of 1220 rej09b0186-0300o end set trs = 0 in iccr set ackb = 1 in icsr set wait = 0 in icmr read iric in iccr clear iric in iccr clear iric in iccr clear iric in iccr read icdr clear iric in iccr set ackb = 0 in icsr set wait = 1 in icmr write bbsy = 0 and scp = 0 in iccr last receive? iric = 1? no no yes last receive? no yes yes read iric in iccr iric = 1? no yes read iric in iccr iric = 1? no yes set trs = 1 in iccr read icdr clear iric in iccr clear iric in iccr [4] clear iric flag (clear wait). [1] select receive mode. [2] start receiving. the first read is a dummy read. (perform icdr write and iric flag clear operations consecutively.) [3] wait for 1 byte to be received. [9] clear iric flag (clear wait). [10] set acknowledge data for the last receive. [11] clear iric flag (clear wait). [5] wait for 1 byte to be received. [8] wait for second and subsequent receive data bytes. [7] clear iric flag. read icdr [6] read the received data. [13] clear wait mode. read receive data. clear iric flag. (perform iric flag clearing while wait = 0.) [14] generate a stop condition. master receive mode read iric in iccr iric = 1? no yes [12] wait for 1 byte to be received. figure 18.15 flowchart for master receive mode (example)
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 777 of 1220 rej09b0186-0300o start initialize set mst = 0 and trs = 0 in iccr set ackb = 0 in icsr read iric in iccr iric = 1? yes no clear iric in iccr read aas and adz in icsr aas = 1 and adz = 0? read trs in iccr trs = 0? no yes no yes yes no yes yes no no [1] [2] [3] [4] [5] [6] [7] [8] last receive? read icdr read iric in iccr iric = 1? clear iric in iccr set ackb = 0 in icsr read icdr read iric in iccr read icdr iric = 1? clear iric in iccr end general call address processing * description omitted slave transmit mode [1] select slave receive mode. [2] wait for the first byte to be received (slave address). [3] start receiving. the first read is a dummy read. [4] wait for the transfer to end. [5] set acknowledge data for the last receive. [6] start the last receive. [7] wait for the transfer to end. [8] read the last receive data. figure 18.16 flowchart for slave transmit mode (example)
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 778 of 1220 rej09b0186-0300o slave transmit mode write transmit data in icdr read iric in iccr iric = 1? clear iric in iccr clear iric in iccr clear iric in iccr read ackb in icsr set trs = 0 in iccr end of transmission (ackb = 1)? yes no no yes end [1] [2] [3] read icdr [5] [4] [1] set transmit data for the second and subsequent bytes. [2] wait for 1 byte to be transmitted. [3] test for end of transfer. [4] select slave receive mode. [5] dummy read (to release the scl line). figure 18.17 flowchart for slave receive mode (example) 18.3.10 initialization of internal state the iic has a function for forcible initialization of its internal state if a deadlock occurs during communication. initialization is executed by (1) setting bits clr3 to clr0 in the ddcswr register or (2) clearing the ice bit. for details of settings for bits clr3 to clr0, see section 18.2.8, ddc switch register (ddcswr).
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 779 of 1220 rej09b0186-0300o (1) scope of initialization the initialization executed by this function covers the following items: ? tdre and rdrf internal flags ? transmit/receive sequencer and internal operating clock counter ? internal latches for retaining the output state of the scl and sda pins (wait, clock, data output, etc.) the following items are not initialized: ? actual register values (icdr, sar, sarx, icmr, iccr, icsr, ddcswr, stcr) ? internal latches used to retain register read information for setting/clearing flags in the icmr, iccr, icsr, and ddcswr registers ? the value of the icmr register bit counter (bc2 to bc0) ? generated interrupt sources (interrupt sources transferred to the interrupt controller) (2) notes on initialization ? interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. ? basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary. ? when initialization is performed by means of the ddcswr register, the write data for bits clr3 to clr0 is not retained. to perform iic clearance, bits clr3 to clr0 must be written to simultaneously using an mov instruction. do not use a bit manipulation instruction such as bclr. similarly, when clearing is required again, all the bits must be written to simultaneously in accordance with the setting. ? if a flag clearing setting is made during transmission/reception, the iic module will stop transmitting/receiving at that point and the scl and sda pins will be released. when transmission/reception is started again, register initialization, etc., must be carried out as necessary to enable correct communication as a system. the value of the bbsy bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release t iming of the scl and sda pins, the bbsy bit may be cleared as a result. similarly, state switching of other bits and flags may also have an effect. to prevent problems caused by these factors, the following procedure should be used when initializing the iic state.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 780 of 1220 rej09b0186-0300o 1. execute initialization of the internal state according to the setting of bits clr3 to clr0, or according to the ice bit. 2. execute a stop condition issuance instruction (write 0 to bbsy and scp) to clear the bbst bit to 0, and wait for two transfer rate clock cycles. 3. re-execute initialization of the internal state according to the setting of bits clr3 to clr0, or according to the ice bit. 4. initialize (re-set) the iic registers. 18.4 usage notes (1) in master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition w ill be output correctly. to output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that scl and sda are both low, then issue the instruction that generates the stop condition. note that scl may not yet have gone low when bbsy is cleared to 0. (2) either of the following two conditions w ill start the next transfer. pay attention to these conditions when reading or writing to icdr. ? write access to icdr when ice = 1 and trs = 1 (including automatic transfer from icdrt to icdrs) ? read access to icdr when ice = 1 and trs = 0 (including automatic transfer from icdrs to icdrr) (3) table 18.6 shows the t iming of scl and sda output in synchronization with the internal clock. timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, series resistance, and parallel resistance.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 781 of 1220 rej09b0186-0300o table 18.6 i 2 c bus timing (scl and sda output) item symbol output timing unit notes scl output cycle time t sclo 28 t cyc to 256 t cyc ns scl output high pulse width t sclho 0.5 t sclo ns figure 25.33 (reference) scl output low pulse width t scllo 0.5 t sclo ns sda output bus free time t bufo 0.5 t sclo ? 1 t cyc ns start condition output hold time t staho 0.5 t sclo ? 1 t cyc ns retransmission start condition output setup time t staso 1 t sclo ns stop condition output setup time t stoso 0.5 t sclo + 2 t cyc ns data output setup time (master) t sdaso 1 t scllo ? 3 t cyc ns data output setup time (slave) 1 t scll ? 3 t cyc data output hold time t sdaho 3 t cyc ns (4) scl and sda input is sampled in synchronization with the internal clock. the ac t iming therefore depends on the system clock cycle t cyc , as shown in table 25.11 in section 25, electrical characteristics. note that the i 2 c bus interface ac timing specifications will not be met with a system clock frequency of less than 5 mhz. (5) the i 2 c bus interface specification for the scl rise time t sr is under 1000 ns (300 ns for high- speed mode). in master mode, the i 2 c bus interface monitors the scl line and synchronizes one bit at a time during communication. if t sr (the time for scl to go from low to v ih ) exceeds the time determined by the input clock of the i 2 c bus interface, the high period of scl is extended. the scl rise time is determined by the pull-up resistance and load capacitance of the scl line. to insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the scl rise time does not exceed the values given in the table below.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 782 of 1220 rej09b0186-0300o table 18.7 permissible scl rise time (t sr ) values time indication iicx t cyc indication i 2 c bus specifi- cation (max.) = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz = 25 mhz = 28 mhz 0 7.5 t cyc standard mode 1000 ns 1000 ns 937 ns 750 ns 468 ns 375 ns ?? high-speed mode 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns ?? 1 17.5 t cyc standard mode 1000 ns 1000 ns 1000 ns 1000 ns 1000 ns875 ns 700 ns 624 ns high-speed mode 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns note: when 7.5 t cyc is selected as the transfer rate, the actual transfer rate may be extended if exceeds 20 mhz. (6) the i 2 c bus interface specifications for the scl and sda rise and fall times are under 1000 ns and 300 ns. the i 2 c bus interface scl and sda output timing is prescribed by t scyc and t cyc , as shown in table 18.6. however, because of the rise and fall times, the i 2 c bus interface specifications may not be satisfied at the maximum transfer rate. table 18.8 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. t bufo fails to meet the i 2 c bus interface specifications at any frequency. the solution is either (a) to provide coding to secure the necessary interval (approximately 1 s) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input t iming permits this output timing for use as slave devices connected to the i 2 c bus. t scllo in high-speed mode and t staso in standard mode fail to satisfy the i 2 c bus interface specifications for worst-case calculations of t sr /t sf . possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input t iming permits this output timing for use as slave devices connected to the i 2 c bus.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 783 of 1220 rej09b0186-0300o table 18.8 i 2 c bus timing (with maximum influence of t sr /t sf ) time indication (at maximum transfer rate) [ns] item t cyc indication t sr /t sf influence (max.) i 2 c bus specifi- cation (min.) = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz = 25 mhz t sclho 0.5 t sclo ( ? t sr ) standard mode ? 1000 4000 4000 4000 4000 4000 4000 4000 high-speed mode ? 300 600 950 950 950 950 950 950 t scllo 0.5 t sclo ( ? t sf ) standard mode ? 250 4700 4750 4750 4750 4750 4750 4750 high-speed mode ? 250 1300 1000 * 1 1000 * 1 1000 * 1 1000 * 1 1000 * 1 1000 * 1 t bufo standard mode ? 1000 4700 3800 * 1 3875 * 1 3900 * 1 3938 * 1 3950 * 1 3960 * 1 0.5 t sclo ? 1 t cyc ( ? t sr ) high-speed mode ? 300 1300 750 * 1 825 * 1 850 * 1 888 * 1 900 * 1 910 * 1 t staho standard mode ? 250 4000 4550 4625 4650 4688 4700 4710 0.5 t sclo ? 1 t cyc ( ? t sf ) high-speed mode ? 250 600 800 875 900 938 950 960 t staso 1 t sclo ( ? t sr ) standard mode ? 1000 4700 9000 9000 9000 9000 9000 9000 high-speed mode ? 300 600 2200 2200 2200 2200 2200 2200 t stoso standard mode ? 1000 4000 4400 4250 4200 4125 4100 4080 0.5 t sclo + 2 t cyc ( ? t sr ) high-speed mode ? 300 600 1350 1200 1150 1075 1050 1030 t sdaso (master) standard mode ? 1000 250 3100 3325 3400 3513 3550 3580 1 t scllo * 2 ? 3 t cyc ( ? t sr ) high-speed mode ? 200 100 400 625 700 813 850 880 t sdaso (slave) standard mode ? 1000 250 3100 3325 3400 3513 3550 3580 1 t scll * 2 ? 3 t cyc * 2 ( ? t sr ) high-speed mode ? 300 100 400 625 700 813 850 880
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 784 of 1220 rej09b0186-0300o time indication (at maximum transfer rate) [ns] item t cyc indication t sr /t sf influence (max.) i 2 c bus specifi- cation (min.) = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz = 25 mhz t sdaho 3 t cyc standard mode 0 0 600 375 300 188 150 120 high-speed mode 0 0 600 375 300 188 150 120 notes: does not meet the i 2 c bus interface specification. remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. the values in the above table will vary depending on the settings of the iicx bit and bits cks0 to cks2. depending on the frequency it may not be possible to achieve the maximum transfer rate; therefore, whether or not the i 2 c bus interface specifications are met must be determined in accordance with the actual setting conditions. calculated using the i 2 c bus specification values (standard mode: 4700 ns min.; high-speed mode: 1300 ns min.). (7) note on icdr read at end of master reception to halt reception at the end of a receive operation in master receive mode, set the trs bit to 1 and write 0 to bbsy and scp in iccr. this changes sda from low to high when scl is high, and generates the stop condition. after this, receive data can be read by means of an icdr read, but if data remains in the buffer the icdrs receive data w ill not be transferred to icdr, and so it will not be possible to read the second byte of data. if it is necessary to read the second byte of data, issue the stop condition in master receive mode (i.e. with the trs bit cleared to 0). when reading the receive data, first confirm that the bbsy bit in the iccr register is cleared to 0, the stop condition has been generated, and the bus has been released, then read the icdr register with trs cleared to 0. note that if the receive data (icdr data) is read in the interval between execution of the instruction for issuance of the stop condition (writing of 0 to bbsy and scp in iccr) and the actual generation of the stop condition, the clock may not be output correctly in subsequent master transmission. clearing of the mst bit after completion of master transmission/reception, or other modifications of iic control bits to change the transmit/r eceive operating mode or settings, must be carried out during interval (a) in figure 18.18 (after confirming that the bbsy bit has been cleared to 0 in the iccr register).
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 785 of 1220 rej09b0186-0300o sda scl internal clock bbsy bit master receive mode icdr reading prohibited bit 0 a 8 9 stop condition (a) start condition execution of stop condition issuance instruction (0 written to bbsy and scp) confirmation of stop condition generation (0 read from bbsy) start condition issuance figure 18.18 points for attention concerning reading of master receive data (8) notes on start condition issuance for retransmission figure 18.19 shows the t iming of start c ondition issuance for retransmission, and the t iming for subsequently writing data to icdr, together with the corresponding flowchart.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 786 of 1220 rej09b0186-0300o read scl pin write transmit data to icdr clear iric in icsr write bbsy = 1, scp = 0 (icsr) iric = 1 ? no scl = low ? no yes start condition issuance? no [1] [2] [3] [4] [5] note: program so that processing from [3] to [5] is executed continuously. [1] wait for end of 1-byte transfer [2] determine whether scl is low [3] issue restart condition instruction for retransmission [4] determine whether scl is high [5] set transmit data (slave address + r/ w ) other processing yes yes read scl pin scl = high ? no yes start condition (retransmission) scl bit7 ack iric [1] iric determination determination of scl = low [2] [3] start condition instruction issuance [4] determination of scl = high [5] icdr write sda figure 18.19 flowchart and timing of start condition instruction issuance for retransmission
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 787 of 1220 rej09b0186-0300o (9) notes on i 2 c bus interface stop condition instruction issuance if the rise time of the 9th scl acknowledge exceeds the specification because the bus load capacitance is large, or if there is a slave device of the type that drives scl low to effect a wait, issue the stop condition instruction after reading scl and determining it to be low, as shown below. stop condition scl iric [1] determination of scl = low 9th clock vih high period secured [2] stop condition instruction issuance sda as waveform rise is late, scl is detected as low figure 18.20 timing of stop condition issuance
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 788 of 1220 rej09b0186-0300o (10) notes on iric flag clearance when using wait function if the scl rise time exceeds the designated duration or if the slave device is of the type that keeps scl low and applies a wait state when the wait function is used in the master mode of the i 2 c bus interface, read scl and clear the iric flag after determining that scl has gone low, as shown below. clearing the iric flag to 0 when wait is set to 1 and scl is being held at high level can cause the sda value to change before scl goes low, resulting in a start condition or stop condition being generated erroneously. scl scl = high duration maintained [1] judgement that scl = low [2] iric clearance v ih sda iric scl = low detected figure 18.21 iric flag clearance in wait = 1 status
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 789 of 1220 rej09b0186-0300o (11) notes on icdr reads and iccr access in slave transmit mode in a transmit operation in the slave mode of the i 2 c bus interface, do not read the icdr register or read or write to the iccr register during the period indicated by the shaded portion in figure 18.22. normally, when interrupt processing is triggered in synchronization with the rising edge of the 9th clock cycle, the period in question has already elapsed when the transition to interrupt processing takes place, so there is no problem with reading the icdr register or reading or writing to the iccr register. to ensure that the interrupt processing is performed properly, one of the following two conditions should be applied. make sure that reading received data from the icdr register, or reading or writing to the iccr register, is completed before the next slave address receive operation starts. monitor the bc2 to bc0 counter in the icmr register and, when the value of bc2 to bc0 is 000 (8th or 9th clock cycle), allow a waiting time of at least 2 transfer clock cycles in order to involve the problem period in question before reading from the icdr register, or reading or writing to the iccr register. sda r/w waveforms if problem occurs bit 7 icdr write data transmission period when icdr reads and iccr reads and writes are prohibited (6 system clock cycles) detection of 9th clock cycle risin g ed g e a 89 scl trs address received figure 18.22 icdr read and iccr access timing in slave transmit mode
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 790 of 1220 rej09b0186-0300o (12) notes on trs bit setting in slave mode from the detection of the rising edge of the 9th clock cycle or of a stop condition to when the rising edge of the next scl pin signal is detected (the period indicated as (a) in figure 18.23) in the slave mode of the i 2 c bus interface, the value set in the trs bit in the iccr register is effective immediately. however, at other times (indicated as (b) in figure 18.23) the value set in the trs bit is put on hold until the next rising edge of the 9th clock cycle or stop condition is detected, rather than taking effect immediately. this results in the actual internal value of the trs bit remaining 1 (transmit mode) and no acknowledge bit being sent at the 9th clock cycle address receive completion in the case of an address receive operation following a restart condition input with no stop condition intervening. when receiving an address in the slave mode, clear the trs bit to 0 during the period indicated as (a) in figure 18.23. to cancel the holding of the scl bit low by the wait function in the slave mode, clear the trs bit to 0 and then perform a dummy read of the icdr register. (a) restart condition icdr dummy read detection of 9th clock cycle rising edge trs bit set detection of 9th clock cycle rising edge 89 (b) data transmission sda scl trs 123456789 a address reception trs bit setting hold time figure 18.23 trs bit setting timing in slave mode
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 791 of 1220 rej09b0186-0300o (13) notes on icdr reads in transmit mode and icdr writes in receive mode when attempting to read icdr in the transmit mode (trs = 1) or write to icdr in the receive mode (trs = 0) under certain conditions, the scl pin may not be held low after the completion of the transmit or receive operation and a clock may not be output to the scl bus line before the icdr register access operation can take place properly. when accessing icdr, always change the setting to the transmit mode before performing a read operation, and always change the setting to the receive mode before performing a write operation. (14) notes on acke bit and trs bit in slave mode when using the i 2 c bus interface, if an address is received in the slave mode immediately after 1 is received as an acknowledge bit (ackb = 1) in the transmit mode (trs = 1), an interrupt may be generated at the rising edge of the 9th clock cycle if the address does not match. when performing slave mode operations using the iic bus interface module, make sure to do the following. when a 1 is received as an acknowledge bit for the final transmit data after completing a series of transmit operations, clear the acke bit in the iccr register to 0 to initialize the ackb bit to 0. in the slave mode, change the setting to the receive mode (trs = 0) before the start condition is input. to ensure that the switch from the slave transmit mode to the slave receive mode is accomplished properly, end the transmission as described in figure 18.17 in section 18.3.9, sample flowcharts. (15) notes on arbitration lost in master mode the i 2 c bus interface recognizes the data in transmit/receive frame as an address when arbitration is lost in master mode and a transition to slave receive mode is automatically carried out. when arbitration is lost not in the first frame but in the second frame or subsequent frame, transmit/receive data that is not an address is compared with the value set in the sar or sarx register as an address. if the receive data matches with the address in the sar or sarx register, the i 2 c bus interface erroneously recognizes that the address call has occurred. (see figure 18.24.) in multi-master mode, a bus conflict could happen. when the i 2 c bus interface is operated in master mode, check the state of the al bit in the icsr register every time after one frame of data has been transmitted or received. when arbitration is lost during transmitting the second frame or subsequent frame, take avoidance measures.
section 18 i 2 c bus interface [option] rev. 3.00 jan 11, 2005 page 792 of 1220 rej09b0186-0300o sa sla r/ w sa sla r/ w a data2 sa sla r/ w a sla r/ w a data3 a data4 data1 i 2 c bus interface (master transmit mode) transmit data match transmit timing match receive address is ignored automatically transferred to slave receive mode receive data is recognized as an address when the receive data matches to the address set in the sar or sarx register, the i 2 c bus interface operates as a slave device. arbitration is lost the al flag in icsr is set to 1 transmit data does not match other device (master transmit mode) i 2 c bus interface (slave receive mode) data contention figure 18.24 diagram of erroneous operation when arbitration is lost though it is prohibited in the normal i 2 c protocol, the same problem may occur when the mst bit is erroneously set to 1 and a transition to master mode is occurred during data transmission or reception in slave mode. in multi-master mode, pay attention to the setting of the mst bit when a bus conflict may occur. in this case, the mst bit in the iccr register should be set to 1 according to the order below. a. make sure that the bbsy flag in the iccr register is 0 and the bus is free before setting the mst bit. b. set the mst bit to 1. c. to confirm that the bus was not entered to the busy state while the mst bit is being set, check that the bbsy flag in the iccr register is 0 immediately after the mst bit has been set.
section 19 a/d converter rev. 3.00 jan 11, 2005 page 793 of 1220 rej09b0186-0300o section 19 a/d converter 19.1 overview the h8s/2643 group incorporates a successive approximation type 10-bit a/d converter that allows up to sixteen analog input channels to be selected. 19.1.1 features a/d converter features are listed below. ? 10-bit resolution ? sixteen input channels ? settable analog conversion voltage range ? conversion of analog voltages with the reference voltage pin (vref) as the analog reference voltage ? high-speed conversion ? minimum conversion time: 10.64 s per channel (at 25 mhz operation) ? choice of single mode or scan mode ? single mode: single-channel a/d conversion ? scan mode: continuous a/d conversion on 1 to 4 channels ? four data registers ? conversion results are held in a 16-bit data register for each channel ? sample and hold function ? three kinds of conversion start ? choice of software or timer conversion start trigger (tpu or 8-bit timer), or adtrg pin ? a/d conversion end interrupt generation ? a/d conversion end interrupt (adi) request can be generated at the end of a/d conversion ? module stop mode can be set ? as the initial setting, a/d converter operation is halted. register access is enabled by exiting module stop mode.
section 19 a/d converter rev. 3.00 jan 11, 2005 page 794 of 1220 rej09b0186-0300o 19.1.2 block diagram figure 19.1 shows a block diagram of the a/d converter. module data bus control circuit internal data bus 10-bit d/a comparator + ? sample-and- hold circuit /2 /4 /8 adi interrupt /16 bus interface a d c s r a d c r a d d r d a d d r c a d d r b a d d r a avcc vref avss an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 an15 adtrg conversion start trigger from 8-bit timer or tpu successive approximations register multiplexer adcr: adcsr: addra: addrb: addrc: addrd: legend: a/d control register a/d control/status register a/d data register a a/d data register b a/d data register c a/d data re g ister d figure 19.1 block diagram of a/d converter
section 19 a/d converter rev. 3.00 jan 11, 2005 page 795 of 1220 rej09b0186-0300o 19.1.3 pin configuration table 19.1 summarizes the input pins used by the a/d converter. the avcc and avss pins are the power supply pins for the analog block in the a/d converter. the vref pin is the a/d conversion reference voltage pin. the 16 analog input pins are divided into two channel sets and two groups, with analog input pins 0 to 7 (an0 to an7) comprising channel set 0, analog input pins 8 to 15 (an8 to an15) comprising channel set 1, analog input pins 0 to 3 and 8 to 11 (an0 to an3, an8 to an11) comprising group 0, and analog input pins 4 to 7 and 12 to 15 (an4 to an7, an12 to an15) comprising group 1. table 19.1 a/d converter pins pin name symbol i/o function analog power supply pin avcc input analog block power supply analog ground pin avss i nput analog block ground and reference voltage reference voltage pin vref input a/d conversion reference voltage analog input pin 0 an0 input channel set 0 (ch3 = 0) group 0 analog inputs analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input analog input pin 4 an4 input channel set 0 (ch3 = 0) group 1 analog inputs analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input analog input pin 8 an8 input channel set 1 (ch3 = 1) group 0 analog inputs analog input pin 9 an9 input analog input pin 10 an10 input analog input pin 11 an11 input analog input pin 12 an12 input channel set 1 (ch3 = 1) group 1 analog inputs analog input pin 13 an13 input analog input pin 14 an14 input analog input pin 15 an15 input a/d external trigger input pin adtrg input external trigger input for starting a/d conversion
section 19 a/d converter rev. 3.00 jan 11, 2005 page 796 of 1220 rej09b0186-0300o 19.1.4 register configuration table 19.2 summarizes the registers of the a/d converter. table 19.2 a/d converter registers name abbreviation r/w initial value address * 1 a/d data register ah addrah r h'00 h 'ff90 a/d data register al addral r h'00 h 'ff91 a/d data register bh addrbh r h'00 h 'ff92 a/d data register bl addrbl r h'00 h 'ff93 a/d data register ch addrch r h'00 h 'ff94 a/d data register cl addrcl r h'00 h 'ff95 a/d data register dh addrdh r h'00 h 'ff96 a/d data register dl addrdl r h'00 h 'ff97 a/d control/status register adcsr r/(w) * 2 h'00 h'ff98 a/d control register adcr r/w h'33 h'ff99 module stop control register a mstpcra r/w h'3f h'fde8 notes: 1. lower 16 bits of the address. 2. bit 7 can only be written with 0 for flag clearing.
section 19 a/d converter rev. 3.00 jan 11, 2005 page 797 of 1220 rej09b0186-0300o 19.2 register descriptions 19.2.1 a/d data registers a to d (addra to addrd) 15 ad9 0 r bit initial value r/w : : : 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? 0 r there are four 16-bit read-only addr registers, addra to addrd, used to store the results of a/d conversion. the 10-bit data resulting from a/d conversion is transferred to the addr register for the selected channel and stored there. the upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of addr, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. bits 5 to 0 are always read as 0. the correspondence between the analog input channels and addr registers is shown in table 19.3. addr can always be read by the cpu. the upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (temp). for details, see section 19.3, interface to bus master. the addr registers are initialized to h'0000 by a reset, and in standby mode or module stop mode. table 19.3 analog input channels and corresponding addr registers analog input channel channel set 0 (ch3 = 0) channel set 1 (ch3 = 1) group 0 group 1 group 0 group 1 a/d data register an0 an4 an8 an12 addra an1 an5 an9 an13 addrb an2 an6 an10 an14 addrc an3 an7 an11 an15 addrd
section 19 a/d converter rev. 3.00 jan 11, 2005 page 798 of 1220 rej09b0186-0300o 19.2.2 a/d control/status register (adcsr) 7 adf 0 r/(w) * 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 ch3 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w bit initial value r/w : : : note: * onl y 0 can be written to bit 7, to clear this fla g . adcsr is an 8-bit readable/writable register that controls a/d conversion operations. adcsr is initialized to h'00 by a reset, and in hardware standby mode or module stop mode. bit 7?a/d end flag (adf): status flag that indicates the end of a/d conversion. bit 7 adf description 0 [clearing conditions] (initial value) ? when 0 is written to the adf flag after reading adf = 1 ? when the dmac or dtc is activated by an adi interrupt and addr is read 1 [setting conditions] ? single mode: when a/d conversion ends ? scan mode: when a/d conversion ends on all specified channels bit 6?a/d interrupt enable (adie): selects enabling or disabling of interrupt (adi) requests at the end of a/d conversion. bit 6 adie description 0 a/d conversion end interrupt (adi) request disabled (initial value) 1 a/d conversion end interrupt (adi) request enabled
section 19 a/d converter rev. 3.00 jan 11, 2005 page 799 of 1220 rej09b0186-0300o bit 5?a/d start (adst): selects starting or stopping on a/d conversion. holds a value of 1 during a/d conversion. the adst bit can be set to 1 by software, a timer conversion start trigger, or the a/d external trigger input pin ( adtrg ). bit 5 adst description 0 ? a/d conversion stopped (initial value) 1 ? single mode: a/d conversion is started. cleared to 0 automatically when conversion on the specified channel ends ? scan mode: a/d conversion is started. conversion continues sequentially on the selected channels until adst is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. bit 4?scan mode (scan): selects single mode or scan mode as the a/d conversion operating mode. see section 19.4, operation, for single mode and scan mode operation. only set the scan bit while conversion is stopped (adst = 0). bit 4 scan description 0 single mode (initial value) 1 scan mode bit 3?channel select 3 (ch3): switches the analog input pins assigned to group 0 or group 1. setting ch3 to 1 enables an8 to an15 to be used instead of an0 to an7. bit 3 ch3 description 0 an8 to an11 are group 0 analog input pins, an12 to an15 are group 1 analog input pins 1 an0 to an3 are group 0 analog input pins, an4 to an7 are group 1 analog input pins (initial value)
section 19 a/d converter rev. 3.00 jan 11, 2005 page 800 of 1220 rej09b0186-0300o bits 2 to 0?channel select 2 to 0 (ch2 to ch0): together with the scan bit, these bits select the analog input channels. only set the input channel while conversion is stopped (adst = 0). channel selection description ch3 ch2 ch1 ch0 single mode (scan = 0) scan mode (scan = 1) 0000 an0 (initial value)an0 1 an1 an0, an1 1 0 an2 an0 to an2 1 an3 an0 to an3 100 an4 an4 1 an5 an4, an5 1 0 an6 an4 to an6 1 an7 an4 to an7 1000 an8 an8 1 an9 an8, an9 1 0 an10 an8 to an10 1 an11 an8 to an11 1 0 0 an12 an12 1 an13 an12, an13 1 0 an14 an12 to an14 1 an15 an12 to an15
section 19 a/d converter rev. 3.00 jan 11, 2005 page 801 of 1220 rej09b0186-0300o 19.2.3 a/d control register (adcr) 7 trgs1 0 r/w 6 trgs0 0 r/w 5 ? 1 ? 4 ? 1 ? 3 cks1 0 r/w 0 ? 1 ? 2 cks0 0 r/w 1 ? 1 ? bit initial value r/w : : : adcr is an 8-bit readable/writable register that enables or disables external triggering of a/d conversion operations and sets the a/d conversion time. adcr is initialized to h'33 by a reset, and in standby mode or module stop mode. bits 7 and 6?timer trigger select 1 and 0 (trgs1, trgs0): select enabling or disabling of the start of a/d conversion by a trigger signal. only set bits trgs1 and trgs0 while conversion is stopped (adst = 0). bit 7 bit 6 trgs1 trgs0 description 0 0 a/d conversion start by software is enabled (initial value) 1 a/d conversion start by tpu conversion start trigger is enabled 1 0 a/d conversion start by 8-bit timer conversion start trigger is enabled 1 a/d conversion start by external trigger pin ( adtrg ) is enabled bits 5, 4, 1, and 0?reserved: they are always read as 1 and cannot be modified. bits 3 and 2?clock select 1 and 0 (cks1, cks0): these bits select the a/d conversion time. the conversion time should be changed only when adst = 0. set bits cks1 and cks0 to give a conversion time of at least 10 s when av cc 4.5 v, and at least 16 s when av cc < 4.5 v. bit 3 bit 2 cks1 cks0 description 0 0 conversion time = 530 states (max.) (initial value) 1 conversion time = 266 states (max.) 1 0 conversion time = 134 states (max.) 1 conversion time = 68 states (max.)
section 19 a/d converter rev. 3.00 jan 11, 2005 page 802 of 1220 rej09b0186-0300o 19.2.4 module stop control register a (mstpcra) 7 mstpa7 0 r/w 6 mstpa6 0 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 0 mstpa0 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w bit initial value r/w : : : mstpcr is an 8-bit readable/writable register that performs module stop mode control. when the mstpa1 bit in mstpcr is set to 1, a/d converter operation stops at the end of the bus cycle and a transition is made to module stop mode. registers cannot be read or written to in module stop mode. for details, see section 24.5, module stop mode. mstpcra is initialized to h'3f by a reset and in hardware standby mode. it is not initialized by a manual reset and in software standby mode. bit 1?module stop (mstpa1): specifies the a/d converter module stop mode. bit 1 mstpa1 description 0 a/d converter module stop mode cleared 1 a/d converter module stop mode set (initial value)
section 19 a/d converter rev. 3.00 jan 11, 2005 page 803 of 1220 rej09b0186-0300o 19.3 interface to bus master addra to addrd are 16-bit registers, and the data bus to the bus master is 8 bits wide. therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (temp). a data read from addr is performed as follows. when the upper byte is read, the upper byte value is transferred to the cpu and the lower byte value is transferred to temp. next, when the lower byte is read, the temp contents are transferred to the cpu. when reading addr. always read the upper byte before the lower byte. it is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. figure 19.2 shows the data flow for addr access. bus master (h'aa) addrnh (h'aa) addrnl (h'40) lower byte read addrnh (h'aa) addrnl (h'40) temp (h'40) temp (h'40) (n = a to d) (n = a to d) module data bus module data bus bus interface upper byte read bus master (h'40) bus interface figure 19.2 addr access operation (reading h'aa40)
section 19 a/d converter rev. 3.00 jan 11, 2005 page 804 of 1220 rej09b0186-0300o 19.4 operation the a/d converter operates by successive approximation with 10-bit resolution. it has two operating modes: single mode and scan mode. 19.4.1 single mode (scan = 0) single mode is selected when a/d conversion is to be performed on a single channel only. a/d conversion is started when the adst bit is set to 1, according to the software or external trigger input. the adst bit remains set to 1 during a/d conversion, and is automatically cleared to 0 when conversion ends. on completion of conversion, the adf flag is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. the adf flag is cleared by writing 0 after reading adcsr. when the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again. the adst bit can be set at the same time as the operating mode or input channel is changed. typical operations when channel 1 (an1) is selected in single mode are described next. figure 19.3 shows a t iming diagram for this example. [1] single mode is selected (scan = 0), input channel an1 is selected (ch3 = 0, ch2 = 0, ch1 = 0, ch0 = 1), the a/d interrupt is enabled (adie = 1), and a/d conversion is started (adst = 1). [2] when a/d conversion is completed, the result is transferred to addrb. at the same time the adf flag is set to 1, the adst bit is cleared to 0, and the a/d converter becomes idle. [3] since adf = 1 and adie = 1, an adi interrupt is requested. [4] the a/d interrupt handling routine starts. [5] the routine reads adcsr, then writes 0 to the adf flag. [6] the routine reads and processes the connection result (addrb). [7] execution of the a/d interrupt handling routine ends. after that, if the adst bit is set to 1, a/d conversion starts again and steps [2] to [7] are repeated.
section 19 a/d converter rev. 3.00 jan 11, 2005 page 805 of 1220 rej09b0186-0300o adie adst adf state of channel 0 (an0) a/d conversion starts 2 1 addra addrb addrc addrd state of channel 1 (an1) state of channel 2 (an2) state of channel 3 (an3) note: * vertical arrows ( ) indicate instructions executed by software. set * set * clear * clear * a/d conversion result 1 a/d conversion a/d conversion result 2 read conversion result read conversion result idle idle idle idle idle idle a/d conversion set * figure 19.3 example of a/d converter operation (single mode, channel 1 selected)
section 19 a/d converter rev. 3.00 jan 11, 2005 page 806 of 1220 rej09b0186-0300o 19.4.2 scan mode (scan = 1) scan mode is useful for monitoring analog inputs in a group of one or more channels. when the adst bit is set to 1 by a software, timer or external trigger input, a/d conversion starts on the first channel in the group (an0). when two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (an1) starts immediately. a/d conversion continues cyclically on the selected channels until the adst bit is cleared to 0. the conversion results are transferred for storage into the addr registers corresponding to the channels. when the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again from the first channel (an0). the adst bit can be set at the same time as the operating mode or input channel is changed. typical operations when three channels (an0 to an2) are selected in scan mode are described next. figure 19.4 shows a t iming diagram for this example. [1] scan mode is selected (scan = 1), channel set 0 is selected (ch3 = 0), scan group 0 is selected (ch2 = 0), analog input channels an0 to an2 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1) [2] when a/d conversion of the first channel (an0) is completed, the result is transferred to addra. next, conversion of the second channel (an1) starts automatically. [3] conversion proceeds in the same way through the third channel (an2). [4] when conversion of all the selected channels (an0 to an2) is completed, the adf flag is set to 1 and conversion of the first channel (an0) starts again. if the adie bit is set to 1 at this time, an adi interrupt is requested after a/d conversion ends. [5] steps [2] to [4] are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops. after that, if the adst bit is set to 1, a/d conversion starts again from the first channel (an0).
section 19 a/d converter rev. 3.00 jan 11, 2005 page 807 of 1220 rej09b0186-0300o adst adf addra addrb addrc addrd state of channel 0 (an0) state of channel 1 (an1) state of channel 2 (an2) state of channel 3 (an3) set * 1 clear * 1 idle notes: 1. vertical arrows ( ) indicate instructions executed by software. 2. data currently being converted is ignored. clear * 1 idle idle a/d conversion time idle continuous a/d conversion execution a/d conversion 1 idle idle idle idle idle transfer * 2 a/d conversion 3 a/d conversion 2 a/d conversion 5 a/d conversion 4 a/d conversion result 1 a/d conversion result 2 a/d conversion result 3 a/d conversion result 4 figure 19.4 example of a/d converter operation (scan mode, 3 channels an0 to an2 selected)
section 19 a/d converter rev. 3.00 jan 11, 2005 page 808 of 1220 rej09b0186-0300o 19.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input at a time t d after the adst bit is set to 1, then starts conversion. figure 19.5 shows the a/d conversion timing. table 1 9.4 indicates the a/d conversion time. as indicated in figure 19.5, the a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the write access to adcsr. the total conversion time therefore varies within the ranges indicated in table 19.4. in scan mode, the values given in table 19.4 apply to the first conversion time. the values given in table 19.5 apply to the second and subsequent conversions. in both cases, set bits cks1 and cks0 in adcr to give a conversion time of at least 10 s when av cc 4.5 v, and at least 16 s when av cc < 4.5 v. (1) (2) t d t spl t conv input sampling timing adf address write signal legend: (1): adcsr write cycle (2): adcsr address t d : a/d conversion start delay t spl : input sampling time t conv : a/d conversion time figure 19.5 a/d conversion timing
section 19 a/d converter rev. 3.00 jan 11, 2005 page 809 of 1220 rej09b0186-0300o table 19.4 a/d conversion time (single mode) cks1 = 0 cks1 = 1 cks0 = 0 cks0 = 1 cks0 = 0 cks0 = 1 item symbol min. typ. max. min. typ. max. min. typ. max. min. typ. max. a/d conversion start delay t d 18 ? 33 10 ? 17 6 ? 94 ? 5 input sampling time t spl ? 127 ?? 63 ?? 31 ?? 15 ? a/d conversion time t conv 515 ? 530 259 ? 266 131 ? 134 67 ? 68 note: values in the table are the number of states. table 19.5 a/d conversion time (scan mode) cks1 cks0 conversion time (state) 0 0 512 (fixed) 1 256 (fixed) 1 0 128 (fixed) 1 64 (fixed)
section 19 a/d converter rev. 3.00 jan 11, 2005 page 810 of 1220 rej09b0186-0300o 19.4.4 external trigger input timing a/d conversion can be externally triggered. when the trgs1 and trgs0 bits are set to 11 in adcr, external trigger input is enabled at the adtrg pin. a falling edge at the adtrg pin sets the adst bit to 1 in adcsr, starting a/d conversion. other operations, in both single and scan modes, are the same as if the adst bit has been set to 1 by software. figure 19.6 shows the timing. adtrg internal trigger signal adst a/d conversion figure 19.6 external trigger input timing 19.5 interrupts the a/d converter generates an a/d conversion end interrupt (adi) at the end of a/d conversion. adi interrupt requests can be enabled or disabled by means of the adie bit in adcsr. the dtc and dmac can be activated by an adi interrupt. having the converted data read by the dtc or dmac in response to an adi interrupt enables continuous conversion to be achieved without imposing a load on software. the a/d converter interrupt source is shown in table 19.6. table 19.6 a/d converter interrupt source interrupt source description dtc, dmac activation adi interrupt due to end of conversion possible
section 19 a/d converter rev. 3.00 jan 11, 2005 page 811 of 1220 rej09b0186-0300o 19.6 usage notes the following points should be noted when using the a/d converter. (1) setting range of analog power supply and other pins: (a) analog input voltage range the voltage applied to analog input pin ann during a/d conversion should be in the range avss ann vref. (b) relation between avcc, avss and vcc, vss as the relationship between avcc, avss and vcc, vss, set avss = vss. if the a/d converter is not used, the avcc and avss pins must on no account be left open. (c) vref input range the analog reference voltage input at the vref pin set in the range vref avcc. if conditions (a), (b), and (c) above are not met, the reliab ility of the device may be adversely affected. (2) notes on board design in board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity s hould be avoided as far as possible. failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting a/d conversion values. also, digital circuitry must be isolated from the analog input signals (an0 to an15), analog reference power supply (vref), and analog power supply (avcc) by the analog ground (avss). also, the analog ground (avss) should be connected at one point to a stable digital ground (vss) on the board. (3) notes on noise countermeasures a protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (an0 to an15) and analog reference power supply (vref) should be connected between avcc and avss as shown in figure 19.7. also, the bypass capacitors connected to avcc and vref and the filter capacitor connected to an0 to an15 must be connected to avss. if a filter capacitor is connected as shown in figure 19.7, the input currents at the analog input pins (an0 to an15) are averaged, and so an error may arise. also, when a/d conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the
section 19 a/d converter rev. 3.00 jan 11, 2005 page 812 of 1220 rej09b0186-0300o sample-and-hold circuit in the a/d converter exceeds the current input via the input impedance (r in ), an error will arise in the analog i nput pin voltage. careful consideration is therefore required when deciding the circuit constants. avcc * 1 * 1 vref an0 to an15 avss notes: values are reference values. 1. 2. r in : input impedance r in * 2 100 0.1 f 0.01 f 10 f figure 19.7 example of analog input protection circuit table 19.7 analog pin specifications item min. max. unit analog input capacitance ? 20 pf permissible signal source impedance ? 5k ?
section 19 a/d converter rev. 3.00 jan 11, 2005 page 813 of 1220 rej09b0186-0300o 20 pf to a/d converter an0 to an15 10 k ? note: values are reference values. figure 19.8 analog input pin equivalent circuit (4) a/d conversion precision definitions h8s/2643 group a/d conversion precision definitions are given below. ? resolution the number of a/d converter digital output codes ? offset error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from the minimum voltage value b'0000000000 (h'00) to b'0000000001 (h'01) (see figure 19.10). ? full-scale error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from b'1111111110 (h'3e) to b'1111111111 (h'3f) (see figure 19.10). ? quantization error the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 19.9). ? nonlinearity error the error with respect to the ideal a/d conversion characteristic between the zero voltage and the full-scale voltage. does not include the offset error, full-scale error, or quantization error. ? absolute precision the deviation between the digital value and the analog input value. includes the offset error, full-scale error, quantization error, and nonlinearity error.
section 19 a/d converter rev. 3.00 jan 11, 2005 page 814 of 1220 rej09b0186-0300o 111 110 101 100 011 010 001 000 fs quantization error digital output ideal a/d conversion characteristic analog input volta ge 1 1024 2 1024 1022 1024 1023 1024 figure 19.9 a/d conversion precision definitions (1)
section 19 a/d converter rev. 3.00 jan 11, 2005 page 815 of 1220 rej09b0186-0300o fs offset error nonlinearity error actual a/d conversion characteristic analog input voltage digital output ideal a/d conversion characteristic full-scale error figure 19.10 a/d conversion precision definitions (2) (5) permissible signal source impedance h8s/2643 group analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 5 k ? or less. this specification is provided to enable the a/d converter?s sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k ? , charging may be insufficient and it may not be possible to guarantee the a/d conversion precision. however, if a large capacitance is provided externally, the input load w ill essentially comprise only the internal input resistance of 10 k ? , and the signal source impedance is ignored. however, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mv/s or greater). when converting a high-speed analog signal, a low-impedance buffer should be inserted.
section 19 a/d converter rev. 3.00 jan 11, 2005 page 816 of 1220 rej09b0186-0300o (6) influences on absolute precision adding capacitance results in coupling with gnd, and therefore noise in gnd may adversely affect absolute precision. be sure to make the connection to an electrically stable gnd such as avss. care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. a/d converter equivalent circuit h8s/2643 group 20 pf c in = 15 pf 10 k ? to 5 k ? low-pass filter c to 0.1 f sensor output impedance sensor input figure 19.11 example of analog input circuit
section 20 d/a converter rev. 3.00 jan 11, 2005 page 817 of 1220 rej09b0186-0300o section 20 d/a converter 20.1 overview the h8s/2643 group has an on-chip d/a converter module with four channels. 20.1.1 features features of the d/a converter module are listed below. ? eight-bit resolution ? four-channel output ? maximum conversion time: 10 s (with 20-pf load capacitance) ? output voltage: 0 v to vref ? d/a output retention in software standby mode ? possible to set module stop mode ? operation of d/a converter is disenabled by initial values. it is possible to access the register by canceling module stop mode. 20.1.2 block diagram figure 20.1 shows a block diagram of the d/a converter.
section 20 d/a converter rev. 3.00 jan 11, 2005 page 818 of 1220 rej09b0186-0300o bus interface module data bus internal data bus 8-bit d/a dadr0 (dadr2) dadr1 (dadr3) dacr control circuit legend: dacr: dadr0 to dadr3: d/a control register d/a data re g ister 0 to 3 vref avcc da1 (da3) da0 (da2) avss figure 20.1 block diagram of d/a converter
section 20 d/a converter rev. 3.00 jan 11, 2005 page 819 of 1220 rej09b0186-0300o 20.1.3 input and output pins table 20.1 lists the input and output pins used by the d/a converter module. table 20.1 input and output pins of d/a converter module name abbreviation i/o function analog supply voltage avcc input power supply for analog circuits analog ground avss i nput ground and reference voltage for analog circuits analog output 0 da0 output analog output channel 0 analog output 1 da1 output analog output channel 1 analog output 2 da2 output analog output channel 2 analog output 3 da3 output analog output channel 3 reference voltage vref input reference voltage of analog section 20.1.4 register configuration table 20.2 lists the registers of the d/a converter module. table 20.2 d/a converter registers channel name abbreviation r/w initial value address * 0, 1 d/a data register 0 dadr0 r/w h'00 h'ffa4 d/a data register 1 dadr1 r/w h'00 h'ffa5 d/a control register 01 dacr01 r/w h'1f h'ffa6 2, 3 d/a data register 2 dadr2 r/w h'00 h'fdac d/a data register 3 dadr3 r/w h'00 h'fdad d/a control register 23 dacr23 r/w h'1f h'fdae all module stop control register a mstpcra r/w h'3f h'fde8 module stop control register c mstpcrc r/w h'ff h'fdea note: * lower 16 bits of the address.
section 20 d/a converter rev. 3.00 jan 11, 2005 page 820 of 1220 rej09b0186-0300o 20.2 register descriptions 20.2.1 d/a data registers 0 to 3 (dadr0 to dadr3) 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : d/a data registers 0 to 3 (dadr0 to dadr3) are 8-bit readable/writable registers that store data to be converted. when analog output is enabled, the value in the d/a data register is converted and output continuously at the analog output pin. the d/a data registers are initialized to h'00 by a reset and in hardware standby mode. 20.2.2 d/a control registers 01 and 23 (dacr01 and dacr23) 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 0 r/w 4 ? 1 ? 3 ? 1 ? 0 ? 1 ? 2 ? 1 ? 1 ? 1 ? bit initial value r/w : : : dacr01 and dacr23 are an 8-bit readable/writable register that controls the operation of the d/a converter module. dacr01 and dacr23 are initialized to h'1f by a reset and in hardware standby mode. bit 7?d/a output enable 1 (daoe1): controls d/a conversion and analog output. bit 7 daoe1 description 0 analog output da1 (da3) is disabled (initial value) 1 d/a conversion is enabled on channel 1. analog output da1 (da3) is enabled
section 20 d/a converter rev. 3.00 jan 11, 2005 page 821 of 1220 rej09b0186-0300o bit 6?d/a output enable 0 (daoe0): controls d/a conversion and analog output. bit 6 daoe0 description 0 analog output da0 (da2) is disabled (initial value) 1 d/a conversion is enabled on channel 0. analog output da0 (da2) is enabled bit 5?d/a enable (dae): controls d/a conversion, in combination with bits daoe0 and daoe1. d/a conversion is controlled independently on channels 0 and 1 when dae = 0. channels 0 and 1 are controlled together when dae = 1. output of the converted results is always controlled independently by daoe0 and daoe1. bit 7 bit 6 bit 5 daoe1 daoe0 dae d/a conversion 00 * disabled on channels 0 and 1 (channels 2 and 3) 1 0 enabled on channel 0 (channel 2) disabled on channel 1 (channel 3) 1 enabled on channels 0 and 1 (channels 2 and 3) 100disabled on channel 0 (channel 2) enabled on channel 1 (channel 3) 1 enabled on channels 0 and 1 (channels 2 and 3) 1 * enabled on channels 0 and 1 (channels 2 and 3) * : don?t care if the h8s/2643 group chip enters software standby mode while d/a conversion is enabled, the d/a output is retained and the analog power supply current is the same as during d/a conversion. if it is necessary to reduce the analog power supply current in software standby mode, disable d/a output by clearing both the daoe0 and daoe1 bits to 0. bits 4 to 0?reserved: these bits cannot be modified and are always read as 1.
section 20 d/a converter rev. 3.00 jan 11, 2005 page 822 of 1220 rej09b0186-0300o 20.2.3 module stop control registers a and c (mstpcra and mstpcrc) 7 mstpa7 0 r/w 6 mstpa6 0 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 0 mstpa0 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w bit initial value r/w : : : mstpcra 7 mstpc7 1 r/w 6 mstpc6 1 r/w 5 mstpc5 1 r/w 4 mstpc4 1 r/w 3 mstpc3 1 r/w 0 mstpc0 1 r/w 2 mstpc2 1 r/w 1 mstpc1 1 r/w bit initial value r/w : : : mstpcrc mstpcra and mstpcrc are 8-bit readable/writable registers that performs module stop mode control. when the mstpa2 and mstpc5 are set to 1, the d/a converter halts and enters module stop mode at the end of the bus cycle. register read/write is disenabled in module stop mode. see section 24.5, module stop mode, for details. mstpcra is initialized to h'3f by a power-on reset and in hardware standby mode. mstpcrc is initialized to h'ff by a power-on reset and in hardware standby mode. it is not initialized by a manual reset and in software standby mode.
section 20 d/a converter rev. 3.00 jan 11, 2005 page 823 of 1220 rej09b0186-0300o (1) module stop control register a (mstpcra) bit 2?module stop (mstpa2): specifies d/a converter (channels 0 and 1) module stop mode. bit 2 mstpa2 description 0 d/a converter (channels 0 and 1) module stop mode is cleared 1 d/a converter (channels 0 and 1) module stop mode is set (initial value) (2) module stop control register c (mstpcrc) bit 5?module stop (mstpc5): specifies d/a converter (channels 2 and 3) module stop mode. bit 5 mstpc5 description 0 d/a converter (channels 2 and 3) module stop mode is cleared 1 d/a converter (channels 2 and 3) module stop mode is set (initial value) 20.3 operation the d/a converter module has two built-in d/a converter circuits that can operate independently. d/a conversion is performed continuously whenever enabled by the d/a control register (dacr). when a new value is written in dadr0 or dadr1, conversion of the new value begins immediately. the converted result is output by setting the daoe0 or daoe1 bit to 1. an example of conversion on channel 0 is given next. figure 20.2 shows the t iming. ? software writes the data to be converted in dadr0. ? d/a conversion begins when the daoe0 bit in dacr is set to 1. after the elapse of the conversion time, analog output appears at the da0 pin. the output value is vref (dadr0 value)/256. this output continues until a new value is written in dadr0 or the daoe0 bit is cleared to 0. ? if a new value is written in dadr0, conversion begins immediately. output of the converted result begins after the conversion time. ? when the daoe0 bit is cleared to 0, da0 becomes an input pin.
section 20 d/a converter rev. 3.00 jan 11, 2005 page 824 of 1220 rej09b0186-0300o dadr0 write cycle dacr write cycle dadr0 write cycle dacr write cycle address dadr0 daoe0 da0 conversion data (1) conversion data (2) high-impedance state conversion result (1) conversion result (2) t dconv t dconv t : d/a conversion time legend: dconv figure 20.2 d/a conversion (example)
section 21 ram rev. 3.00 jan 11, 2005 page 825 of 1220 rej09b0186-0300o section 21 ram 21.1 overview the h8s/2643 has 16 kbytes of on-chip high-speed static ram, the h8s/2642 has 12 kbytes, and the h8s/2641 has 8 kbytes. the ram is connected to the cpu by a 16-bit data bus, enabling one- state access by the cpu to both byte data and word data. this makes it possible to perform fast word data transfer. the on-chip ram can be enabled or disabled by means of the ram enable bit (rame) in the system control register (syscr). 21.1.1 block diagram figure 21.1 shows a block diagram of the on-chip ram. internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'ffb000 h'ffb002 h'ffb004 h'ffffc0 h'ffb001 h'ffb003 h'ffb005 h'ffffc1 h'fffffe h'ffffff h'ffefbe h'ffefbf figure 21.1 block diagram of ram (h8s/2643 group)
section 21 ram rev. 3.00 jan 11, 2005 page 826 of 1220 rej09b0186-0300o 21.1.2 register configuration the on-chip ram is controlled by syscr. table 21.1 shows the address and initial value of syscr. table 21.1 ram register name abbreviation r/w initial value address * system control register syscr r/w h'01 h'fde5 note: * lower 16 bits of the address. 21.2 register descriptions 21.2.1 system control register (syscr) 7 macs 0 r/w 6 ? 0 ? 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 mrese 0 r/w 1 ? 0 ? bit initial value r/w : : : the on-chip ram is enabled or disabled by the rame bit in syscr. for details of other bits in syscr, see section 3.2.2, system control register (syscr). bit 0?ram enable (rame): enables or disables the on-chip ram. the rame bit is initialized when the reset state is released. it is not initialized in software standby mode. note: when the dtc is used, the rame bit must be set to 1. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value)
section 21 ram rev. 3.00 jan 11, 2005 page 827 of 1220 rej09b0186-0300o 21.3 operation when the rame bit is set to 1, accesses to addresses h'ffb000 to h'ffefbf and h'ffffc0 to h'ffffff in the h8s/2643, to addresses h'ffc000 to h'ffefbf and h'ffffc0 to h'ffffff in the h8s/2642, and to addresses h'ffd000 to h'ffefbf and h'ffffc0 to h'ffffff in the h8s/2641, are directed to the on-chip ram. when the rame bit is cleared to 0, the off-chip address space is accessed. since the on-chip ram is connected to the cpu by an internal 16-bit data bus, it can be written to and read in byte or word units. each type of access can be performed in one state. even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. word data must start at an even address. 21.4 usage notes (1) when using the dtc dtc register information can be located in addresses h'ffebc0 to h'ffefbf. when the dtc is used, the rame bit must not be cleared to 0. (2) reserved areas addresses h'ffb000 to h'ffbfff in the h8s/2642, and h'ffb000 to h'ffcfff in the h8s/2641 are reserved areas that cannot be read or written to. when the rame bit is cleared to 0, the off-chip address space is accessed.
section 21 ram rev. 3.00 jan 11, 2005 page 828 of 1220 rej09b0186-0300o
section 22 rom rev. 3.00 jan 11, 2005 page 829 of 1220 rej09b0186-0300o section 22 rom 22.1 overview the h8/2643 group has 256 kbytes of on-chip flash memory, or 256 , 192 , or 128 kbytes of on- chip mask rom. the rom is connected to the bus master via a 16-bit data bus, enabling both byte and word data to be accessed in one state. instruction fetching is thus speeded up, and processing speed increased. the on-chip rom is enabled and disabled by setting the mode pins (md2 to md0). the flash memory version can be erased and programmed on-board, as well as with a special- purpose prom programmer. 22.1.1 block diagram figure 22.1 shows a block diagram of 256-kbyte rom. internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'000000 h'000002 h'03fffe h'000001 h'000003 h'03ffff figure 22.1 block diagram of rom (256 kbytes) 22.1.2 register configuration the h8/2643 group operating mode is controlled by the mode pins and the bcrl register. the register configuration is shown in table 22.1.
section 22 rom rev. 3.00 jan 11, 2005 page 830 of 1220 rej09b0186-0300o table 22.1 register configuration register name abbreviation r/w initial value address * mode control register mdcr r/w undefined h'fde7 note: * lower 16 bits of the address. 22.2 register descriptions 22.2.1 mode control register (mdcr) bit:76543210 ?????mds2mds1mds0 initial value:10000? * ? * ? * r/w:r/w???? r r r note: * determined by pins md2 to md0. mdcr is an 8-bit read-only register used to monitor the current h8/2643 group operating mode. bit 7?reserved: only 1 should be written to this bit. bits 6 to 3?reserved: read-only bits, always read as 0. bits 2 to 0?mode select 2 to 0 (mds2 to mds0): these bits indicate the input levels at pins md2 to md0 (the current operating mode). bits mds2 to mds0 correspond to pins md2 to md0. mds2 to mds0 are read-only bits, and cannot be modified. the mode pin (md2 to md0) input levels are latched into these bits when mdcr is read. these latches are canceled by a power-on reset, but are retained in a manual reset. 22.3 operation the on-chip rom is connected to the cpu by a 16-bit data bus, and both byte and word data can be accessed in one state. even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. word data must start at an even address. the on-chip rom is enabled and disabled by setting the mode pins (md2 to md0). these settings are shown in table 22.2.
section 22 rom rev. 3.00 jan 11, 2005 page 831 of 1220 rej09b0186-0300o table 22.2 operating modes and rom (f-ztat version) mode pins operating mode fwe md2 md1 md0 on-chip rom mode 0 ? 0 0 0 0 ? mode 1 1 mode 2 1 0 mode 3 1 mode 4 advanced expanded mode with on-chip rom disabled 1 0 0 disabled mode 5 advanced expanded mode with on-chip rom disabled 1 mode 6 advanced expanded mode with on-chip rom enabled 1 0 enabled (256 kbytes) mode 7 advanced single-chip mode 1 enabled (256 kbytes) mode 8 ? 1 0 0 0 ? mode 9 1 mode 10 boot mode (advanced expanded mode with on-chip rom enabled) * 1 1 0 enabled (256 kbytes) mode 11 boot mode (advanced single-chip mode) * 2 1 enabled (256 kbytes) mode 12 ? 1 0 0 ? mode 13 1 mode 14 user program mode (advanced expanded mode with on-chip rom enabled) * 1 10 enabled (256 kbytes) mode 15 user program mode (advanced single- chip mode) * 2 1 enabled (256 kbytes) notes: 1. apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced expanded mode with on-chip rom enabled. 2. apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced single-chip mode.
section 22 rom rev. 3.00 jan 11, 2005 page 832 of 1220 rej09b0186-0300o table 22.3 operating modes and rom (masked rom version) mode pins operating mode md2 md1 md0 on-chip rom mode 0 ? 0 0 0 ? mode 1 1 mode 2 1 0 mode 3 1 mode 4 advanced expanded mode with on-chip rom disabled 100disabled mode 5 advanced expanded mode with on-chip rom disabled 1 mode 6 advanced expanded mode with on-chip rom enabled 1 0 enabled (256 kbytes) * mode 7 advanced single-chip mode 1 enabled (256 kbytes) * note: * in the case of the h8s/2643. 192 kbytes are enabled in the h8s/2642, and 128 kbytes in the h8s/2641.
section 22 rom rev. 3.00 jan 11, 2005 page 833 of 1220 rej09b0186-0300o 22.4 flash memory overview 22.4.1 features the h8s/2643 group has 256 kbytes of on-chip flash memory. the features of the flash memory are summarized below. ? four flash memory operating modes ? program mode ? erase mode ? program-verify mode ? erase-verify mode ? programming/erase methods the flash memory is programmed 128 bytes at a time. block erase (in single-block units) can be performed. to erase the entire flash memory, each block must be erased in turn. block erasing can be performed as required on 4 kbytes, 32 kbytes, and 64 kbytes blocks. ? programming/erase times the flash memory programming time is 10 ms (typ.) for simultaneous 128-byte progra mming, equivalent to 78 s (typ.) per byte, and the erase time is 100 ms (typ.). ? reprogramming capability the flash memory can be reprogrammed up to 100 times. ? on-board programming modes there are two modes in which flash memory can be programmed/erased/verified on-board: ? boot mode ? user program mode ? automatic bit rate adjustment with data transfer in boot mode, the lsi?s bit rate can be automatically adjusted to match the transfer bit rate of the host. ? flash memory emulation in ram flash memory programming can be emulated in real time by overlapping a part of ram onto flash memory. ? protect modes there are three protect modes, hardware, software, and error protection, which allow protected status to be designated for flash memory program/erase/verify operations. ? programmer mode flash memory can be programmed/erased in programmer mode, using a prom programmer, as well as in on-board programming mode.
section 22 rom rev. 3.00 jan 11, 2005 page 834 of 1220 rej09b0186-0300o 22.4.2 overview (1) block diagram module bus bus interface/controller flash memory (256 kbytes) operating mode flmcr2 internal address bus internal data bus (16 bits) fwe pin mode pin ebr1 ebr2 ramer flpwcr flmcr1 flash memory control register 1 flash memory control register 2 erase block register 1 erase block register 2 ram emulation register flash memory power control register legend: flmcr1: flmcr2: ebr1: ebr2: ramer: flpwcr: figure 22.2 block diagram of flash memory
section 22 rom rev. 3.00 jan 11, 2005 page 835 of 1220 rej09b0186-0300o 22.4.3 flash memory operating modes (1) mode transitions when the mode pins and the fwe pin are set in the reset state and a reset-start is executed, the microcomputer enters an operating mode as shown in figure 22.3. in user mode, flash memory can be read but not programmed or erased. the boot, user program and programmer modes are provided as modes to write and erase the flash memory. boot mode on-board programming mode user program mode user mode (on-chip rom enabled) reset state programmer mode res = 0 fwe = 1 fwe = 0 * 1 * 1 * 2 notes: only make a transition between user mode and user program mode when the cpu is not accessing the flash memory. 1. ram emulation possible 2. md0 = 0, md1 = 0, md2 = 0, p14 = 0, p16 = 0, pf0 = 1 res = 0 md1 = 0, md2 = 0, fwe = 1 res = 0 res = 0 md1 = 1, md2 = 1, fwe = 0 md1 = 1, md2 = 1, fwe = 1 figure 22.3 flash memory state transitions
section 22 rom rev. 3.00 jan 11, 2005 page 836 of 1220 rej09b0186-0300o 22.4.4 on-board programming modes (1) boot mode flash memory h8s/2643 ram host programming control program sci application program (old version) new application program flash memory h8s/2643 ram host sci application program (old version) boot program area new application program flash memory h8s/2643 ram host sci flash memory preprogramming erase boot program new application program flash memory h8s/2643 program execution state ram host sci new application program boot program programming control program 1. initial state the old program version or data remains written in the flash memory. the user should prepare the programming control program and new application program beforehand in the host. 2. programming control program transfer when boot mode is entered, the boot program in the h8s/2643 (originally incorporated in the chip) is started and the programming control program in the host is transferred to ram via sci communication. the boot program required for flash memory erasing is automatically transferred to the ram boot program area. 3. flash memory initialization the erase program in the boot program area (in ram) is executed, and the flash memory is initialized (to h'ff). in boot mode, total flash memory erasure is performed, without regard to blocks. 4. writing new application program the programming control program transferred from the host to ram is executed, and the new application program in the host is written into the flash memory. programming control program boot program boot program boot program area boot program area programming control program
section 22 rom rev. 3.00 jan 11, 2005 page 837 of 1220 rej09b0186-0300o (2) user program mode flash memory h8s/2643 ram host programming/ erase control program sci boot program new application program flash memory h8s/2643 ram host sci new application program flash memory h8s/2643 ram host sci flash memory erase boot program new application program flash memory h8s/2643 program execution state ram host sci boot program boot program fwe assessment program application program (old version) new application program 1. initial state the fwe assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip ram should be written into the flash memory by the user beforehand. the programming/erase control program should be prepared in the host or in the flash memory. 2. programming/erase control program transfer when user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to ram. 3. flash memory initialization the programming/erase program in ram is executed, and the flash memory is initialized (to h'ff). erasing can be performed in block units, but not in byte units. 4. writing new application program next, the new application program in the host is written into the erased flash memory blocks. do not write to unerased blocks. programming/ erase control program programming/ erase control program programming/ erase control program transfer program application program (old version) transfer program fwe assessment program fwe assessment program transfer program fwe assessment program transfer program
section 22 rom rev. 3.00 jan 11, 2005 page 838 of 1220 rej09b0186-0300o 22.4.5 flash memory emulation in ram emulation should be performed in user mode or user program mode. when the emulation block set in ramer is accessed while the emulation function is being executed, data written in the overlap ram is read. application program execution state flash memory emulation block ram sci overlap ram (emulation is performed on data written in ram) figure 22.4 reading overlap ram data in user mode or user program mode when overlap ram data is confirmed, the rams bit is cleared, ram overlap is released, and writes should actually be performed to the flash memory. when the programming control program is transferred to ram, ensure that the transfer destination and the overlap ram do not overlap, as this will cause data in the overlap ram to be rewritten.
section 22 rom rev. 3.00 jan 11, 2005 page 839 of 1220 rej09b0186-0300o application program flash memory ram sci programming control program execution state overlap ram (programming data) programming data figure 22.5 writing overlap ram data in user program mode 22.4.6 differences between boot mode and user program mode table 22.4 differences between boot mode and user program mode boot mode user program mode total erase yes yes block erase no yes programming control program * program/program-verify erase/erase-verify program/program-verify emulation note: * to be provided by the user, in accordance with the recommended algorithm.
section 22 rom rev. 3.00 jan 11, 2005 page 840 of 1220 rej09b0186-0300o 22.4.7 block configuration the flash memory is divided into three 64 kbytes blocks, one 32 kbytes block, and eight 4 kbytes blocks. address h'00000 address h'3ffff 64 kbytes 32 kbytes 64 kbytes 64 kbytes 256 kbytes 4 kbytes 8 figure 22.6 flash memory block configuration
section 22 rom rev. 3.00 jan 11, 2005 page 841 of 1220 rej09b0186-0300o 22.4.8 pin configuration the flash memory is controlled by means of the pins shown in table 22.5. table 22.5 pin configuration pin name abbreviation i/o function reset res input reset flash write enable fwe input flash memory program/erase protection by hardware mode 2 md2 input sets mcu operating mode mode 1 md1 input sets mcu operating mode mode 0 md0 input sets mcu operating mode port f0 pf0 input sets mcu operating mode in programmer mode port 16 p16 input sets mcu operating mode in programmer mode port 14 p14 input sets mcu operating mode in programmer mode transmit data txd2 output serial transmit data output receive data rxd2 input serial receive data input
section 22 rom rev. 3.00 jan 11, 2005 page 842 of 1220 rej09b0186-0300o 22.4.9 register configuration the registers used to control the on-chip flash memory when enabled are shown in table 22.6. in order to access these registers, the flshe bit in scrx must be set to 1 (except for ramer, scrx). table 22.6 register configuration register name abbreviation r/w initial value address * 1 flash memory control register 1 flmcr1 * 5 r/w * 2 h'00 * 3 h'ffa8 flash memory control register 2 flmcr2 * 5 r * 2 h'00 h'ffa9 erase block register 1 ebr1 * 5 r/w * 2 h'00 * 4 h'ffaa erase block register 2 ebr2 * 5 r/w * 2 h'00 * 4 h'ffab ram emulation register ramer * 5 r/w h'00 h'fedb flash memory power control register flpwcr * 5 r/w * 2 h'00 * 4 h'ffac serial control register x scrx r/w h'00 h'fdb4 notes: 1. lower 16 bits of the address. 2. to access these registers, set the flshe bit to 1 in serial control register x. even if flshe is set to 1, if the chip is in a mode in which the on-chip flash memory is disabled, a read will return h'00 and writes are invalid. writes are also invalid when the fwe bit in flmcr1 is not set to 1. 3. when a high level is input to the fwe pin, the initial value is h'80. 4. when a low level is input to the fwe pin, or if a high level is input and the swe1 bit in flmcr1 is not set, these registers are initialized to h'00. 5. flmcr1, flmcr2, ebr1, and ebr2, ramer, and flpwcr are 8-bit registers. use byte access on these registers. 22.5 register descriptions 22.5.1 flash memory control register 1 (flmcr1) flmcr1 is an 8-bit register used for flash memory operating mode control. program-verify mode or erase-verify mode for addresses h'00000 to h'3ffff is entered by setting swe1 bit to 1 when fwe = 1, then setting the pv1 or ev1 bit. program mode for addresses h'00000 to h'3ffff is entered by setting swe1 bit to 1 when fwe = 1, then setting the psu1 bit, and finally setting the p1 bit. erase mode for addresses h'00000 to h'3ffff is entered by setting swe1 bit to 1 when fwe = 1, then setting the esu1 bit, and finally setting the e1 bit. flmcr1 is initialized by a power-on reset, and in hardware standby mode and software standby mode. its initial value is h'80 when a high level is input to the fwe pin, and h'00 when a low level is input. when on-chip flash memory is disabled, a read will return h' 00, and writes are invalid.
section 22 rom rev. 3.00 jan 11, 2005 page 843 of 1220 rej09b0186-0300o writes are enabled only in the following cases: writes to bit swe1 of flmcr1 enabled when fwe = 1, to bits esu1, psu1, ev1, and pv1 when fwe = 1 and swe1 = 1, to bit e1 when fwe = 1, swe1 = 1 and esu1 = 1, and to bit p1 when fwe = 1, swe1 = 1, and psu1 = 1. bit:76543210 fwe swe1 esu1 psu1 ev1 pv1 e1 p1 initial value: ? * 0000000 r/w: r r/w r/w r/w r/w r/w r/w r/w note: * determined by the state of the fwe pin. bit 7?flash write enable bit (fwe): sets hardware protection against flash memory programming/erasing. bit 7 fwe description 0 when a low level is input to the fwe pin (hardware-protected state) 1 when a high level is input to the fwe pin bit 6?software write enable bit 1 (swe1): this bit selects write and erase valid/invalid of the flash memory. set it when setting bits 5 to 0, bits 7 to 0 of ebr1, and bits 3 to 0 of ebr2. bit 6 swe1 description 0 writes disabled (initial value) 1 writes enabled [setting condition] ? when fwe = 1
section 22 rom rev. 3.00 jan 11, 2005 page 844 of 1220 rej09b0186-0300o bit 5?erase setup bit 1 (esu1): prepares for a transition to erase mode. set this bit to 1 before setting the e1 bit in flmcr1 to 1. do not set the swe1, psu1, ev1, pv1, e1, or p1 bit at the same time. bit 5 esu1 description 0 erase setup cleared (initial value) 1 erase setup [setting condition] ? when fwe = 1 and swe1 = 1 bit 4?program setup bit 1 (psu1): prepares for a transition to program mode. set this bit to 1 before setting the p1 bit in flmcr1 to 1. do not set the swe1, esu1, ev1, pv1, e1, or p1 bit at the same time. bit 4 psu1 description 0 program setup cleared (initial value) 1 program setup [setting condition] ? when fwe = 1 and swe1 = 1 bit 3?erase-verify 1 (ev1): selects erase-verify mode transition or clearing. do not set the swe1, esu1, psu1, pv1, e1, or p1 bit at the same time. bit 3 ev1 description 0 erase-verify mode cleared (initial value) 1 transition to erase-verify mode [setting condition] ? when fwe = 1 and swe1 = 1
section 22 rom rev. 3.00 jan 11, 2005 page 845 of 1220 rej09b0186-0300o bit 2?program-verify 1 (pv1): selects program-verify mode transition or clearing. do not set the swe1, esu1, psu1, ev1, e1, or p1 bit at the same time. bit 2 pv1 description 0 program-verify mode cleared (initial value) 1 transition to program-verify mode [setting condition] ? when fwe = 1 and swe1 = 1 bit 1?erase 1 (e1): selects erase mode transition or clearing. do not set the swe1, esu1, psu1, ev1, pv1, or p1 bit at the same time. bit 1 e1 description 0 erase mode cleared (initial value) 1 transition to erase mode [setting condition] ? when fwe = 1, swe1 = 1, and esu1 = 1 bit 0?program 1 (p1): selects program mode transition or clearing. do not set the swe1, psu1, esu1, ev1, pv1, or e1 bit at the same time. bit 0 p1 description 0 program mode cleared (initial value) 1 transition to program mode [setting condition] ? when fwe = 1, swe1 = 1, and psu1 = 1
section 22 rom rev. 3.00 jan 11, 2005 page 846 of 1220 rej09b0186-0300o 22.5.2 flash memory control register 2 (flmcr2) flmcr2 is an 8-bit register used for flash memory operating mode control. flmcr2 is initialized to h'00 by a power-on reset, and in hardware standby mode and software standby mode. when on-chip flash memory is disabled, a read will return h'00. bit:76543210 fler ??????? initial value:00000000 r/w: r ??????? note: flmcr2 is a read-only register, and should not be written to. bit 7?flash memory error (fler): indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error- protection state. bit 7 fler description 0 flash memory is operating normally (initial value) flash memory program/erase protection (error protection) is disabled [clearing condition] ? power-on reset or hardware standby mode 1 an error has occurred during flash memory programming/erasing flash memory program/erase protection (error protection) is enabled [setting condition] ? see section 22.8.3, error protection bits 6 to 0?reserved: these bits always read 0.
section 22 rom rev. 3.00 jan 11, 2005 page 847 of 1220 rej09b0186-0300o 22.5.3 erase block register 1 (ebr1) ebr1 is an 8-bit register that specifies the flash memory erase area block by block. ebr1 is initialized to h'00 by a power-on reset, in hardware standby mode and software standby mode, when a low level is input to the fwe pin, and when a high level is input to the fwe pin and the swe1 bit in flmcr1 is not set. when a bit in ebr1 is set to 1, the corresponding block can be erased. other blocks are erase-protected. only one of the bits of ebr1 and ebr2 combined can be set. do not set more than one bit, as this will cause all the bits in both ebr1 and ebr2 to be automatically cleared to 0. when on-chip flash memory is disabled, a read will return h' 00, and writes are invalid. the flash memory erase block configuration is shown in table 22.7. bit:76543210 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 22.5.4 erase block register 2 (ebr2) ebr2 is an 8-bit register that specifies the flash memory erase area block by block. ebr2 is initialized to h'00 by a power-on reset, in hardware standby mode and software standby mode, when a low level is input to the fwe pin. bit 0 w ill be initialized to 0 if bit swe1 of flmcr1 is not set, even though a high level is input to pin fwe. when a bit in ebr2 is set to 1, the corresponding block can be erased. other blocks are erase-protected. only one of the bits of ebr1 and ebr2 combined can be set. do not set more than one bit, as this will cause all the bits in both ebr1 and ebr2 to be automatically cleared to 0. bits 7 to 4 are reserved and must only be written with 0. when on-chip flash memory is disabled, a read will return h'00, and writes are invalid. the flash memory erase block configuration is shown in table 22.7. bit:76543210 ???? eb11 eb10 eb9 eb8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w
section 22 rom rev. 3.00 jan 11, 2005 page 848 of 1220 rej09b0186-0300o table 22.7 flash memory erase blocks block (size) addresses eb0 (4 kbytes) h'000000 to h'000fff eb1 (4 kbytes) h'001000 to h'001fff eb2 (4 kbytes) h'002000 to h'002fff eb3 (4 kbytes) h'003000 to h'003fff eb4 (4 kbytes) h'004000 to h'004fff eb5 (4 kbytes) h'005000 to h'005fff eb6 (4 kbytes) h'006000 to h'006fff eb7 (4 kbytes) h'007000 to h'007fff eb8 (32 kbytes) h'008000 to h'00ffff eb9 (64 kbytes) h'010000 to h'01ffff eb10 (64 kbytes) h'020000 to h'02ffff eb11 (64 kbytes) h'030000 to h'03ffff 22.5.5 ram emulation register (ramer) ramer specifies the area of flash memory to be overlapped with part of ram when emulating real-time flash memory programming. ramer initialized to h'00 by a power-on reset and in hardware standby mode. it is not initialized by a manual reset and in software standby mode. ramer settings should be made in user mode or user program mode. flash memory area divisions are shown in table 22.8. to ensure correct operation of the emulation function, the rom for which ram emulation is performed should not be accessed immediately after this register has been modified. normal execution of an access immediately after register modification is not guaranteed. bit:76543210 ???? rams ram2 ram1 ram0 initial value:00000000 r/w: r r r/w r/w r/w r/w r/w r/w bits 7 and 6?reserved: these bits always read 0. bits 5 and 4?reserved: only 0 may be written to these bits.
section 22 rom rev. 3.00 jan 11, 2005 page 849 of 1220 rej09b0186-0300o bit 3?ram select (rams): specifies selection or non-selection of flash memory emulation in ram. when rams = 1, all flash memory block are program/erase-protected. bit 3 rams description 0 emulation not selected (initial value) program/erase-protection of all flash memory blocks is disabled 1 emulation selected program/erase-protection of all flash memory blocks is enabled bits 2 to 0?flash memory area selection: these bits are used together with bit 3 to select the flash memory area to be overlapped with ram. (see table 22.8.) table 22.8 flash memory area divisions addresses block name rams ram1 ram1 ram0 h'ffd000 to h'ffdfff ram area 4 kbytes 0 *** h'000000 to h'000fff eb0 (4 kbytes) 1 0 0 0 h'001000 to h'001fff eb1 (4 kbytes) 1 0 0 1 h'002000 to h'002fff eb2 (4 kbytes) 1 0 1 0 h'003000 to h'003fff eb3 (4 kbytes) 1 0 1 1 h'004000 to h'004fff eb4 (4 kbytes) 1 1 0 0 h'005000 to h'005fff eb5 (4 kbytes) 1 1 0 1 h'006000 to h'006fff eb6 (4 kbytes) 1 1 1 0 h'007000 to h'007fff eb7 (4 kbytes) 1 1 1 1 * : don't care
section 22 rom rev. 3.00 jan 11, 2005 page 850 of 1220 rej09b0186-0300o 22.5.6 flash memory power control register (flpwcr) bit:76543210 pdwnd ??????? initial value:00000000 r/w:r/wrrrrrrr flpwcr enables or disables a transition to the flash memory power-down mode when the lsi switches to subactive mode. bit 7?power-down disable (pdwnd): enables or disables a transition to the flash memory power-down mode when the lsi switches to subactive mode. bit 7 pdwnd description 0 transition to flash memory power-down mode enabled (initial value) 1 transition to flash memory power-down mode disabled bits 6 to 0?reserved: these bits always read 0. 22.5.7 serial control register x (scrx) bit:76543210 ? iicx1 iicx0 iice flshe ??? initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w scrx is an 8-bit readable/writable register that controls on-chip flash memory. scrx is initialized to h'00 by a reset and in hardware standby mode. bit 7?reserved: this bit should always be written with 0. bits 6 and 5?i 2 c transfer rate select (iicx1, iicx0): these bits, together with bits cks2 to cks0 in icmr, select the transfer rate in master mode. for details of the transfer rate, see section 18.2.4, i 2 c bus mode register (icmr).
section 22 rom rev. 3.00 jan 11, 2005 page 851 of 1220 rej09b0186-0300o bit 4?i 2 c master enable (iice): controls access to the i 2 c bus interface data registers and control registers (iccr, icsr, icdr/sarx, icmr/sar). for details of the control, see section 18.2.7, serial control register x (scrx). bit 3?flash memory control register enable (flshe): controls cpu access to the flash memory control registers (flmcr1, flmcr2, ebr1, and ebr2). setting the flshe bit to 1 enables read/write access to the flash memory control registers. if flshe is cleared to 0, the flash memory control registers are deselected. in this case, the flash memory control register contents are retained. bit 3 flshe description 0 flash control registers deselected in area h'ffffa8 to h'ffffac (initial value) 1 flash control registers selected in area h'ffffa8 to h'ffffac bits 2 to 0?reserved: should always be written with 0. 22.6 on-board programming modes when pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. there are two on-board programming modes: boot mode and user program mode. the pin settings for transition to each of these modes are shown in table 22.9. for a diagram of the transitions to the various flash memory modes, see figure 22.11. table 22.9 setting on-board programming modes mode fwe md2 md1 md0 boot mode expanded mode 1 0 1 0 single-chip mode 0 1 1 user program mode expanded mode 1 1 1 0 single-chip mode 1 1 1
section 22 rom rev. 3.00 jan 11, 2005 page 852 of 1220 rej09b0186-0300o 22.6.1 boot mode when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. the sci channel to be used is set to asynchronous mode. when a reset-start is executed after the h8s/2643 group ? s pins have been set to boot mode, the boot program built into the h8s/2643 group is started and the progra mming control program prepared in the host is serially transmitted to the h8s/ 2643 group via the sci. in the h8s/2643 group, the progra mming control program r eceived via the sci is written into the progra mming control program area in on-chip ram. after the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). the transferred programming control program must therefore include coding that follows the programming algorithm given later. the system configuration in boot mode is shown in figure 22.7, and the boot mode execution procedure in figure 22.8. rxd2 txd2 sci2 h8s/2643 group flash memory write data reception verify data transmission host on-chip ram figure 22.7 system configuration in boot mode
section 22 rom rev. 3.00 jan 11, 2005 page 853 of 1220 rej09b0186-0300o note: if a memory cell does not operate normally and cannot be erased, one h'ff byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. start set pins to boot mode and execute reset-start host transfers data (h'00) continuously at prescribed bit rate h8s/2643 measures low period of h'00 data transmitted by host h8s/2643 calculates bit rate and sets value in bit rate register after bit rate adjustment, h8s/2643 transmits one h'00 data byte to host to indicate end of adjustment host confirms normal reception of bit rate adjustment end indication (h'00), and transmits one h'55 data byte after receiving h'55, lsi transmits one h'aa data byte to host host transmits number of programming control program bytes (n), upper byte followed by lower byte h8s/2643 transmits received number of bytes to host as verify data (echo-back) n = 1 host transmits programming control program sequentially in byte units h8s/2643 transmits received programming control program to host as verify data (echo-back) transfer received programming control program to on-chip ram n = n? no yes end of transmission check flash memory data, and if data has already been written, erase all blocks after confirming that all flash memory data has been erased, h8s/2643 transmits one h'aa data byte to host execute programming control program transferred to on-chip ram n + 1 n figure 22.8 boot mode execution procedure
section 22 rom rev. 3.00 jan 11, 2005 page 854 of 1220 rej09b0186-0300o (1) automatic sci bit rate adjustment start bit stop bit d0 d1 d2 d3 d4 d5 d6 d7 low period (9 bits) measured (h'00 data) high period ( 1 or more bits ) figure 22.9 automatic sci bit rate adjustment when boot mode is initiated, the h8s/2643 group measures the low period of the asynchronous sci communication data (h'00) transmitted conti nuously from the host. the sci trans mit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. the h8s/2643 group calculates the bit rate of the transmission from the host from the measured low period, and transmits one h'00 byte to the host to indicate the end of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the h8s/2643 group. if reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. depending on the host ? s transmission bit rate and the h8s/2643 group ? system clock frequency, there will be a discrepancy between the bit rates of the host and the h8s/2643 group. set the host transfer bit rate at 2,400, 4,800, 9,600 or 19,200 bps to operate the sci properly. table 22.10 shows host transfer bit rates and system clock frequencies for which automatic adjustment of the h8s/2643 group bit rate is possible. the boot program should be executed within this system clock range. table 22.10 system clock frequencies for which automatic adjustment of h8s/2643 group bit rate is possible host bit rate system clock frequency for which automatic adjustment of h8s/2643 group bit rate is possible 2,400 bps 2 to 8 mhz 4,800 bps 4 to 16 mhz 9,600 bps 8 to 25 mhz 19,200 bps 16 to 25 mhz
section 22 rom rev. 3.00 jan 11, 2005 page 855 of 1220 rej09b0186-0300o (2) on-chip ram area divisions in boot mode in boot mode, the ram area is divided into an area used by the boot program and an area to which the programming control program is transferred via the sci, as shown in figure 22. 10. the boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host. h'ffc000 h'ffdfff h'ffe000 h'ffefbf boot program area (4 kbytes) programming control program area (8 kbytes) note: the boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to ram. note also that the boot program remains in this area of the on-chip ram even after control branches to the programming control program. figure 22.10 ram areas in boot mode (3) notes on use of boot mode ? when the chip comes out of reset in boot mode, it measures the low-level period of the input at the sci ? s rxd2 pin. the reset should end with rxd2 high. after the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period of the rxd2 pin. ? in boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. ? interrupts cannot be used while the flash memory is being programmed or erased. ? the rxd2 and txd2 pins should be pulled up on the board. ? before branching to the programming control program (ram area h'ffc 000), the chip terminates transmit and receive operations by the on-chip sci (channel 2) (by clearing the re
section 22 rom rev. 3.00 jan 11, 2005 page 856 of 1220 rej09b0186-0300o and te bits in scr to 0), but the adjusted bit rate value remains set in brr. the transmit data output pin, txd2, goes to the high-level output state (pa1ddr = 1, pa1dr = 1). the contents of the cpu ? s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. in particular, since the stack pointer (sp) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. the initial values of other on-chip registers are not changed. ? boot mode can be entered by making the pin settings shown in table 22.9 and executing a reset-start. boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the fwe pin and mode pins, and executing reset release* 1 . boot mode can also be cleared by a wdt overflow reset. do not change the mode pin input levels in boot mode, and do not drive the fwe pin low while the boot program is being executed or while flash memory is being programmed or erased* 2 . ? if the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins ( as , rd , hwr ) will change according to the change in the microcomputer ? s operating mode* 3 . therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. notes: 1. mode pin and fwe pin input must satisfy the mode progra mming setup time (t mds = 4 states) with respect to the reset release timing. 2. for further information on fwe application and disconnection, see section 22.13, flash memory programming and erasing precautions. 3. see appendix d, pin states. 22.6.2 user program mode when set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of fwe control and supply of programming data, and storing a program/erase control program in part of the program area as necessary. to select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7), and apply a high level to the fwe pin. in this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7.
section 22 rom rev. 3.00 jan 11, 2005 page 857 of 1220 rej09b0186-0300o the flash memory itself cannot be read while the swe1 bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing s hould be run in on-chip ram or external memory. if the program is to be located in external memory, the instruction for writing to flash memory, and the following instruction, should be placed in on-chip ram. figure 22.11 shows the procedure for executing the program/erase control program when transferred to on-chip ram. clear fwe * fwe = high * branch to flash memory application program branch to program/erase control program in ram area execute program/erase control program (flash memory rewriting) transfer program/erase control program to ram md2, md1, md0 = 110, 111 reset-start write the fwe assessment program and transfer program (and the program/erase control program if necessary) beforehand notes: do not apply a constant high level to the fwe pin. apply a high level to the fwe pin only when the flash memory is programmed or erased. also, while a high level is applied to the fwe pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * for further information on fwe application and disconnection, see section 22.13, flash memory programming and erasing precautions. figure 22.11 user program mode execution procedure
section 22 rom rev. 3.00 jan 11, 2005 page 858 of 1220 rej09b0186-0300o 22.7 programming/erasing flash memory a software method, using the cpu, is employed to program and erase flash memory in the on- board programming modes. there are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. transitions to these modes are made by setting the psu1, esu1, p1, e1, pv1, and ev1 bits in flmcr1 for addresses h'000000 to h'03ffff. the flash memory cannot be read while it is being written or erased. the flash memory cannot be read while being programmed or erased. therefore, the program (user program) that controls flash memory programming/erasing s hould be located and executed in on-chip ram or external memory. if the program is to be located in external memory, the instruction for writing to flash memory, and the following instruction, should be placed in on-chip ram. also ensure that the dtc and dmac is not activated before or after execution of the flash memory write instruction. in the following operation descriptions, wait times after setting or clearing individual bits in flmcr1 are given as parameters; for details of the wait times, see section 25.6, flash memory characteristics. notes: 1. operation is not guaranteed if bits swe1, esu1, psu1, ev1, pv1, e1, and p1 of flmcr1 are set/reset by a program in flash memory in the corresponding address areas. 2. when programming or erasing, set fwe to 1 (programming/erasing will not be executed if fwe = 0). 3. programming s hould be performed in the erased state. do not perform additional programming on previously programmed addresses.
section 22 rom rev. 3.00 jan 11, 2005 page 859 of 1220 rej09b0186-0300o normal mode on-board programming mode software programming disable state erase setup state erase mode program mode erase-verify mode program setup state program-verify mode swe1 = 1 swe1 = 0 fwe = 1 fwe = 0 e1 = 1 e1 = 0 p1 = 1 p1 = 0 software programming enable state * 1 * 2 * 3 * 4 notes: in order to perform a normal read of flash memory, swe must be cleared to 0. also note that verify-reads can be performed during the programming/erasing process. 1. : normal mode : on-board programming mode 2. do not make a state transition by setting or clearing multiple bits simultaneously. 3. after a transition from erase mode to the erase setup state, do not enter erase mode without passing through the software programming enable state. 4. after a transition from program mode to the program setup state, do not enter program mode without passing through the software programming enable state. esu1 = 0 esu1 = 1 psu1 = 1 psu1 = 0 pv1 = 1 pv1 = 0 ev1 = 0 ev1 = 1 figure 22.12 flmcr1 bit settings and state transitions 22.7.1 program mode when writing data or programs to flash memory, the program/program-verify flowchart shown in figure 22.13 should be followed. performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. programming s hould be carried out 128 bytes at a time.
section 22 rom rev. 3.00 jan 11, 2005 page 860 of 1220 rej09b0186-0300o the wait times after bits are set or cleared in the flash memory control register 1 (flmcr1) and the maximum number of programming operations (n1 + n2) are shown in table 25.13 in section 25.6, flash memory characteristics. following the elapse of (x0) s or more after the swe1 bit is set to 1 in flmcr1, 128-byte program data is stored in the program data area and reprogram data area, and the 128-byte data in the program data area in ram is written consecutively to the program address (the lower 8 bits of the first address written to must be h'00 or h'80). 128 consecutive byte data transfers are performed. the program address and program data are latched in the flash memory. a 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to the extra addresses. next, the watchdog timer is set to prevent overprogra mming in the event of program runaway, etc. set a value greater than (y + z2 + + ) ms as the wdt overflow period. after this, preparation for program mode (program setup) is carried out by setting the psu1 bit in flmcr1, and after the elapse of (y) s or more, the operating mode is switched to program mode by setting the p1 bit in flmcr1. the time during which the p1 bit is set is the flash memory programming time. refer to the table in figure 22.13 for the programming time. 22.7.2 program-verify mode in program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. after the elapse of the given programming time, clear the p1 bit in flmcr1, then wait for at least ( ) s before clearing the psu1 bit to exit program mode. after the elapse of at least ( ) s, the watchdog timer is cleared and the operating mode is switched to program-verify mode by setting the pv1 bit in flmcr1. before reading in program-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of ( ) s or more. when the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. wait at least ( ) s after the dummy write before performing this read operation. next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 22.13) and transferred to ram. after verification of 128 bytes of data has been completed, exit program-verify mode, wait for at least ( ) s, then clear the swe1 bit in flmcr1. if reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. the maximum number of repetitions of the program/program-verify sequence is indicated by the maximum programming c ount (n1 + n2). however, ensure that the program/program-verify sequence is not repeated more than (n1 + n2) times on the same bits.
section 22 rom rev. 3.00 jan 11, 2005 page 861 of 1220 rej09b0186-0300o notes on program/program-verify procedure (1) in order to perform 128-byte-unit programming, the lower 8 bits of the write start address must be h'00 or h'80. (2) when performing continuous writing of 128-byte data to flash memory, byte-unit transfer should be used. 128-byte data transfer is necessary even when writing fewer than 128 bytes of data. write h'ff data to the extra addresses. (3) verify data is read in word units. (4) the write pulse is applied and a flash memory write executed while the p1 bit in flmcr1 is set. in the h8s/2643, write pulses should be applied as follows in the program/program-verify procedure to prevent voltage stress on the device and loss of write data reliability. a. after write pulse application, perform a verify-read in program-verify mode and apply a write pulse again for any bits read as 1 (reprogramming processing). when all the 0-write bits in the 128-byte write data are read as 0 in the verify-read operation, the program/program-verify procedure is completed. in the h8s/2643, the number of loops in reprogramming processing is guaranteed not to exceed the maximum value of the maximum programming c ount (n). b. after write pulse application, a verify-read is performed in program-verify mode, and programming is judged to have been completed for bits read as 0. c. if programming of other bits is incomplete in the 128 bytes, reprogramming processing should be executed. if a bit for which progra mming has been judged to be completed is read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit. (5) the period for which the p1 bit in flmcr1 is set (the write pulse width) should be changed according to the degree of progress through the program/program-verify procedure. for detailed wait time specifications, see section 25.6, flash memory characteristics. (6) the program/program-verify flowchart for the h8s/2643 is shown in figure 22.13. to cover the points noted above, bits on which reprogramming processing is to be executed, and bits on which additional programming is to be executed, must be determined as shown below. since reprogram data and additional-programming data vary according to the progress of the programming procedure, it is recommended that the following data storage areas (128 bytes each) be provided in ram.
section 22 rom rev. 3.00 jan 11, 2005 page 862 of 1220 rej09b0186-0300o reprogram data computation table (d) result of verify-read after write pulse application (v) (x) result of operation comments 00 1 programming completed: reprogramming processing not to be executed 0 1 0 programming incomplete: reprogramming processing to be executed 10 1 ? 1 1 1 still in erased state: no action legend: (d): source data of bits on which programming is executed (x): source data of bits on which reprogramming is executed additional-programming data computation table (x') result of verify-read after write pulse application (v) (y) result of operation comments 0 0 0 programming by write pulse application judged to be completed: additional programming processing to be executed 0 1 1 programming by write pulse application incomplete: additional programming processing not to be executed 1 0 1 programming already completed: additional programming processing not to be executed 1 1 1 still in erased state: no action legend: (y): data of bits on which additional programming is executed (x'): data of bits on which reprogramming is executed in a certain reprogramming loop (7) it is necessary to execute additional programming processing during the course of the h8s/2643 program/program-verify procedure. however, once 128-byte-unit progra mming is finished, additional programming s hould not be carried out on the same address area. when executing reprogramming, an erase must be executed first. note that normal operation of reads, etc., is not guaranteed if additional programming is performed on addresses for which a program/program-verify operation has finished.
section 22 rom rev. 3.00 jan 11, 2005 page 863 of 1220 rej09b0186-0300o start end of programming set swe1 bit in flmcr1 wait ( 0) s tcpv: tcswe: n = 1 m = 0 sub-routine-call set pv1 bit in flmcr1 wait ( ) s wait ( ) s read verify data ng ng ng ng ng ok ok ok ok * 4 * 2 * 4 * 3 wait ( ) s additional-programming data computation reprogram data computation transfer additional-programming data to additional-programming data area * 4 transfer reprogram data to reprogram data area program data = verify data? clear pv1 bit in flmcr1 clear swe1 bit in flmcr1 m = 1 128-byte data verification completed? wait ( 1) s m = 0 ? n1 n? ng n1 n? increment address programming failure ok clear swe1 bit in flmcr1 wait ( 1) s n (n1 + n2) ? n n + 1 notes: 1. data transfer is performed by byte transfer. the lower 8 bits of the first address written to must be h'00 or h'80. a 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to the extra addresses. 2. verify data is read in 16-bit (word) units. 3. even bits for which programming has been completed in the 128-byte programming loop will be subject to programming again if they fail the subsequent verify operation. 4. a 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additi onal-programming data must be provided in ram. the reprogram and additional-programming data contents are modified as programming proceeds. 5. a write pulse of 30 s or 200 s is applied according to the progress of the programming operation. see note 6 for details of the pulse widths. when writing of additional-programming data is executed, a 10 s write pulse should be applied. reprogram data x' means repro gram data when the write pulse is applied. original data (d) 0 0 1 1 verify data (v) 0 1 0 1 reprogram data (x) 1 0 1 1 comments programming complete programming is incomplete: reprogramming should be performed left in the erased state write pulse application subroutine programming must be executed in the erased state. do not perform additional programming on addresses that have already been programmed. ram program data storage area (128 bytes) reprogram data storage area (128 bytes) additional-programming data storage area (128 bytes) store 128 bytes of program data in program data area and reprogram data area * 1 successively write 128-byte reprogram data to flash memory enable wdt disable wdt set psu1 bit in flmcr1 set p1 bit in flmcr1 clear psu1 bit in flmcr1 wait (y) s wait ( ) s wait ( ) s tsp10 or tsp30 or tsp200: wait (z0) s or (z1) s or (z2) s sub-routine-call additional programming subroutine * 1 successively write 128-byte data from additional- programming data area in ram to flash memory h'ff dummy write to verify address sub-routine write pulse end sub clear p1 bit in flmcr1 start of programming write pulse application subroutine number of writes 1 2 n1 ? 1 n1 n1 + 1 n1 + 2 n1 + 3 n1 + n2 ? 2 n1 + n2 ? 1 n1 + n2 programming z0 z0 z0 z0 z2 z2 z2 z2 z2 z2 z1 z1 z1 z1 ? ? ? ? ? ? additional programming note: 6. programming time reprogram data computation table reprogram data (x') 0 0 1 1 verify data (v) 0 1 0 1 additional-programming data (x) 0 1 1 1 comments additional programming should be performed additional programming should not be performed additional programming should not be performed additional programming should not be performed additional-programming data computation table p1 bit set time (s) figure 22.13 program/program-verify flowchart
section 22 rom rev. 3.00 jan 11, 2005 page 864 of 1220 rej09b0186-0300o 22.7.3 erase mode when erasing flash memory, the single-block erase/erase-verify flowchart shown in figure 22.14 should be followed. to erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in erase block register 1 and 2 (ebr1, ebr2) at least (x) s after setting the swe1 bit to 1 in flmcr1. next, the watchdog timer (wdt) is set to prevent overerasing due to program runaway, etc. set a value greater than (y + z + + ) ms as the wdt overflow period. preparation for entering erase mode (erase setup) is performed next by setting the esu1 bit in flmcr1. the operating mode is then switched to erase mode by setting the e1 bit in flmcr1 after the elapse of at least (y) s. the time during which the e1 bit is set is the flash memory erase time. ensure that the erase time does not exceed (z) ms. note: with flash memory erasing, preprogramming (setting all memory data in the memory to be erased to all 0) is not necessary before starting the erase procedure. 22.7.4 erase-verify mode in erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. after the elapse of the fixed erase time, clear the e1 bit in flmcr1, then wait for at least ( ) s before clearing the esu1 bit to exit erase mode. after exiting erase mode, the watchdog timer is cleared after the elapse of ( ) s or more. the operating mode is then switched to erase-verify mode by setting the ev1 bit in flmcr1. before reading in erase-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of ( ) s or more. when the flash memory is read in this state (verify data is read in 16- bit units), the data at the latched address is read. wait at least ( ) s after the dummy write before performing this read operation. if the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. if the read data is unerased, set erase mode again and repeat the erase/erase-verify sequence in the same way. the maximum number of reoperations of the erase/erase-verify sequence is indicated by the maximum erase count (n). however, ensure that the erase/erase-verify sequence is not repeated more than (n) times. when verification is completed, exit erase-verify mode, and wait for at least ( ) s. if erasure has been completed on all the erase blocks, clear the swe1 bit in flmcr1. if there are any unerased blocks, make a 1 bit setting for the flash memory area to be erased, and repeat the erase/erase- verify sequence as before.
section 22 rom rev. 3.00 jan 11, 2005 page 865 of 1220 rej09b0186-0300o end of erasing start set swe1 bit in flmcr1 set esu1 bit in flmcr1 set e1 bit in flmcr1 wait (x) s wait (y) s n = 1 set ebr1 and 2 enable wdt * 3 wait (z) ms wait ( ) s wait ( ) s wait ( ) s set block start address to verify address wait ( ) s wait ( ) s * 2 * 4 start erase clear e1 bit in flmcr1 clear esu1 bit in flmcr1 set ev1 bit in flmcr1 h'ff dummy write to verify address read verify data clear ev1 bit in flmcr1 wait ( ) s clear ev1 bit in flmcr1 clear swe1 bit in flmcr1 disable wdt halt erase * 1 verify data = all "1"? last address of block? end of erasing of all erase blocks? erase failure clear swe1 bit in flmcr1 n (n)? ng ng ng ng ok ok ok ok n n + 1 increment address wait ( 1) s wait ( 1) s notes: 1. preprogramming (setting erase block data to all "0") is not necessary. 2. verify data is read in 16-bit (w) units. 3. set only one bit in ebr1 and 2. more than 2 bits cannot be set. 4. erasing is performed in block units. to erase a number of blocks, each block must be erased in turn. figure 22.14 erase/erase-verify flowchart
section 22 rom rev. 3.00 jan 11, 2005 page 866 of 1220 rej09b0186-0300o 22.8 protection there are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 22.8.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. hardware protection is reset by settings in flash memory control register 1 (flmcr1), flash memory control register 2 (flmcr2), erase block register 1 (ebr1), and erase block register 2 (ebr2). the flmcr1, flmcr2, ebr1, and ebr2 settings are retained in the error-protected state. (see table 22.11.) table 22.11 hardware protection functions item description program erase fwe pin protection ? when a low level is input to the fwe pin, flmcr1, flmcr2, (except bit fler) ebr1, and ebr2 are initialized, and the program/erase-protected state is entered. yes yes reset/standby protection ? in a power-on reset (including a wdt power- on reset) and in standby mode, flmcr1, flmcr2, ebr1, and ebr2 are initialized, and the program/erase-protected state is entered. ? in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristics section. yes yes
section 22 rom rev. 3.00 jan 11, 2005 page 867 of 1220 rej09b0186-0300o 22.8.2 software protection software protection can be implemented by setting the swe1 bit in flmcr1, erase block register 1 (ebr1), erase block register 2 (ebr2), and the rams bit in the ram emulation register (ramer). when software protection is in effect, setting the p1 or e1 bit in flash memory control register 1 (flmcr1), does not cause a transition to program mode or erase mode. (see table 22.12.) table 22.12 software protection functions item description program erase swe bit protection ? setting bit swe1 in flmcr1 to 0 will place area h'000000 to h'03ffff in the program/erase-protected state. (execute the program in the on-chip ram, external memory) yes yes block specification protection ? erase protection can be set for individual blocks by settings in erase block register 1 (ebr1) and erase block register 2 (ebr2). ? setting ebr1 and ebr2 to h'00 places all blocks in the erase-protected state. ? yes emulation protection ? setting the rams bit to 1 in the ram emulation register (ramer) places all blocks in the program/erase-protected state. yes yes
section 22 rom rev. 3.00 jan 11, 2005 page 868 of 1220 rej09b0186-0300o 22.8.3 error protection in error protection, an error is detected when h8s/2643 group runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. if the h8s/2643 group malfunctions during flash memory progra mming/erasing, the fler bit is set to 1 in flmcr2 and the error protection state is entered. the flmcr1, flmcr2, ebr1, and ebr2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. program mode or erase mode cannot be re-entered by re-setting the p1 or e1 bit. however, pv1 and ev1 bit setting is enabled, and a transition can be made to verify mode. fler bit setting conditions are as follows: (1) when the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) (2) immediately after exception handling (excluding a reset) during programming/erasing (3) when a sleep instruction (including software standby) is executed during programming/erasing (4) when the cpu releases the bus to the dtc error protection is released only by a power-on reset and in hardware standby mode.
section 22 rom rev. 3.00 jan 11, 2005 page 869 of 1220 rej09b0186-0300o figure 22.15 shows the flash memory state transition diagram. rd vf pr er fler = 0 error occurrence res = 0 or hstby = 0 res = 0 or hstby = 0 rd vf pr er fler = 0 program mode erase mode reset or standby (hardware protection) rd vf pr er fler = 1 rd vf pr er fler = 1 error protection mode error protection mode (software standby) software standby mode flmcr1, flmcr2, (except bit fler) ebr1, ebr2 initialization state flmcr1, flmcr2, ebr1, ebr2 initialization state software standby mode release rd: memory read possible vf: verify-read possible pr: programming possible er: erasing possible rd : memory read not possible vf : verify-read not possible pr : programming not possible er : erasing not possible legend: res = 0 or hstby = 0 error occurrence (software standby) figure 22.15 flash memory state transitions
section 22 rom rev. 3.00 jan 11, 2005 page 870 of 1220 rej09b0186-0300o 22.9 flash memory emulation in ram making a setting in the ram emulation register (ramer) enables part of ram to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in ram in real time. after the ramer setting has been made, accesses cannot be made from the flash memory area or the ram area overlapping flash memory. emulation can be performed in user mode and user program mode. figure 22.16 shows an example of emulation of real-time flash memory programming. start of emulation program end of emulation program tuning ok? yes no set ramer write tuning data to overlap ram execute application program clear ramer write to flash memory emulation block figure 22.16 flowchart for flash memory emulation in ram
section 22 rom rev. 3.00 jan 11, 2005 page 871 of 1220 rej09b0186-0300o h'00000 h'01000 h'02000 h'03000 h'04000 h'05000 h'06000 h'07000 h'08000 h'3ffff flash memory eb8 to eb11 eb0 eb1 eb2 eb3 eb4 eb5 eb6 eb7 h'ffd000 h'ffdfff h'ffefbf on-chip ram this area can be accessed from both the ram area and flash memory area figure 22.17 example of ram overlap operation example in which flash memory block area eb0 is overlapped (1) set bits rams, ram2 to ram0 in ramer to 1, 0, 0, 0, to overlap part of ram onto the area (eb0) for which real-time programming is required. (2) real-time programming is performed using the overlapping ram. (3) after the program data has been confirmed, the rams bit is cleared, releasing ram overlap. (4) the data written in the overlapping ram is written into the flash memory space (eb0). notes: 1. when the rams bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of ram2 to ram0 (emulation protection). in this state, setting the p1 or e1 bit in flash memory control register 1 (flmcr1), will not cause a transition to program mode or erase mode. when actually programming or erasing a flash memory area, the rams bit should be cleared to 0. 2. a ram area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in ram is being used. 3. block area eb0 contains the vector table. when performing ram emulation, the vector table is needed in the overlap ram.
section 22 rom rev. 3.00 jan 11, 2005 page 872 of 1220 rej09b0186-0300o 22.10 interrupt handling when programming/erasing flash memory all interrupts, including nmi interrupt is disabled when flash memory is being programmed or erased (when the p1 or e1 bit is set in flmcr1), and while the boot program is executing in boot mode* 1 , to give priority to the program or erase operation. there are three reasons for this: (1) interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. (2) in the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly* 2 , possibly resulting in mcu runaway. (3) if interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. for these reasons, in on-board programming mode alone there are conditions for disabling interrupt, as an exception to the general rule. however, this provision does not guarantee normal erasing and programming or mcu operati on. all requests, including nmi interrupt, must therefore be restricted inside and outside the mcu when programming or erasing flash memory. nmi interrupt is also disabled in the error-protection state while the p1 or e1 bit remains set in flmcr1. notes: 1. interrupt requests must be disabled inside and outside the mcu until the programming control program has completed programming. 2. the vector may not be read correctly in this case for the following two reasons: if flash memory is read while being programmed or erased (while the p1 or e1 bit is set in flmcr1), correct read data will not be obtained (undetermined values will be returned). if the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. 22.11 flash memory programmer mode programs and data can be written and erased in programmer mode as well as in the on-board programming modes. in programmer mode, flash memory read mode, auto-program mode, auto- erase mode, and status read mode are supported. in auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. in programmer mode, set the mode pins to programmer mode (see table 22.13) and input a 12 mhz input clock.
section 22 rom rev. 3.00 jan 11, 2005 page 873 of 1220 rej09b0186-0300o table 22.13 shows the pin settings for programmer mode. table 22.13 programmer mode pin settings pin names settings mode pins: md2, md1, md0 low level input to md2, md1, and md0. mode setting pins: pf0, p16, p14 high level input to pf0, low level input to p16 and p14 fwe pin high level input (in auto-program and auto-erase modes) res pin power-on reset circuit xtal, extal, pllvcc, pllcap, pllvss pins oscillator circuit 22.11.1 socket adapter and memory map memory read (verify), write, and flash memory initialize (erase all) are supported in the writer mode using a prom writer. in this case a general purpose prom writer is used with a custom socket adapter installed. table 22.14 lists suitable socket adapter models. the socket adapter used with the write mode of the lsi must be one of the models listed in table 22.14. table 22.14 socket adapter models product model package socket adapter model manufacturer hd64f2643fc 144-pin qfp me2643eshf1h minato electronics inc. (fp-144j) hf2643q144d4001 data-io japan inc. hd64f2643tf 144-pin tqfp (tfp-144) me2643esnhh minato electronics inc.
section 22 rom rev. 3.00 jan 11, 2005 page 874 of 1220 rej09b0186-0300o 22.11.2 programmer mode operation table 22.15 shows how the different operating modes are set when using programmer mode, and table 22.16 lists the commands used in programmer mode. details of each mode are given below. (1) memory read mode memory read mode supports byte reads. (2) auto-program mode auto-program mode supports progra mming of 128 bytes at a time. status po lling is used to confirm the end of auto-programming. (3) auto-erase mode auto-erase mode supports automatic erasing of the entire flash memory. status po lling is used to confirm the end of auto-programming. (4) status read mode status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the i/o6 signal. in status read mode, error information is output if an error occurs. table 22.15 settings for various operating modes in programmer mode pin names mode fwe ce oe we i/o7 to i/o0 a18 to a0 read h or l l l h data output ain output disable h or l l h h hi-z x command write h or l * 3 l h l data input ain * 2 chip disable * 1 h or lhxxhi-zx notes: 1. chip disable is not a standby state; internally, it is an operation state. 2. ain indicates that there is also address input in auto-program mode. 3. for command writes in auto-program and auto-erase modes, input a high level to the fwe pin.
section 22 rom rev. 3.00 jan 11, 2005 page 875 of 1220 rej09b0186-0300o table 22.16 programmer mode commands 1st cycle 2nd cycle command name number of cycles mode address data mode address data memory read mode 1 + n write x h'00 read ra dout auto-program mode 129 write x h'40 write wa din auto-erase mode 2 write x h'20 write x h'20 status read mode 2 write x h'71 write x h'71 notes: 1. in auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. in memory read mode, the number of cycles depends on the number of address write cycles (n). 22.11.3 memory read mode (1) after completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. when reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. (2) in memory read mode, command writes can be performed in the same way as in the command wait state. (3) once memory read mode has been entered, consecutive reads can be performed. (4) after powering on, memory read mode is entered. table 22.17 ac characteristics in transition to memory read mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25 c 5 c) item symbol min max unit command write cycle t nxtc 20 ? s ce hold time t ceh 0 ? ns ce setup time t ces 0 ? ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns we rise time t r ? 30 ns we fall time t f ? 30 ns
section 22 rom rev. 3.00 jan 11, 2005 page 876 of 1220 rej09b0186-0300o ce oe ce a18 to a0 oe we i/o7 to i/o0 note: data is latched on the risin g ed g e of we . t ceh t wep t f t r t ces t nxtc address stable t ds t dh command write memory read mode figure 22.18 timing waveforms for memory read after memory write table 22.18 ac characteristics in transition from memory read mode to another mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25 c 5 c) item symbol min max unit command write cycle t nxtc 20 ? s ce hold time t ceh 0 ? ns ce setup time t ces 0 ? ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns we rise time t r ? 30 ns we fall time t f ? 30 ns
section 22 rom rev. 3.00 jan 11, 2005 page 877 of 1220 rej09b0186-0300o ce a18 to a0 oe we i/o7 to i/o0 note: do not enable we and oe at the same time. t ceh t wep t f t r t ces t nxtc address stable t ds t dh other mode command write memory read mode figure 22.19 timing waveforms in transition from memory read mode to another mode table 22.19 ac characteristics in memory read mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25 c 5 c) item symbol min max unit access time t acc ? 20 s ce output delay time t ce ? 150 ns oe output delay time t oe ? 150 ns output disable delay time t df ? 100 ns data output hold time t oh 5 ? ns
section 22 rom rev. 3.00 jan 11, 2005 page 878 of 1220 rej09b0186-0300o ce a18 to a0 oe we i/o7 to i/o0 v il v il v ih t acc t acc t oh t oh address stable address stable figure 22.20 ce and oe enable state read timing waveforms ce a18 to a0 oe we i/o7 to i/o0 v ih t acc t ce t oe t oe t ce t acc t oh t df t df t oh address stable address stable figure 22.21 ce and oe clock system read timing waveforms 22.11.4 auto-program mode (1) in auto-program mode, 128 bytes are programmed simultaneously. this should be carried out by executing 128 consecutive byte transfers. (2) a 128-byte data transfer is necessary even when progra mming fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. (3) the lower 7 bits of the transfer address must be low. if a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. (4) memory address transfer is performed in the second cycle (figure 22.22). do not perform transfer after the third cycle. (5) do not perform a command write during a programming operation.
section 22 rom rev. 3.00 jan 11, 2005 page 879 of 1220 rej09b0186-0300o (6) perform one auto-program operation for a 128-byte block for each address. two or more additional programming operations cannot be performed on a previously programmed address block. (7) confirm normal end of auto-programming by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status polling uses the auto-program operation end decision pin). (8) status polling i/o6 and i/o7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe . table 22.20 ac characteristics in auto-program mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25 c 5 c) item symbol min max unit command write cycle t nxtc 20 ? s ce hold time t ceh 0 ? ns ce setup time t ces 0 ? ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns status polling start time t wsts 1 ? ms status polling access time t spa ? 150 ns address setup time t as 0 ? ns address hold time t ah 60 ? ns memory write time t write 1 3000 ms write setup time t pns 100 ? ns write end setup time t pnh 100 ? ns we rise time t r ? 30 ns we fall time t f ? 30 ns
section 22 rom rev. 3.00 jan 11, 2005 page 880 of 1220 rej09b0186-0300o ce a18 to a0 fwe oe we i/o7 i/o6 i/o5 to i/o0 t pns t wep t ds t dh t f t r t as t ah t wsts t write t spa t ces t ceh t nxtc t nxtc t pnh address stable h'40 h'00 data transfer 1 to 128 bytes write operation end decision signal write normal end decision signal figure 22.22 auto-program mode timing waveforms 22.11.5 auto-erase mode (1) auto-erase mode supports only entire memory erasing. (2) do not perform a command write during auto-erasing. (3) confirm normal end of auto-erasing by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status polling uses the auto-erase operation end decision pin). (4) status polling i/o6 and i/o7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe .
section 22 rom rev. 3.00 jan 11, 2005 page 881 of 1220 rej09b0186-0300o table 22.21 ac characteristics in auto-erase mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25 c 5 c) item symbol min max unit command write cycle t nxtc 20 ? s ce hold time t ceh 0 ? ns ce setup time t ces 0 ? ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns status polling start time t ests 1 ? ms status polling access time t spa ? 150 ns memory erase time t erase 100 40000 ms erase setup time t ens 100 ? ns erase end setup time t enh 100 ? ns we rise time t r ? 30 ns we fall time t f ? 30 ns ce a18 to a0 fwe oe we i/o7 i/o6 i/o5 to i/o0 t ens t wep t ds t dh t f t r t ests t erase t spa t ces t ceh t nxtc t nxtc t enh h'20 h'20 h'00 erase end decision signal erase normal end decision signal figure 22.23 auto-erase mode timing waveforms
section 22 rom rev. 3.00 jan 11, 2005 page 882 of 1220 rej09b0186-0300o 22.11.6 status read mode (1) status read mode is provided to identify the kind of abnormal end. use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. (2) the return code is retained until a command write other than a status read mode command write is executed. table 22.22 ac characteristics in status read mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25 c 5 c) item symbol min max unit read time after command write t nxtc 20 ? s ce hold time t ceh 0 ? ns ce setup time t ces 0 ? ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns oe output delay time t oe ? 150 ns disable delay time t df ? 100 ns ce output delay time t ce ? 150 ns we rise time t r ? 30 ns we fall time t f ? 30 ns ce a18 to a0 oe we i/o7 to i/o0 t wep t f t r t oe t df t ds t ds t dh t dh t ces t ceh t ce t ceh t nxtc t nxtc t nxtc t ces h'71 t wep t f t r h'71 note: i/o2 and i/o3 are undefined. figure 22.24 status read mode timing waveforms
section 22 rom rev. 3.00 jan 11, 2005 page 883 of 1220 rej09b0186-0300o table 22.23 status read mode return commands pin name i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 attribute normal end decision command error program- ming error erase error ?? program- ming or erase count exceeded effective address error initial value00000000 indications normal end: 0 abnormal end: 1 command error: 1 otherwise: 0 program- ming error: 1 otherwise: 0 erasing error: 1 otherwise: 0 ?? count exceeded: 1 otherwise: 0 effective address error: 1 otherwise: 0 note: i/o2 and i/o3 are undefined. 22.11.7 status polling (1) the i/o7 status polling flag indicates the operating status in auto-program/auto-erase mode. (2) the i/o6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase mode. table 22.24 status polling output truth table pin name during internal operation abnormal end ? normal end i/o7 0 1 0 1 i/o6 0 0 1 1 i/o0 to i/o5 0 0 0 0 22.11.8 programmer mode transition time commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. after the programmer mode setup time, a transition is made to memory read mode. table 22.25 stipulated transition times to command wait state item symbol min max unit standby release (oscillation stabilization time) t osc1 30 ? ms programmer mode setup time t bmv 10 ? ms v cc hold time t dwn 0 ? ms
section 22 rom rev. 3.00 jan 11, 2005 page 884 of 1220 rej09b0186-0300o t osc1 t bmv t dwn v cc res fwe memory read mode command wait state auto-program mode auto-erase mode command wait state normal/abnormal end decision note: when using other than the automatic write mode and automatic erase mode, drive the fwe input pin low. figure 22.25 oscillation stabilization time, boot program transfer time, and power-down sequence 22.11.9 notes on memory programming (1) when programming addresses which have previously been programmed, carry out auto- erasing before auto-programming. (2) when performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. notes: the flash memory is initially in the erased state when the device is shipped by renesas. for other chips for which the erasure history is unknown, it is recommended that auto- erasing be executed to check and supplement the initialization (erase) level. auto-programming s hould be performed once only on the same address block. additional programming cannot be performed on previously programmed address blocks.
section 22 rom rev. 3.00 jan 11, 2005 page 885 of 1220 rej09b0186-0300o 22.12 flash memory and power-down states in addition to its normal operating state, the flash memory has power-down states in which power consumption is reduced by halting part or all of the internal power supply circuitry. there are three flash memory operating states: (1) normal operating mode: the flash memory can be read and written to. (2) power-down mode: part of the power supply circuitry is halted, and the flash memory can be read when the h8s/2643 is operating on the subclock. (3) standby mode: all flash memory circuits are halted, and the flash memory cannot be read or written to. states (2) and (3) are flash memory power-down states. table 22.26 shows the correspondence between the operating states of the h8s/2643 and the flash memory. table 22.26 flash memory operating states lsi operating state flash memory operating state high-speed mode medium-speed mode sleep mode normal mode (read/write) subactive mode subsleep mode when pdwnd = 0: power-down mode (read-only) when pdwnd = 1: normal mode (read-only) watch mode software standby mode hardware standby mode standby mode 22.12.1 note on power-down states when the flash memory is in a power-down state, part or all of the internal power supply circuitry is halted. therefore, a power supply circuit stabilization period must be provided when returning to normal operation. when the flash memory returns to its normal operating state from a power- down state, bits sts2 to sts0 in sbycr must be set to provide a wait time of at least 20 s (power supply stabilization time), even if an oscillation stabilization period is not necessary.
section 22 rom rev. 3.00 jan 11, 2005 page 886 of 1220 rej09b0186-0300o 22.13 flash memory programming and erasing precautions precautions concerning the use of on-board programming mode, the ram emulation function, and programmer mode are summarized below. (1) use the specified voltages and timing for programming and erasing applied voltages in excess of the rating can permanently damage the device. use a prom programmer that supports the renesas microcomputer device type with 256-kbyte on-chip flash memory (fztat256v3a). do not select the hn27c4096 setting for the prom programmer, and only use the specified socket adapter. failure to observe these points may result in damage to the device. (2) powering on and off (see figures 22.26 to 22.28) do not apply a high level to the fwe pin until v cc has stabilized. also, drive the fwe pin low before turning off v cc . when applying or disconnecting v cc power, fix the fwe pin low and place the flash memory in the hardware protection state. the power-on and power-off timing requirements s hould also be satisfied in the event of a power failure and subsequent recovery. (3) fwe application/disconnection (see figures 22.26 to 22.28) fwe application should be carried out when mcu operation is in a stable condition. if mcu operation is not stable, fix the fwe pin low and set the protection state. the following points must be observed concerning fwe application and disconnection to prevent unintentional programming or erasing of flash memory: ? apply fwe when the v cc voltage has stabilized within its rated voltage range. ? apply fwe when oscillation has stabilized (after the elapse of the oscillation stabilization time). ? in boot mode, apply and disconnect fwe during a reset. ? in user program mode, fwe can be switched between high and low level regardless of the reset state. fwe input can also be switched during execution of a program in flash memory. ? do not apply fwe if program runaway has occurred. ? disconnect fwe only when the swe1, esu1, psu1, ev1, pv1, p1, and e1 bits in flmcr1 are cleared.
section 22 rom rev. 3.00 jan 11, 2005 page 887 of 1220 rej09b0186-0300o make sure that the swe1, esu1, psu1, ev1, pv1, p1, and e1 bits are not set by mistake when applying or disconnecting fwe. (4) do not apply a constant high level to the fwe pin apply a high level to the fwe pin only when programming or erasing flash memory. a system configuration in which a high level is constantly applied to the fwe pin should be avoided. also, while a high level is applied to the fwe pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. (5) use the recommended algorithm when programming and erasing flash memory the recommended algorithm enables programming and erasing to be carried out wit hout subjecting the device to voltage stress or sacrificing program data reliability. when setting the p1 or e1 bit in flmcr1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. (6) do not set or clear the swe1 bit during execution of a program in flash memory wait for at least 100 s after clearing the swe1 bit before executing a program or reading data in flash memory. when the swe1 bit is set, data in flash memory can be rewritten, but when swe1 = 1, flash memory can only be read in program-verify or erase-verify mode. access flash memory only for verify operations (verification during programming/erasing). also, do not clear the swe1 bit during programming, erasing, or verifying. similarly, when using the ram emulation function while a high level is being i nput to the fwe pin, the swe1 bit must be cleared before executing a program or reading data in flash memory. however, the ram area overlapping flash memory space can be read and written to regardless of whether the swe1 bit is set or cleared. (7) do not use interrupts while flash memory is being programmed or erased all interrupt requests, including nmi, should be disabled during fwe application to give priority to program/erase operations. (8) do not perform overwriting. erase the memory before reprogramming in on-board programming, perform only one programming operation on a 128-byte programming unit block. in programmer mode, too, perform only one progra mming operation on a 128-byte programming unit block. programming s hould be carried out with the entire progra mming unit block erased.
section 22 rom rev. 3.00 jan 11, 2005 page 888 of 1220 rej09b0186-0300o (9) before programming, check that the chip is correctly mounted in the prom programmer overcurrent damage to the device can result if the index marks on the prom programmer socket, socket adapter, and chip are not correctly aligned. (10) do not touch the socket adapter or chip during programming touching either of these can cause contact faults and write errors. period during which flash memory access is prohibited (x: wait time after setting swe1 bit) * 2 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) v cc fwe t osc1 min 0 s min 0 s t mds * 3 t mds * 3 md2 to md0 * 1 res swe1 bit swe1 set swe1 cleared programming/ erasing possible wait time: x wait time: 100 s notes: 1. except when switching modes, the level of the mode pins (md2 to md0) must be fixed until power-off by pulling the pins up or down. 2. see section 25.6, flash memory characteristics. 3. mode programming setup time t mds (min.) = 200 ns figure 22.26 power-on/off timing (boot mode)
section 22 rom rev. 3.00 jan 11, 2005 page 889 of 1220 rej09b0186-0300o swe1 set swe1 cleared v cc fwe t osc1 min 0 s md2 to md0 * 1 res swe1 bit programming/ erasing possible wait time: x wait time: 100 s t mds * 3 period during which flash memory access is prohibited (x: wait time after setting swe1 bit) * 2 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) notes: 1. except when switching modes, the level of the mode pins (md2 to md0) must be fixed until power-off by pulling the pins up or down. 2. see section 25.6, flash memory characteristics. 3. mode programming setup time t mds (min.) = 200 ns figure 22.27 power-on/off timing (user program mode)
section 22 rom rev. 3.00 jan 11, 2005 page 890 of 1220 rej09b0186-0300o period during which flash memory access is prohibited (x: wait time after setting swe1 bit) * 3 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) v cc fwe t osc1 min 0 s t mds t mds t mds * 2 t resw md2 to md0 res swe1 bit mode change * 1 mode change * 1 boot mode user mode user program mode swe1 set swe1 cleared programming/erasing possible wait time: x wait time: 100 s programming/erasing possible wait time: x wait time: 100 s programming/erasing possible wait time: x wait time: 100 s programming/erasing possible wait time: x wait time: 100 s user mode user program mode notes: 1. when entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of res input. the state of ports with multiplexed address functions and bus control output pins ( as , rd , wr ) will change during this switchover interval (the interval during which the res pin input is low), and therefore these pins should not be used as output signals during this time. 2. when making a transition from boot mode to another mode, a mode programming setup time t mds (min.) of 200 ns is necessary with respect to res clearance timing. 3. see section 25.6, flash memory characteristics. figure 22.28 mode transition timing (example: boot mode user mode ? ? ? ? user program mode)
section 22 rom rev. 3.00 jan 11, 2005 page 891 of 1220 rej09b0186-0300o 22.14 note on switching from f-ztat version to masked rom version the masked rom version does not have the internal registers for flash memory control that are provided in the f-ztat version. table 22.27 lists the registers that are present in the f-ztat version but not in the masked rom version. if a register listed in table 22.27 is read in the masked rom version, an undefined value will be returned. therefore, if application software developed on the f-ztat version is switched to a masked rom version product, it must be modified to ensure that the registers in table 22.27 have no effect. table 22.27 registers present in f-ztat version but absent in masked rom version register abbreviation address flash memory control register 1 flmcr1 h'ffa8 flash memory control register 2 flmcr2 h'ffa9 erase block register 1 ebr1 h'ffaa erase block register 2 ebr2 h'ffab ram emulation register ramer h'fedb
section 22 rom rev. 3.00 jan 11, 2005 page 892 of 1220 rej09b0186-0300o
section 23 clock pulse generator rev. 3.00 jan 11, 2005 page 893 of 1220 rej09b0186-0300o section 23 clock pulse generator 23.1 overview the h8s/2643 group has a built-in clock pulse generator (cpg) that generates the system clock ( ), the bus master clock, and internal clocks. the clock pulse generator consists of an oscillator, pll (phase-locked loop) circuit, clock selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock oscillator, and waveform shaping circuit. the frequency can be changed by means of the pll circuit in the cpg. frequency changes are performed by software by means of settings in the system clock control register (sckcr) and low-power control register (lpwrcr). 23.1.1 block diagram figure 23.1 shows a block diagram of the clock pulse generator. legend: lpwrcr: sckcr: low-power control register system clock control register extal xtal pll circuit ( 1, 2, 4) medium- speed clock divider system clock oscillator clock selection circuit sub wdt1 count clock system clock to pin internal clock to supporting modules bus master clock to cpu, dmac and dtc /2 to /32 sck2 to sck0 sckcr stc1, stc0 osc1 osc2 waveform shaping circuit subclock oscillator lpwrcr bus master clock selection circuit figure 23.1 block diagram of clock pulse generator
section 23 clock pulse generator rev. 3.00 jan 11, 2005 page 894 of 1220 rej09b0186-0300o 23.1.2 register configuration the clock pulse generator is controlled by sckcr and lpwrcr. table 23.1 shows the register configuration. table 23.1 clock pulse generator register name abbreviation r/w initial value address * system clock control register sckcr r/w h'00 h'fde6 low-power control register lpwrcr r/w h'00 h'fdec note: * lower 16 bits of the address. 23.2 register descriptions 23.2.1 system clock control register (sckcr) 7 pstop 0 r/w 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 stcs 0 r/w 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w bit initial value r/w : : : sckcr is an 8-bit readable/writable register that performs clock output control, selection of operation when the pll circuit frequency multiplication factor is changed, and medium-speed mode control. sckcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7? clock output disable (pstop): controls output. description bit 7 pstop high-speed mode, medium-speed mode, sub-active mode sleep mode, sub-sleep mode software standby mode, watch mode hardware standby mode 0 output (initial value) output fixed high high impedance 1 fixed high fixed high fixed high high impedance bits 6 and 4?reserved: these bits are always read as 0 and cannot be modified.
section 23 clock pulse generator rev. 3.00 jan 11, 2005 page 895 of 1220 rej09b0186-0300o bit 3?frequency multiplication factor switching mode select (stcs): selects the operation when the pll circuit frequency multiplication factor is changed. bit 3 stcs description 0 specified multiplication factor is valid after transition to software standby mode, watch mode, and subactive mode (initial value) 1 specified multiplication factor is valid immediately after stc bits are rewritten bits 2 to 0?system clock select 2 to 0 (sck2 to sck0): these bits select the bus master clock. bit 2 bit 1 bit 0 sck2 sck1 sck0 description 0 0 0 bus master is in high-speed mode (initial value) 1 medium-speed clock is /2 1 0 medium-speed clock is /4 1 medium-speed clock is /8 1 0 0 medium-speed clock is /16 1 medium-speed clock is /32 1?? 23.2.2 low-power control register (lpwrcr) 7 dton 0 r/w 6 lson 0 r/w 5 nesel 0 r/w 4 substp 0 r/w 3 rfcut 0 r/w 0 stc0 0 r/w 2 ? 0 r/w 1 stc1 0 r/w bit : initial value : r/w : lpwrcr is an 8-bit readable/writable register that performs power-down mode control. the following pertains to bits 1 and 0. for details of the other bits, see section 24.2.3, low-power control register (lpwrcr). lpwrcr is initialized to h'00 by a power-on reset and in hardware standby mode. it is not initialized in software standby mode.
section 23 clock pulse generator rev. 3.00 jan 11, 2005 page 896 of 1220 rej09b0186-0300o bits 1 and 0?frequency multiplication factor (stc1, stc0): the stc bits specify the frequency multiplication factor of the pll circuit. bit 1 bit 0 stc1 stc0 description 00 1 (initial value) 1 2 10 4 1 setting prohibited notes: a system clock frequency multiplied by the multiplication factor (stc1 and stc0) should not exceed the maximum operating frequency defined in section 25, electrical characteristics. current consumption and noise can be reduced by using this function?s pll 4 setting and lowering the external clock frequency. 23.3 oscillator clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 23.3.1 connecting a crystal resonator (1) circuit configuration a crystal resonator can be connected as shown in the example in figure 23.2. select the damping resistance r d according to table 23.2. an at-cut parallel-resonance crystal should be used. extal xtal r d c l2 c l1 c l1 = c l2 = 10 to 22 pf figure 23.2 connection of crystal resonator (example)
section 23 clock pulse generator rev. 3.00 jan 11, 2005 page 897 of 1220 rej09b0186-0300o table 23.2 damping resistance value frequency (mhz)24812162025 r d ( ? ) 1 k 500 200 0 0 0 0 (2) crystal resonator figure 23.3 shows the equivalent circuit of the crystal resonator. use a crystal resonator that has the characteristics shown in table 23.3. xtal c l at-cut parallel-resonance typ e extal c 0 lr s figure 23.3 crystal resonator equivalent circuit table 23.3 crystal resonator parameters frequency (mhz) 2 4 8 12 16 20 25 r s max ( ? ) 500 120 80 60 50 40 40 c 0 max (pf)7777777 (3) note on board design when a crystal resonator is connected, the following points should be noted: other signal lines should be routed away from the osc illator circuit to prevent i nduction from interfering with correct oscillati on. see figure 23.4. when designing the board, place the crystal resonator and its load capacitors as close as possible to the xtal and extal pins.
section 23 clock pulse generator rev. 3.00 jan 11, 2005 page 898 of 1220 rej09b0186-0300o c l2 signal a signal b c l1 h8s/2643 group xtal extal avoid figure 23.4 example of incorrect board design external circuitry such as that shown below is recommended around the pll. pllcap pllvcc pllvss vcc pvcc vss r1 c1 rp cpb * cb * cb * note: * cb and cpb are laminated ceramic capacitors. recommended values: r1 = 3 k ? rp = 200 ? c1 = 470 pf cb = cpb = 0.1 f figure 23.5 points for attention when using pll oscillation circuit place oscillation stabilization capacitor c1 and resistor r1 close to the pllcap pin, and ensure that no other signal lines cross this line. supply the c1 ground from pllvss. separate pllvcc and pllvss from the other vcc and vss lines at the board power supply source, and be sure to insert bypass capacitors cpb and cb close to the pins.
section 23 clock pulse generator rev. 3.00 jan 11, 2005 page 899 of 1220 rej09b0186-0300o 23.3.2 external clock input (1) circuit configuration an external clock signal can be input as shown in the examples in figure 23.6. if the xtal pin is left open, make sure that stray capacitance is no more than 10 pf. in example (b), make sure that the external clock is held high in standby mode. extal xtal external clock inpu t open (a) xtal pin left open extal xtal external clock inpu t (b) complementary clock input at xtal pin figure 23.6 external clock input (examples)
section 23 clock pulse generator rev. 3.00 jan 11, 2005 page 900 of 1220 rej09b0186-0300o (2) external clock table 23.4 and figure 23.7 show the input conditions for the external clock. table 23.4 external clock input conditions v cc = 3.0 v to 3.6 v, pv cc = 3.0 v to 5.5 v v cc = 3.0 v to 3.6 v pv cc = 5.0 v 10% item symbol min. max. min. max. unit test conditions external clock input low pulse width t exl 20 ? 15 ? ns figure 23.7 external clock input high pulse width t exh 20 ? 15 ? ns external clock rise time t exr ? 10 ? 5ns external clock fall time t exf ? 10 ? 5ns clock low pulse width level t cl 0.4 0.6 0.4 0.6 t cyc 5 mhz figure 25.2 80 ? 80 ? ns < 5 mhz clock high pulse width level t ch 0.4 0.6 0.4 0.6 t cyc 5 mhz 80 ? 80 ? ns < 5 mhz t exh t exl t exr t exf v cc 0.5 extal figure 23.7 external clock input timing
section 23 clock pulse generator rev. 3.00 jan 11, 2005 page 901 of 1220 rej09b0186-0300o 23.4 pll circuit the pll circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 1, 2, or 4. the multiplication factor is set with the stc bits in lpwrcr. the phase of the rising edge of the internal clock is controlled so as to match that at the extal pin. when setting the multiplication factor, ensure that the clock frequency after multiplication does not exceed the maximum operating frequency of the chip. when the multiplication factor of the pll circuit is changed, the operation varies according to the setting of the stcs bit in sckcr. when stcs = 0 (initial value), the setting becomes valid after a transition to software standby mode, watch mode, or subactive mode. the transition time count is performed in accordance with the setting of bits sts2 to sts0 in sbycr. [1] the initial pll circuit multiplication factor is 1. [2] a value is set in bits sts2 to sts0 to give the specified transition time. [3] the target value is set in stc1 and stc0, and a transition is made to software standby mode, watch mode, or subactive mode. [4] the clock pulse generator stops and the value set in stc1 and stc0 becomes valid. [5] software standby mode, watch mode, or subactive mode is cleared, and a transition time is secured in accordance with the setting in sts2 to sts0. [6] after the set transition time has elapsed, the lsi resumes operation using the target multiplication factor. if a pc break is set for the sleep instruction that causes a transition to software standby mode in [3], software standby mode is entered and break exception handling is executed after the oscillation stabilization time. in this case, the instruction following the sleep instruction is executed after execution of the rte instruction. when stcs = 1, the lsi operates on the changed multiplication factor immediately after bits stc1 and stc0 are rewritten.
section 23 clock pulse generator rev. 3.00 jan 11, 2005 page 902 of 1220 rej09b0186-0300o 23.5 medium-speed clock divider the medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32. 23.6 bus master clock selection circuit the bus master clock selection circuit selects the system clock ( ) or one of the medium-speed clocks ( /2, /4, /8, /16, and /32) to be supplied to the bus master, according to the settings of the sck2 to sck0 bits in sckcr. 23.7 subclock oscillator (1) connecting 32.768 khz quartz oscillator to supply a clock to the subclock osc illator, connect a 32. 768 khz quartz osc illator, as shown in figure 23.8. see (3), note on board design in section 23.3.1, connecting a crystal resonator, for points to be noted when connecting a crystal oscillator. osc1 osc2 c 1 c 2 c 1 = c 2 = 15 pf (typ.) figure 23.8 example connection of 32.768 khz crystal oscillator
section 23 clock pulse generator rev. 3.00 jan 11, 2005 page 903 of 1220 rej09b0186-0300o figure 23.9 shows the equivalence circuit for a 32.768 khz osc illator. osc1 osc2 c s l s r s c o c o = 1.5 pf (typ.) r s = 14 k ? (typ.) f w = 32.768 khz figure 23.9 equivalence circuit for 32.768 khz oscillator (2) handling pins when subclock not required if no subclock is required, connect the osc1 pin to vcc and leave osc2 open, as shown in figure 23.10. osc1 osc2 vcc open figure 23.10 pin handling when subclock not required 23.8 subclock waveform shaping circuit to eliminate noise from the subclock input to osc1, the subclock is sampled using the dividing clock . the sampling frequency is set using the nesel bit of lpwrcr. for details, see section 24.2.3, low power control register (lpwrcr). no sampling is performed in sub-active mode, sub-sleep mode, or watch mode.
section 23 clock pulse generator rev. 3.00 jan 11, 2005 page 904 of 1220 rej09b0186-0300o 23.9 note on crystal resonator since various characteristics related to the crystal resonator are closely linked to the user ? s board design, thorough evaluation is necessary on the user ? s part, for both the mask versions and f-ztat versions, using the resonator connection examples shown in this section as a guide. as the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. the design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin.
section 24 power-down modes rev. 3.00 jan 11, 2005 page 905 of 1220 rej09b0186-0300o section 24 power-down modes 24.1 overview in addition to the normal program execution state, the h8s/2643 group has eight power-down modes in which operation of the cpu and oscillator is halted and power dissipation is reduced. low-power operation can be achieved by individually controlling the cpu, on-chip supporting modules, and so on. the h8s/2643 group operating modes are as follows: (1) high-speed mode (2) medium-speed mode (3) subactive mode (4) sleep mode (5) subsleep mode (6) watch mode (7) module stop mode (8) software standby mode (9) hardware standby mode (2) to (9) are power down modes. sleep mode and sub-sleep mode are cpu mode, medium-speed mode is a cpu and bus master mode, sub-active mode is a cpu and bus master and on-chip supporting module mode, and module stop mode is an on-chip supporting module mode (including bus masters other than the cpu) state. some of these modes can be combined. after a reset, the lsi is in high-speed mode, with modules other than the dmac and dtc in module stop mode. table 24.1 shows the internal states of the lsi in the respective modes. table 24.2 shows the conditions for shifting between the power-down modes. figure 24.1 is a mode transition diagram.
section 24 power-down modes rev. 3.00 jan 11, 2005 page 906 of 1220 rej09b0186-0300o table 24.1 lsi internal states in each mode function high- speed medium- speed sleep module stop watch sub- active subsleep software standby hardware standby system clock pulse generator function- ing function- ing function- ing function- ing halted halted halted halted halted subclock pulse generator function- ing function- ing function- ing function- ing function- ing function- ing function- ing function- ing halted cpu instructions registers function- ing medium- speed operation halted (retained) high/ medium- speed operation halted (retained) subclock operation halted (retained) halted (retained) halted (undefined) external nmi halted i n t errup t s irq0 to irq7 function- ing function- ing function- ing function- ing function- ing function- ing function- ing function- ing peripheral functions wdt1 function- ing function- ing function- ing function- ing subclock operation subclock operation subclock operation halted (retained) halted (reset) wdt0 function- ing function- ing function- ing function- ing halted (retained) subclock operation subclock operation halted (retained) halted (reset) tmr halted (retained) dmac dtc function- ing medium- speed operation function- ing halted ( re t a i ne d) halted ( re t a i ne d) halted ( re t a i ne d) halted ( re t a i ne d) halted ( re t a i ne d) halted (reset) tpu iic0 function- ing function- ing function- ing halted ( re t a i ne d) halted ( re t a i ne d) halted ( re t a i ne d) halted ( re t a i ne d) halted ( re t a i ne d) halted (reset) iic1 pcb ppg d/a0, 1 sci0 sci1 function- ing function- ing function- ing halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) sci2 halted (reset) sci3 sci4 pwm0, 1 a/d ram function- ing function- ing function- ing (dtc) function- ing retained function- ing retained retained retained i/o function- ing function- ing function- ing function- ing retained function- ing * retained retained high impedance notes: ?halted (retained)? means that internal register values are retained. the internal state is ?operation suspended.? ?halted (reset)? means that internal register values and internal states are initialized. in module stop mode, only modules for which a stop setting has been made are halted (reset or retained).
section 24 power-down modes rev. 3.00 jan 11, 2005 page 907 of 1220 rej09b0186-0300o * with the exception of ports d and e, an i/o port always returns a value of 1 when read in the h8s/2643f-ztat. use as an output port is possible. program-halted state program execution state sck2 to sck0 = 0 sck2 to sck0 0 sleep command ssby = 1, pss = 1 dton = 1, lson = 1 clock switching exception processing sleep command ssby = 1, pss = 1 dton = 1, lson = 0 after the oscillation stabilization time (sts2 to 0), clock switching exception processing sleep command sleep command external interrupt * 3 any interrupt sleep command sleep command sleep command interrupt * 2 lson bit = 0 interrupt * 2 interrupt * 1 lson bit = 1 stby pin = high res pin = low stby pin = low ssby = 0, lson = 0 ssby = 1, pss = 0, lson = 0 ssby = 0, pss = 1, lson = 1 ssby = 1, pss = 1, dton = 0 res pin = high : transition after exception processing : low power dissipation mode reset state high-speed mode (main clock) medium-speed mode (main clock) sub-active mode (subclock) sub-sleep mode (subclock) hardware standby mode software standby mode sleep mode (main clock) watch mode (subclock) notes: when a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. ensure that interrupt handling is performed after accepting the interrupt request. from any state except hardware standby mode, a transition to the reset state occurs when res is driven low. from any state, a transition to hardware standby mode occurs when stby is driven low. always select high-speed mode before making a transition to watch mode or sub-active mode. 1. 2. 3. nmi, irq0 to irq7, and wdt1 interrupts nmi, irq0 to irq7, iwdt0 interrupts, wdt1 interrupt, and tmr0 to tmr3 interrupts nmi and irq0 to irq7 figure 24.1 mode transition diagram
section 24 power-down modes rev. 3.00 jan 11, 2005 page 908 of 1220 rej09b0186-0300o table 24.2 power-down mode transition conditions pre-transition status of control bit at transition state after transition invoked by sleep state after transition back from low power mode invoked by state ssby pss lson dton command interrupt 0 * 0 * sleep high-speed/medium-speed 0 * 1 * ?? 100 * software standby high-speed/medium-speed 101 * ?? 1 1 0 0 watch high-speed 1110watch sub-active 1101 ?? high-speed/ medium-speed 1111sub-active ? sub-active 0 0 ** ?? 010 * ?? 011 * sub-sleep sub-active 10 ** ?? 1 1 0 0 watch high-speed 1110watch sub-active 1 1 0 1 high-speed ? 1111 ?? legend: * :don ? t care ? : do not set
section 24 power-down modes rev. 3.00 jan 11, 2005 page 909 of 1220 rej09b0186-0300o 24.1.1 register configuration power-down modes are controlled by the sbycr, sckcr, lpwrcr, tcsr (wdt1), and mstpcr registers. table 24.3 summarizes these registers. table 24.3 power-down mode registers name abbreviation r/w initial value address * standby control register sbycr r/w h'08 h'fde4 system clock control register sckcr r/w h'00 h'fde6 low-power control register lpwrcr r/w h'00 h'fdec timer control/status register tcsr r/w h'00 h'ffa2 mstpcra r/w h'3f h'fde8 mstpcrb r/w h'ff h'fde9 module stop control register a to c mstpcrc r/w h'ff h'fdea note: * lower 16 bits of the address.
section 24 power-down modes rev. 3.00 jan 11, 2005 page 910 of 1220 rej09b0186-0300o 24.2 register descriptions 24.2.1 standby control register (sbycr) 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ope 1 r/w 0 ? 0 ? 2 ? 0 ? 1 ? 0 ? bit initial value r/w : : : sbycr is an 8-bit readable/writable register that performs power-down mode control. sbycr is initialized to h'08 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7?software standby (ssby): when making a low power dissipation mode transition by executing the sleep instruction, the operating mode is determined in combination with other control bits. note that the value of the ssby bit does not change even when shifting between modes using interrupts. bit 7 ssby description 0 shifts to sleep mode when the sl eep instruction is executed in high-speed mode or medium-speed mode. shifts to sub-sleep mode when the sl eep instruction is executed in sub-active mode. (initial value) 1 shifts to software standby mode, sub-active mode, and watch mode when the sleep instruction is executed in high-speed mode or medium-speed mode. shifts to watch mode or high-speed mode when the sl eep instruction is executed in sub-active mode.
section 24 power-down modes rev. 3.00 jan 11, 2005 page 911 of 1220 rej09b0186-0300o bits 6 to 4?standby timer select 2 to 0 (sts2 to sts0): these bits select the mcu wait time for clock stabilization when shifting to high-speed mode or medium-speed mode by using a specific interrupt or command to cancel software standby mode, watch mode, or sub-active mode. with a crystal oscillator (table 24.5), select a wait time of 8ms (osc illation stabilization time) or more, depending on the operating frequency. with an external clock, there are no specific wait requirements. bit 6 bit 5 bit 4 sts2 sts1 sts0 description 0 0 0 standby time = 8192 states (initial value) 1 standby time = 16384 states 1 0 standby time = 32768 states 1 standby time = 65536 states 1 0 0 standby time = 131072 states 1 standby time = 262144 states 10reserved 1 standby time = 16 states bit 3?output port enable (ope): this bit specifies whether the output of the address bus and bus control signals ( cs0 to cs7 , as , rd , hwr , lwr , cas , oe ) is retained or set to high- impedance state in the software standby mode, watch mode, and when making a direct transition. bit 3 ope description 0 in software standby mode, watch mode, and when making a direct transition, address bus and bus control signals are high-impedance. 1 in software standby mode, watch mode, and when making a direct transition, the output state of the address bus and bus control signals is retained. (initial value) bits 2 to 0?reserved: these bits are always read as 0 and cannot be modified.
section 24 power-down modes rev. 3.00 jan 11, 2005 page 912 of 1220 rej09b0186-0300o 24.2.2 system clock control register (sckcr) 7 pstop 0 r/w 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 stcs 0 r/w 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w bit initial value r/w : : : sckcr is an 8-bit readable/writable register that performs clock output control, selection of operation when the pll circuit frequency multiplication factor is changed, and medium-speed mode control. sckcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7? clock output disable (pstop): in combination with the ddr of the applicable port, this bit controls output. see section 24.12, clock output disabling function for details. description bit 7 pstop high-speed mode, medium-speed mode, sub-active mode sleep mode, sub-sleep mode software standby mode, watch mode hardware standby mode 0 output (initial value) output fixed high high impedance 1 fixed high fixed high fixed high high impedance bits 6 and 4?reserved: these bits are always read as 0 and cannot be modified. bit 3?frequency multiplication factor switching mode select (stcs): selects the operation when the pll circuit frequency multiplication factor is changed. bit 3 stcs description 0 specified multiplication factor is valid after transition to software standby mode, watch mode, or subactive mode (initial value) 1 specified multiplication factor is valid immediately after stc bits are rewritten
section 24 power-down modes rev. 3.00 jan 11, 2005 page 913 of 1220 rej09b0186-0300o bits 2 to 0?system clock select (sck2 to sck0): these bits select the bus master clock in high-speed mode, medium-speed mode, and sub-active mode. set sck2 to sck0 all to 0 when shifting to operation in watch mode or sub-active mode. bit 2 bit 1 bit 0 sck2 sck1 sck0 description 0 0 0 bus master in high-speed mode (initial value) 1 medium-speed clock is /2 1 0 medium-speed clock is /4 1 medium-speed clock is /8 1 0 0 medium-speed clock is /16 1 medium-speed clock is /32 1 ?? 24.2.3 low-power control register (lpwrcr) 7 dton 0 r/w 6 lson 0 r/w 5 nesel 0 r/w 4 substp 0 r/w 3 rfcut 0 r/w 0 stc0 0 r/w 2 ? 0 r/w 1 stc1 0 r/w bit initial value r/w : : : the lpwrcr is an 8-bit read/write register that controls the low power dissipation modes. the lpwrcr is initialized to h'00 at a power-on reset and when in hardware standby mode. it is not initialized at a manual reset or when in software standby mode. the following describes bits 7 to 2. for details of other bits, see section 23.2.2, low-power control register. bit 7?direct transition on flag (dton): when shifting to low power dissipation mode by executing the sleep instruction, this bit specifies whether or not to make a direct transition between high-speed mode or medium-speed mode and the sub-active modes. the selected operating mode after executing the sleep instruction is determined by the combination of other control bits.
section 24 power-down modes rev. 3.00 jan 11, 2005 page 914 of 1220 rej09b0186-0300o bit 7 dton description 0 ? when the sleep instruction is executed in high-s peed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode * . ? when the sleep instruction is executed in sub-active m ode, operation shifts to sub-sleep mode or watch mode. (initial value) 1 ? when the sleep instruction is executed in high-s peed mode or medium-speed mode, operation shifts directly to sub-active mode * , or shifts to sleep mode or software standby mode. ? when the sleep instruction is executed in sub-active m ode, operation shifts directly to high-speed mode, or shifts to sub-sleep mode. note: * always set high-speed mode when shifting to watch mode or sub-active mode. bit 6?low-speed on flag (lson): when shifting to low power dissipation mode by executing the sleep instruction, this bit specifies the operating mode, in combination with other control bits. this bit also controls whether to shift to high-speed mode or sub-active mode when watch mode is cancelled. bit 6 lson description 0 ? when the sleep instruction is executed in high-s peed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode * . ? when the sleep instruction is executed in sub-active m ode, operation shifts to watch mode or shifts directly to high-speed mode. ? operation shifts to high-speed mode when watch mode is cancelled. (initial value) 1 ? when the sleep instruction is executed in high-s peed mode, operation shifts to watch mode or sub-active mode. ? when the sleep instruction is executed in sub-active m ode, operation shifts to sub- sleep mode or watch mode. ? operation shifts to sub-active mode when watch mode is cancelled. note: * always set high-speed mode when shifting to watch mode or sub-active mode.
section 24 power-down modes rev. 3.00 jan 11, 2005 page 915 of 1220 rej09b0186-0300o bit 5?noise elimination sampling frequency select (nesel): this bit selects the sampling frequency of the subclock ( sub) generated by the subclock oscillator is sampled by the clock ( ) generated by the system clock oscillator. set this bit to 0 when = 5mhz or more. bit 5 nesel d escription 0 sampling using 1/32 (initial value) 1 sampling using 1/4 bit 4?subclock enable (substp): this bit enables/disables subclock generation. bit 4 substp description 0 enables subclock generation (initial value) 1 disables subclock generation bit 3?oscillation circuit feedback resistance control bit (rfcut): this bit turns the internal feedback resistance of the main clock oscillation circuit on/off. bit 3 rfcut description 0 when the main clock is oscillating, sets the feedback resistance on. when the main clock is stopped, sets the feedback resistance off. (initial value) 1 sets the feedback resistance off. bit 2?reserved: should always be written with 0.
section 24 power-down modes rev. 3.00 jan 11, 2005 page 916 of 1220 rej09b0186-0300o 24.2.4 timer control/status register (tcsr) wdt1 tcsr 7 ovf 0 r/ ( w ) * 6 wt/it 0 r/w 5 tme 0 r/w 4 pss 0 r/w 3 rst/nmi 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value r/w : : : note: * only write 0 to clear the flag. tcsr is an 8-bit read/write register that selects the clock input to wdt1 tcnt and the mode. the following describes bit 4. for details of the other bits in this register, see section 15.2.2, timer control/status register (tcsr). the tcsr is initialized to h'00 at a reset and when in hardware standby mode. it is not initialized in software standby mode. bit 4?prescaler select (pss): this bit selects the clock source input to wdt1 tcnt. it also controls operation when shifting low power dissipation modes. the operating mode selected after the sleep instruction is executed is determined in combination with other control bits. for details, see the description for clock selection in section 15.2.2, timer control/status register (tcsr), and this section. bit 4 pss description 0 ? tcnt counts the divided clock from the -based prescaler (psm). ? when the sleep instruction is executed in high-s peed mode or medium-speed mode, operation shifts to sleep mode or software standby mode. (initial value) 1 ? tcnt counts the divided clock from the sub-based prescaler (pss). ? when the sleep instruction is executed in high-s peed mode or medium-speed mode, operation shifts to sleep mode, watch mode * , or sub-active mode * . ? when the sleep instruction is executed in sub-active m ode, operation shifts to sub- sleep mode, watch mode, or high-speed mode. note: * always set high-speed mode when shifting to watch mode or sub-active mode.
section 24 power-down modes rev. 3.00 jan 11, 2005 page 917 of 1220 rej09b0186-0300o 24.2.5 module stop control register (mstpcr) mstpcra bit:76543210 mstpa7 mstpa6 mstpa5 mstpa4 mstpa3 mstpa2 mstpa1 mstpa0 initial value:00111111 r/w : r/w r/w r/w r/w r/w r/w r/w r/w mstpcrb bit:76543210 mstpb7 mstpb6 mstpb5 mstpb4 mstpb3 mstpb2 mstpb1 mstpb0 initial value:11111111 r/w : r/w r/w r/w r/w r/w r/w r/w r/w mstpcrc bit:76543210 mstpc7 mstpc6 mstpc5 mstpc4 mstpc3 mstpc2 mstpc1 mstpc0 initial value:11111111 r/w : r/w r/w r/w r/w r/w r/w r/w r/w mstpcr, comprising three 8-bit readable/writable registers, performs module stop mode control. mstpcr is initialized to h'3fffff by a reset and in hardware standby mode. it is not initialized in software standby mode. mstpcra/mstpcrb/mstpcrc bits 7 to 0?module stop (mstpa7 to mstpa0, mstpb7 to mstpb0, mstpc7 to mstpc0): these bits specify module stop mode. see table 24.3 for the method of selecting the on-chip peripheral functions. mstpcra/mstpcrb/ mstpcrc bits 7 to 0 mstpa7 to mstpa0, mstpb7 to mstpb0, mstpc7 to mstpc0 description 0 module stop mode is cleared (initial value of mstpa7 and mstpa6) 1 module stop mode is set (initial value of mstpa5 to 0, mstpb7 to 0, and mstpc7 to 0)
section 24 power-down modes rev. 3.00 jan 11, 2005 page 918 of 1220 rej09b0186-0300o 24.3 medium-speed mode in high-speed mode, when the sck2 to sck0 bits in sckcr are set to 1, the operating mode changes to medium-speed mode as soon as the current bus cycle ends. in medium-speed mode, the cpu operates on the operating clock ( /2, /4, /8, /16, or /32) specified by the sck2 to sck0 bits. the bus masters other than the cpu (the dmac and dtc) also operate in medium-speed mode. on-chip supporting modules other than the bus masters always operate on the high-speed clock ( ). in medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. for example, if /4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal i/o registers in 8 states. medium-speed mode is cleared by clearing all of bits sck2 to sck0 to 0. a transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. if a sleep instruction is executed when the ssby bit in sbycr is cleared to 0, and lson bit in lpwrcr is cleared to 0, a transition is made to sleep mode. when sleep mode is cleared by an interrupt, medium-speed mode is restored. when the sleep instruction is executed with the ssby bit = 1, lpwrcr lson bit = 0, and tcsr (wdt1) pss bit = 0, operation shifts to the software standby mode. when software standby mode is cleared by an external interrupt, medium-speed mode is restored. when the res and mres pins are set low and medium-speed mode is cancelled, operation shifts to the reset state. the same applies in the case of a reset caused by overflow of the watchdog timer. when the stby pin is driven low, a transition is made to hardware standby mode. figure 24.2 shows the t iming for transition to and clearance of medium-speed mode.
section 24 power-down modes rev. 3.00 jan 11, 2005 page 919 of 1220 rej09b0186-0300o , bus master clock supporting module clock internal address bus internal write signal medium-speed mode sbycr sbycr figure 24.2 medium-speed mode transition and clearance timing 24.4 sleep mode 24.4.1 sleep mode when the sleep instruction is executed when the sbycr ssby bit = 0 and the lpwrcr lson bit = 0, the cpu enters the sleep mode. in sleep mode, cpu operation stops but the contents of the cpus internal registers are retained. other supporting modules do not stop. 24.4.2 exiting sleep mode sleep mode is exited by any interrupt, or signals at the res , mres , or stby pins. (1) exiting sleep mode by interrupts when an interrupt occurs, sleep mode is exited and interrupt exception processing starts. sleep mode is not exited if the interrupt is disabled, or interrupts other than nmi are masked by the cpu. (2) exiting sleep mode by res or mres pins setting the res or mres pin level low selects the reset state. after the stipulated reset input duration, driving the res and mres pins high starts the cpu performing reset exception processing. (3) exiting sleep mode by stby pin when the stby pin level is driven low, a transition is made to hardware standby mode.
section 24 power-down modes rev. 3.00 jan 11, 2005 page 920 of 1220 rej09b0186-0300o 24.5 module stop mode 24.5.1 module stop mode module stop mode can be set for individual on-chip supporting modules. when the corresponding mstp bit in mstpcr is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. the cpu continues operating independently. table 24.4 shows mstp bits and the corresponding on-chip supporting modules. when the corresponding mstp bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. in module stop mode, the internal states of modules other than the sci, a/d converter and 14-bit pwm are retained. after reset clearance, all modules other than dmac and dtc are in module stop mode. when an on-chip supporting module is in module stop mode, read/write access to its registers is disabled.
section 24 power-down modes rev. 3.00 jan 11, 2005 page 921 of 1220 rej09b0186-0300o table 24.4 mstp bits and corresponding on-chip supporting modules register bit module mstpcra mstpa7 dma controller (dmac) mstpa6 data transfer controller (dtc) mstpa5 16-bit timer pulse unit (tpu) mstpa4 8-bit timer (tmr0, tmr1) mstpa3 programmable pulse generator (ppg) mstpa2 d/a converter (channels 0, 1) mstpa1 a/d converter mstpa0 8-bit timer (tmr2, tmr3) mstpcrb mstpb7 serial communication interface 0 (sci0) mstpb6 serial communication interface 1 (sci1) mstpb5 serial communication interface 2 (sci2) mstpb4 i 2 c bus interface 0 (iic0) mstpb3 i 2 c bus interface 1 (iic1) mstpb2 14-bit pwm timer (pwm0) mstpb1 14-bit pwm timer (pwm1) mstpb0 * ? mstpcrc mstpc7 serial communication interface 3 (sci3) mstpc6 serial communication interface 4 (sci4) mstpc5 d/a converter (channels 2, 3) mstpc4 pc break controller (pbc) mstpc3 * ? mstpc2 * ? mstpc1 * ? mstpc0 * ? note: * write 1 to bit mstpb0 and bits mtspc3 to mstpc0.
section 24 power-down modes rev. 3.00 jan 11, 2005 page 922 of 1220 rej09b0186-0300o 24.5.2 usage notes (1) dmac and dtc module stop depending on the operating status of the dmac and dtc, the mstpa7 and mstpa6 bits may not be set to 1. setting of the dmac or dtc module stop mode should be carried out only when the respective module is not activated. for details, refer to section 8, dma controller, and section 9, data transfer controller (dtc). (2) on-chip supporting module interrupt relevant interrupt operations cannot be performed in module stop mode. consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source or the dmac and dtc activation source. interrupts should therefore be disabled before entering module stop mode. (3) writing to mstpcr mstpcr should only be written to by the cpu. 24.6 software standby mode 24.6.1 software standby mode a transition is made to software standby mode when the sleep instruction is executed when the sbycr ssby bit = 1 and the lpwrcr lson bit = 0, and the tcsr (wdt1) pss bit = 0. in this mode, the cpu, on-chip supporting modules, and osc illator all stop. however, the contents of the cpu?s internal registers, ram data, and the states of on-chip supporting modules other than the sci, a/d converter, and 14-bit pwm, and i/o ports, are retained. whether the address bus and bus control signals are placed in the high-impedance state. in this mode the oscillator stops, and therefore power dissipation is significantly reduced. 24.6.2 exiting software standby mode software standby mode is cleared by an external interrupt (nmi pin, or pins irq0 to irq7 ), or by means of the res pin, mres pin or stby pin.
section 24 power-down modes rev. 3.00 jan 11, 2005 page 923 of 1220 rej09b0186-0300o (1) exiting software standby mode with an interrupt when an nmi or irq0 to irq7 interrupt request signal is input, clock osc illation starts, and after the elapse of the time set in bits sts2 to sts0 in sbycr, stable clocks are supplied to the entire chip, software standby mode is exited, and interrupt exception handling is started. when exiting software standby mode with an irq0 to irq7 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts irq0 to irq7 is generated. software standby mode cannot be exited if the interrupt has been masked on the cpu side or has been designated as a dtc activation source. (2) exiting software standby mode by res or mres pins when the res pin or mres pin is driven low, clock oscillation is started. at the same time as clock oscillation starts, clocks are s upplied to the entire chip. note that the res pin or mres pin must be held low until clock oscillation stabilizes. when the res pin or mres pin goes high, the cpu begins reset exception handling. (3) exiting software standby mode by stby pin when the stby pin is driven low, a transition is made to hardware standby mode. 24.6.3 setting oscillation stabilization time after clearing software standby mode bits sts2 to sts0 in sbycr should be set as described below. (1) using a crystal oscillator set bits sts2 to sts0 so that the standby time is at least 8 ms (the oscillation stabilization time). table 24.5 shows the standby times for different operating frequencies and settings of bits sts2 to sts0.
section 24 power-down modes rev. 3.00 jan 11, 2005 page 924 of 1220 rej09b0186-0300o table 24.5 oscillation stabilization time settings sts2 sts1 sts0 standby time 25 mhz 20 mhz 16 mhz 12 mhz 10 mhz 8 mhz 6 mhz 4 mhz 2 mhz unit 000 8192 states 0.32 0.41 0.51 0.65 0.8 1.0 1.3 2.0 4.1 ms 1 16384 states 0.65 0.82 1.0 1.3 1.6 2.0 2.7 4.1 8.2 1 0 32768 states 1.3 1.6 2.0 2.7 3.3 4.1 5.5 8.2 16.4 1 65536 states 2.6 3.3 4.1 5.5 6.6 8.2 10.9 16.4 32.8 1 0 0 131072 states 5.2 6.6 8.2 10.9 13.1 16.4 21.8 32.8 65.5 1 262144 states 10.4 13.1 16.4 21.8 26.2 32.8 43.6 65.6 131.2 1 0 reserved ????????? s 1 16 states * 0.6 0.8 1.0 1.3 1.6 2.0 1.7 4.0 8.0 : recommended time setting note: * do not use this setting in the version with built-in flash memory. (2) using an external clock the pll circuit requires a time for stabilization. insert a wait of 2 ms min. 24.6.4 software standby mode application example figure 24.3 shows an example in which a transition is made to software standby mode at the falling edge on the nmi pin, and software sta ndby mode is cleared at the rising edge on the nmi pin. in this example, an nmi interrupt is accepted with the nmieg bit in syscr cleared to 0 (falling edge specification), then the nmieg bit is set to 1 (rising edge specification), the ssby bit is set to 1, and a sleep instruction is executed, causing a transition to software standby mode. software standby mode is then cleared at the rising edge on the nmi pin.
section 24 power-down modes rev. 3.00 jan 11, 2005 page 925 of 1220 rej09b0186-0300o oscillator nmi nmieg ssby nmi exception handling nmieg = 1 ssby = 1 sleep instruction software standby mode (power-down mode) oscillation stabilization time t osc2 nmi exception handling figure 24.3 software standby mode application example
section 24 power-down modes rev. 3.00 jan 11, 2005 page 926 of 1220 rej09b0186-0300o 24.6.5 usage notes (1) i/o port status in software standby mode, i/o port states are retained. if the ope bit is set to 1, the address bus and bus control signal output is also retained. therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. (2) current dissipation during oscillation stabilization wait period current dissipation increases during the oscillation stabilization wait period. (3) write data buffer function the write data buffer function and software standby mode cannot be used at the same time. when the write data buffer function is used, the wdbe bit in bcrl should be cleared to 0 to cancel the write data buffer function before entering software standby mode. also check that external writes have finished, by reading external addresses, etc., before executing a sleep instruction to enter software standby mode. see section 7.9, write data buffer function, for details of the write data buffer function. 24.7 hardware standby mode 24.7.1 hardware standby mode when the stby pin is driven low, a transition is made to hardware standby mode from any mode. in hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. as long as the prescribed voltage is supplied, on-chip ram data is retained. i/o ports are set to the high-impedance state. in order to retain on-chip ram data, the rame bit in syscr should be cleared to 0 before driving the stby pin low. do not change the state of the mode pins (md2 to md0) while the h8s/2643 group is in hardware standby mode. hardware standby mode is cleared by means of the stby pin and the res pin. when the stby pin is driven high while the res pin is low, the reset state is set and clock oscillation is started. ensure that the res pin is held low until the clock oscillator stabilizes (at least 8 ms?the oscillation stabilization time?when using a crystal oscillator). when the res pin is subsequently
section 24 power-down modes rev. 3.00 jan 11, 2005 page 927 of 1220 rej09b0186-0300o driven high, a transition is made to the program execution state via the reset exception handling state. 24.7.2 hardware standby mode timing figure 24.4 shows an example of hardware standby mode t iming. when the stby pin is driven low after the res pin has been driven low, a transition is made to hardware standby mode. hardware standby mode is cleared by driving the stby pin high, waiting for the oscillation stabilization time, then changing the res pin from low to high. oscillator res stby oscillation stabilization time reset exception handling figure 24.4 hardware standby mode timing 24.8 watch mode 24.8.1 watch mode cpu operation makes a transition to watch mode when the sleep instruction is executed in high- speed mode or sub-active mode with sbycr ssby = 1, lpwrcr dton = 0, and tcsr (wdt1) pss = 1. in watch mode, the cpu is stopped and supporting modules other than wdt1 are also stopped. the contents of the cpu?s internal registers, the data in internal ram, and the statuses of the internal supporting modules (excluding the sci, adc, and 14-bit pwm) and i/o ports are retained.
section 24 power-down modes rev. 3.00 jan 11, 2005 page 928 of 1220 rej09b0186-0300o 24.8.2 exiting watch mode watch mode is exited by any interrupt (wovi1 interrupt, nmi pin, or irq0 to irq7 ), or signals at the res , mres , or stby pins. (1) exiting watch mode by interrupts when an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or medium-speed mode when the lpwrcr lson bit = 0 or to sub-active mode when the lson bit = 1. when a transition is made to high-speed mode, a stable clock is supplied to all lsi circuits and interrupt exception processing starts after the time set in sbycr sts2 to sts0 has elapsed. in the case of irq0 to irq7 interrupts, no transition is made from watch mode if the corresponding enable bit has been cleared to 0, and, in the case of interrupts from the internal supporting modules, the interrupt enable register has been set to disable the reception of that interrupt, or is masked by the cpu. see section 24.6.3, setting osc illation stabilization time after clearing software sta ndby mode for how to set the oscillation stabilization time when making a transition from watch mode to high-speed mode. (2) exiting watch mode by res or mres pins for exiting watch mode by the res or mres pins, see (2), exiting software standby mode by res or mres pins in section 24.6.2, exiting software standby mode. (3) exiting watch mode by stby pin when the stby pin level is driven low, a transition is made to hardware standby mode. 24.8.3 notes (1) i/o port status the status of the i/o ports is retained in watch mode. also, when the ope bit is set to 1, the address bus and bus control signals continue to be output. therefore, when a high level is output, the current consumption is not diminished by the amount of current to support the high level output. (2) current consumption when waiting for oscillation stabilization the current consumption increases during stabilization of oscillation.
section 24 power-down modes rev. 3.00 jan 11, 2005 page 929 of 1220 rej09b0186-0300o 24.9 sub-sleep mode 24.9.1 sub-sleep mode when the sleep instruction is executed with the sbycr ssby bit = 0, lpwrcr lson bit = 1, and tcsr (wdt1) pss bit = 1, cpu operation shifts to sub-sleep mode. in sub-sleep mode, the cpu is stopped. supporting modules other than tmr0 to tmr3, wdt0, and wdt1 are also stopped. the contents of the cpus internal registers, the data in internal ram, and the statuses of the internal supporting modules (excluding the sci, adc, and 14-bit pwm) and i/o ports are retained. 24.9.2 exiting sub-sleep mode sub-sleep mode is exited by an interrupt (interrupts from internal supporting modules, nmi pin, or irq0 to irq7 ), or signals at the res , mres , or stby pins. (1) exiting sub-sleep mode by interrupts when an interrupt occurs, sub-sleep mode is exited and interrupt exception processing starts. in the case of irq0 to irq7 interrupts, sub-sleep mode is not cancelled if the corresponding enable bit has been cleared to 0, and, in the case of interrupts from the internal supporting modules, the interrupt enable register has been set to disable the reception of that interrupt, or is masked by the cpu. (2) exiting sub-sleep mode by res or mres pins for exiting sub-sleep mode by the res or mres pins, see (2), exiting software standby mode by res or mres pins in section 24.6.2, exiting software standby mode. (3) exiting sub-sleep mode by stby pin when the stby pin level is driven low, a transition is made to hardware standby mode.
section 24 power-down modes rev. 3.00 jan 11, 2005 page 930 of 1220 rej09b0186-0300o 24.10 sub-active mode 24.10.1 sub-active mode when the sleep instruction is executed in high-speed mode with the sbycr ssby bit = 1, lpwrcr dton bit = 1, lson bit = 1, and tcsr (wdt1) pss bit = 1, cpu operation shifts to sub-active mode. when an interrupt occurs in watch mode, and if the lson bit of lpwrcr is 1, a transition is made to sub-active mode. and if an interrupt occurs in sub-sleep mode, a transition is made to sub-active mode. in sub-active mode, the cpu operates at low speed on the subclock, and the program is executed step by step. supporting modules other than tmr0 to tmr3, wdt0, and wdt1 are also stopped. when operating the cpu in sub-active mode, the sckcr sck2 to sck0 bits must be set to 0. 24.10.2 exiting sub-active mode sub-active mode is exited by the sleep instruction or the res , mres , or stby pins. (1) exiting sub-active mode by sleep instruction when the sleep instruction is executed with the sbycr ssby bit = 1, lpwrcr dton bit = 0, and tcsr (wdt1) pss bit = 1, the cpu exits sub-active mode and a transition is made to watch mode. when the sleep instruction is executed with the sbycr ssby bit = 0, lpwrcr lson bit = 1, and tcsr (wdt1) pss bit = 1, a transition is made to sub-sleep mode. finally, when the sleep instruction is executed with the sbycr ssby bit = 1, lpwrcr dton bit = 1, lson bit = 0, and tcsr (wdt1) pss bit = 1, a direct transition is made to high-speed mode (sck0 to sck2 all 0). see section 24.11, direct transitions for details of direct transitions. (2) exiting sub-active mode by res or mres pins for exiting sub-active mode by the res or mres pins, see (2), exiting software standby mode by res or mres pins in section 24.6.2, exiting software standby mode. (3) exiting sub-active mode by stby pin when the stby pin level is driven low, a transition is made to hardware standby mode.
section 24 power-down modes rev. 3.00 jan 11, 2005 page 931 of 1220 rej09b0186-0300o 24.11 direct transitions 24.11.1 overview of direct transitions there are three modes, high-speed, medium-speed, and sub-active, in which the cpu executes programs. when a direct transition is made, there is no interruption of program execution when shifting between high-speed and sub-active modes. direct transitions are enabled by setting the lpwrcr dton bit to 1, then executing the sleep instruction. after a transition, direct transition interrupt exception processing starts. (1) direct transitions from high-speed mode to sub-active mode execute the sleep instruction in high-speed mode when the sbycr ssby bit = 1, lpwrcr lson bit = 1, and dton bit = 1, and tscr (wdt1) pss bit = 1 to make a transition to sub- active mode. (2) direct transitions from sub-active mode to high-speed mode execute the sleep instruction in sub-active mode when the sbycr ssby bit = 1, lpwrcr lson bit = 0, and dton bit = 1, and tscr (wdt1) pss bit = 1 to make a direct transition to high-speed mode after the time set in sbycr sts2 to sts0 has elapsed. 24.12 clock output disabling function output of the clock can be controlled by means of the pstop bit in sckcr, and ddr for the corresponding port. when the pstop bit is set to 1, the clock stops at the end of the bus cycle, and output goes high. clock output is enabled when the pstop bit is cleared to 0. when ddr for the corresponding port is cleared to 0, clock output is disabled and input port mode is set. table 24.6 shows the state of the pin in each processing state. using the on-chip pll circuit to lower the oscillator frequency or prohibiting external clock output also have the effect of reducing unwanted electromagnetic interference*. therefore, consideration should be given to these options when deciding on system board settings. note: * electromagnetic interference: emi (electro magnetic interference)
section 24 power-down modes rev. 3.00 jan 11, 2005 page 932 of 1220 rej09b0186-0300o table 24.6 pin state in each processing state ddr 0 1 1 pstop ? 01 hardware standby mode high impedance high impedance high impedance software standby mode, watch mode, and direct transition high impedance fixed high fixed high sleep mode and subsleep mode high impedance output fixed high high-speed mode, medium-speed mode, and subactive mode high impedance output fixed high
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 933 of 1220 rej09b0186-0300o section 25 electrical characteristics 25.1 absolute maximum ratings table 25.1 lists the absolute maximum ratings. table 25.1 absolute maximum ratings item symbol value unit power supply voltage v cc pllv cc ?0.3 to +4.3 v pv cc ?0.3 to +7.0 v input voltage (xtal, extal, osc1, osc2) v in ?0.3 to v cc +0.3 v input voltage (ports 4 and 9) v in ?0.3 to av cc +0.3 v input voltage (except xtal, extal, osc1, osc2, ports 4 and 9) v in ?0.3 to pv cc +0.3 v reference voltage v ref ?0.3 to av cc +0.3 v analog power supply voltage av cc ?0.3 to +7.0 v analog input voltage v an ?0.3 to av cc +0.3 v operating temperature t opr regular specifications: ?20 to +75 c wide-range specifications: ?40 to +85 c storage temperature t stg ?55 to +125 c caution: permanent damage to the chip may result if absolute maximum rating are exceeded.
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 934 of 1220 rej09b0186-0300o 25.2 dc characteristics table 25.2 lists the dc characteristics. table 25.3 lists the permissible output currents. table 25.2 dc characteristics (1) conditions: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = av ss = pllv ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * 1 item symbol min. typ. max. unit test conditions irq7 to irq0 v t ? 1.0 ? ? v port 2 v t + ??pv cc 0.7 v schmitt trigger input voltage v t + ? v t ? 0.4 ? ? v input high voltage res , stby , nmi, fwe * 5 , md2 to md0 v ih pv cc ? 0.7 ?pv cc + 0.3 v extal, osc1 v cc 0.8 ? v cc + 0.3 v ports 1, 3, 5, 7, 8, a to g 2.2 ? pv cc + 0.3 v ports 4, 9 av cc 0.7 ?av cc + 0.3 v input low voltage res , stby , nmi, fwe * 5 , md2 to md0 v il ?0.3 ? 0.5 v extal, osc1 ?0.3 ? v cc 0.2 v ports 1, 3, 4, 5, 7, 8, 9, a to g ?0.3 ? 0.8 v output high voltage all output pins except p34 and p35 v oh pv cc ?0.5 ? ? v i oh = ?200 a p34, p35 pv cc ?2.5 i oh = ?100 a all output pins except p34 and p35 3.5 i oh = ?1 ma all output pins v ol ??0.4 vi ol = 1.6 ma output low voltage
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 935 of 1220 rej09b0186-0300o item symbol min. typ. max. unit test conditions res , fwe * 5 | i in |?? 1.0 a input leakage current stby , nmi, md2 to md0 ?? 1.0 a v in = 0.5 to pv cc ? 0.5 v ports 4, 9 ? ? 1.0 a v in = 0.5 to av cc ? 0.5 v three-state leakage current (off state) ports 1, 2, 3, 5, 7, 8, a to g ? i tsi ? ?? 1.0 a v in = 0.5 to pv cc ? 0.5 v mos input pull-up current ports a to e ?i p 50 ? 300 a v in = 0 v res c in ? ? 30 pf v in = 0 v input capacitance nmi ? ? 30 pf f = 1 mhz all input pins except res and nmi ? ? 15 pf t a = 25c current dissipation * 2 normal operation i cc * 4 ?72 v cc = 3.3 v 85 v cc = 3.6 v ma f = 25 mhz sleep mode ? 58 v cc = 3.3 v 75 v cc = 3.6 v ma f = 25 mhz all modules stopped ?50 ? ma f = 25 mhz, v cc = 3.3 v (reference values) medium- speed mode ( /32) ? 40 ? ma f = 25 mhz, v cc = 3.3 v (reference values) subactive mode ? 120 v cc = 3.0 v t a = 25 c 200 a using 32.768 khz crystal resonator subsleep mode ?70 v cc = 3.0 v t a = 25 c 150 a using 32.768 khz crystal resonator watch mode ? 20 v cc = 3.0 v t a = 25 c 50 a using 32.768 khz crystal resonator standby mode ? 1.0 5.0 a t a 50 c ? ? 20 50c < t a
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 936 of 1220 rej09b0186-0300o item symbol min. typ. max. unit test conditions operating pi cc ? 17 pv cc = 5.0 v 25 ma port power supply current * 2 subclock operation ?? 50 a standby ? 0.5 5.0 t a 50 c watch mode ? ? 20 50 c < t a analog power supply current during a/d and d/a conversion al cc ?0.6 2.0 maav cc = 5.0 v idle ? 0.01 t a = 25 c 5.0 a reference power supply current during a/d and d/a conversion al cc ?4.0 5.0 maav ref = 5.0 v idle ? 0.01 t a = 25 c 5.0 a ram standby voltage * 3 v ram 2.0 ? ? v notes: 1. if the a/d and d/a converters are not used, do not leave the av cc , v ref , and av ss pins open. apply a voltage between 4.5 v and 5.5 v to the av cc and v ref pins by connecting them to pv cc , for instance. set v ref av cc . 2. current dissipation values are for v ih = v cc (extal, osc1), av cc (ports 4 and 9), or pv cc (other), and v il = 0 v, with all output pins unloaded and the on-chip mos pull-up transistors in the off state. 3. the values are for v ram v cc < 3.0 v, v ih (min.) = v cc ? 0.1 v, and v il (max.) = 0.1 v. 4. i cc depends on v cc and f as follows: i cc (max.) = 1.0 (ma) + 0.93 (ma/(mhz v)) v cc f (normal operation) i cc (max.) = 1.0 (ma) + 0.77 (ma/(mhz v)) v cc f (sleep mode) 5. fwe is used only in the flash memory version.
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 937 of 1220 rej09b0186-0300o table 25.2 dc characteristics (2) conditions: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 3.0 v to 5.5 v, av cc = 3.6 v to 5.5 v * 7 , v ref = 3.6 v to av cc * 8 , v ss = av ss = pllv ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications)* 1 item symbol min. typ. max. unit test conditions irq7 to irq0 v t ? pv cc 0.2 ? ? v port 2 v t + ??pv cc 0.7 v schmitt trigger input voltage v t + ? v t ? pv cc 0.05 ? ? v input high voltage res , stby , fwe * 6 , nmi, md2 to md0 v ih pv cc 0.9 ? pv cc + 0.3 v extal, osc1 v cc 0.8 ? v cc + 0.3 v ports 1, 3, 5, 7, 8, a to g pv cc 0.8 ? pv cc + 0.3 v ports 4, 9 av cc 0.8 ? av cc + 0.3 v input low voltage res , stby , nmi, fwe * 6 , md2 to md0 v il ?0.3 ? pv cc 0.1 v extal, osc1 ?0.3 ? v cc 0.2 v ports 1, 3, 5, 7, 8, a to g ?0.3 ? pv cc 0.2 v ports 4 and 9 ?0.3 ? av cc 0.2 v output high voltage all output pins except p34 and p35 v oh pv cc ?0.5 ? ? v i oh = ?200 a p34, p35 pv cc ?2.5 ? ? i oh = ?100 a * 2 all output pins except p34 and p35 pv cc ?1.0 ? i oh = ?1ma output low all output pins v ol ??0.4vi ol = 1.6 ma voltage res , fwe * 6 | i in |? ?1.0 a input leakage current stby , nmi, md2 to md0 ??1.0a v in = 0.5 to pv cc ? 0.5 v ports 4, 9 ? ? 1.0 a v in = 0.5 to av cc ? 0.5 v
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 938 of 1220 rej09b0186-0300o item symbol min. typ. max. unit test conditions three-state leakage current (off state) ports 1, 2, 3, 5, 7, 8, a to g ? i tsi ? ?? 1.0 a v in = 0.5 to pv cc ? 0.5 v mos input pull-up current ports a to e ?i p 25 ? 300 a v in = 0 v res c in ? ? 30 pf v in = 0 v nmi ? ? 30 pf f = 1 mhz input capacitance all input pins except res and nmi ? ? 15 pf ta = 25c current dissipation * 3 normal operation i cc * 5 ?40 v cc = 3.3 v 60 v cc = 3.6 v ma f = 16 mhz sleep mode ? 35 v cc = 3.3 v 45 v cc = 3.6 v ma f = 16 mhz all modules stopped ? 30 ? ma f = 16 mhz, v cc = 3.3 v (reference values) medium- speed mode ( /32) ? 25 ? ma f = 16 mhz, v cc = 3.3 v (reference values) subactive mode ? 120 v cc = 3.0 v t a = 25 c 200 a using 32.768 khz crystal resonator subsleep mode ?70 v cc = 3.0 v t a = 25 c 150 a using 32.768 khz crystal resonator watch mode ? 20 v cc = 3.0 v t a = 25 c 50 a using 32.768 khz crystal resonator standby mode ? 1.0 5.0 a t a 50c ? ? 20 50c < t a
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 939 of 1220 rej09b0186-0300o item symbol min. typ. max. unit test conditions operating pi cc ? 10 pv cc = 5.0 v 16 ma port power supply current * 3 subclock operation ?? 50 a standby ? 0.5 5.0 t a 50 c watch mode ? ? 20 50 c < t a analog power supply current during a/d and d/a conversions al cc ?0.6 2.0 maav cc = 5.0 v idle ? 0.01 t a = 25 c 5.0 a reference current during a/d and d/a conversions al cc ?4.0 5.0 maav ref = 5.0 v idle ? 0.01 t a = 25 c 5.0 a ram standby voltage * 4 v ram 2.0 ? ? v notes: 1. if the a/d and d/a converters are not used, do not leave the av cc , v ref , and av ss pins open. apply a voltage between 3.3 v to 5.5 v to the av cc and v ref pins by connecting them to pv cc , for instance. set v ref av cc . 2. when using p34 and p35 as output pins, set pv cc = 4.5 v to 5.5 v. 3. current dissipation values are for v ih = v cc (extal, osc1), av cc (ports 4 and 9), or pv cc (other), and v il = 0 v, with all output pins unloaded and the on-chip mos pull-up transistors in the off state. 4. the values are for v ram v cc < 3.0 v, v ih (min.) = v cc ? 0.1 v, and v il (max.) = 0.1 v. 5. i cc depends on v cc and f as follows: i cc (max.) = 1.0 (ma) + 0.93 (ma/(mhz v)) v cc f (normal operation) i cc (max.) = 1.0 (ma) + 0.77 (ma/(mhz v)) v cc f (sleep mode) 6. fwe is used only in the flash memory version. 7. av cc = 3.3 v to 5.5 v if the a/d and d/a converters are not used (used as i/o ports). 8. v ref = 3.3 v to av cc if the a/d and d/a converters are not used (used as i/o ports).
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 940 of 1220 rej09b0186-0300o table 25.3 permissible output currents conditions: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 3.0 v to 5.5 v, av cc = 3.6 v to 5.5 v * 1 , v ref = 3.6 v to av cc * 2 , v ss = av ss = pllv ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) * 1 item symbol min. typ. max. unit permissible output low current (per pin) all output pins pv cc = 3.0 to 5.5 v i ol ??10ma permissible output low current (total) total of all output pins pv cc = 3.0 to 5.5 v i ol ? ? 120 ma permissible output high current (per pin) all output pins pv cc = 3.0 to 5.5 v ?i oh ??2.0ma permissible output high current (total) total of all output pins pv cc = 3.0 to 5.5 v ?i oh ??40ma notes: to protect chip reliability, do not exceed the output current values in table 25.3. 1. av cc = 3.3 v to 5.5 v if the a/d and d/a converters are not used (used as i/o ports). 2. v ref = 3.3 v to av cc if the a/d and d/a converters are not used (used as i/o ports).
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 941 of 1220 rej09b0186-0300o table 25.4 bus drive characteristics conditions : v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 3.0 v to 5.5 v, av cc = 3.3 v to 5.5 v, v ref = 3.3 v to av cc , v ss = av ss = pllv ss = 0 v, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) applicable pins: scl1 and 0, sda1 and 0 item symbol min. typ. max. unit test conditions v t - pv cc 0.3 ? ? v schmitt trigger input voltage v t + ??pv cc 0.7 v t + - v t - 0.4 ? ? pv cc = 4.5 v to 5.5 v 0.2 ? ? pv cc = 3.0 v to 4.5 v input high voltage v ih pv cc 0.7 ? pv cc + 0.5 v input low voltage v il - 0.5 ? pv cc 0.3 v output low voltage v ol ??0.7 i ol = 8 ma, pv cc = 4.5 v to 5.5 v ??0.4 i ol = 3 ma, pv cc = 4.5 v to 5.5 v ??0.4 i ol = 1.6 ma, pv cc = 3.0 v to 5.5 v input capacitance c in ? ? 20 pf v in = 0 v, f = 1 mhz, ta = 25 c three-state leakage current (off state) ? i tsi ? ??1.0 av in = 0.5 to v cc - 0.5 v scl, sda, output fall time t of 20 + 0.1 cb ? 250 ns
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 942 of 1220 rej09b0186-0300o 25.3 ac characteristics figure 25.1 shows the test conditions for the ac characteristics. 5 v r l r h c lsi output pin c = 50 pf: ports 10 to 13, 70 to 73, a to g (in case of expansion bus control signal output pin setting) c = 30 pf: all ports r l = 2.4 k ? r h = 12 k ? input/output timing measurement levels low level : 0.8 v hi g h level : 2.0 v figure 25.1 output load circuit
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 943 of 1220 rej09b0186-0300o 25.3.1 clock timing table 25.5 lists the clock t iming table 25.5 clock timing condition a: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 3.0 v to 5.5 v, av cc = 3.6 v to 5.5 v * 1 , v ref = 3.6 v to av cc * 2 , v ss = av ss = pllv ss = 0 v, = 32.768 khz, 2 to 16 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition b: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = av ss = pllv ss = 0 v, = 32.768 khz, 2 to 25 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition a condition b 16mhz 25mhz item symbol min. max. min. max. unit test conditions clock cycle time t cyc 62.5 500 40 500 ns figure 25.2 clock high pulse width t ch 18 ? 15 ? ns clock low pulse width t cl 18 ? 15 ? ns clock rise time t cr ? 12 ? 5ns clock fall time t cf ? 12 ? 5ns clock oscillator settling time at reset (crystal) t osc1 10 ? 10 ? ms figure 25.3 clock oscillator settling time in software standby (crystal) t osc2 8 ? 5 ? ms figure 24.3 external clock output stabilization delay time t dext 2 ? 2 ? ms figure 25.3 32 khz clock oscillation settling time t osc3 ? 2 ? 2s sub clock oscillator frequency f sub 32.768 32.768 khz sub clock ( sub ) cycle time t sub 30.5 30.5 s notes: 1. av cc = 3.3 v to 5.5 v if the a/d and d/a converters are not used (used as i/o ports). 2. v ref = 3.3 v to av cc if the a/d and d/a converters are not used (used as i/o ports).
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 944 of 1220 rej09b0186-0300o t ch t cf t cyc t cl t cr figure 25.2 system clock timing t osc1 t osc1 extal v cc stby res t dext t dext figure 25.3 oscillator settling timing
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 945 of 1220 rej09b0186-0300o 25.3.2 control signal timing table 25.6 lists the control signal t iming. table 25.6 control signal timing condition a: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 3.0 v to 5.5 v, av cc = 3.6 v to 5.5 v * 1 , v ref = 3.6 v to av cc * 2 , v ss = av ss = pllv ss = 0 v, = 32.768 khz, 2 to 16 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition b: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = av ss = pllv ss = 0 v, = 32.768 khz, 2 to 25 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition a condition b item symbol min. max. min. max. unit test conditions res setup time t ress 200 ? 200 ? ns figure 25.4 res pulse width t resw 20 ? 20 ? t cyc mres setup time t mress 250 ? 250 ? ns mres pulse width t mresw 20 ? 20 ? t cyc nmi setup time t nmis 250 ? 150 ? ns figure 25.5 nmi hold time t nmih 10 ? 10 ? nmi pulse width (exiting software standby mode) t nmiw 200 ? 200 ? ns irq setup time t irqs 250 ? 150 ? ns irq hold time t irqh 10 ? 10 ? ns irq pulse width (exiting software standby mode) t irqw 200 ? 200 ? ns notes: 1. av cc = 3.3 v to 5.5 v if the a/d and d/a converters are not used (used as i/o ports). 2. v ref = 3.3 v to av cc if the a/d and d/a converters are not used (used as i/o ports).
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 946 of 1220 rej09b0186-0300o t resw t ress t mress t mress t mresw t ress res mres figure 25.4 reset input timing t irqs irq edge input t irqh t nmis t nmih t irqs irq level input nmi irq t nmiw t irqw figure 25.5 interrupt input timing
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 947 of 1220 rej09b0186-0300o 25.3.3 bus timing table 25.7 lists the bus t iming. table 25.7 bus timing condition a: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 3.0 v to 5.5 v, av cc = 3.6 v to 5.5 v * 1 , v ref = 3.6 v to av cc * 2 , v ss = av ss = pllv ss = 0 v, = 2 to 16 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition b: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc * 2 , v ss = av ss = pllv ss = 0 v, = 2 to 25 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition a condition b item symbol min. max. min. max. unit test conditions address delay time t ad ? 30 ? 20 ns figure 25.6 to address setup time t as 0.5 t cyc ? 30 ? 0.5 t cyc ? 15 ? ns figure 25.11 address hold time t ah 0.5 t cyc ? 20 ? 0.5 t cyc ? 8 ? ns cs delay time 1 t csd1 ? 30 ? 20 ns cs delay time 2 t csd2 ? 30 ? 18 ns as delay time t asd ? 30 ? 18 ns rd delay time 1 t rsd1 ? 30 ? 18 ns rd delay time 2 t rsd2 ? 30 ? 18 ns read data setup time t rds 30 ? 15 ? ns read data hold time t rdh 0 ? 0 ? ns read data access time 1 t acc1 ? 1.0 t cyc ? 35 ? 1.0 t cyc ? 25 ns read data access time 2 t acc2 ? 1.5 t cyc ? 35 ? 1.5 t cyc ? 25 ns read data access time 3 t acc3 ? 2.0 t cyc ? 35 ? 2.0 t cyc ? 25 ns read data access time 4 t acc4 ? 2.5 t cyc ? 35 ? 2.5 t cyc ? 25 ns
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 948 of 1220 rej09b0186-0300o condition a condition b item symbol min. max. min. max. unit test conditions read data access time 5 t acc5 ? 3.0 t cyc ? 35 ? 3.0 t cyc ? 25 ns figure 25.6 to figure 25.11 wr delay time 1 t wrd1 ? 30 ? 18 ns wr delay time 2 t wrd2 ? 30 ? 18 ns wr pulse width 1 t wsw1 1.0 t cyc ? 30 ? 1.0 t cyc ? 15 ? ns wr pulse width 2 t wsw2 1.5 t cyc ? 30 ? 1.5 t cyc ? 15 ? ns write data delay time t wdd ? 30 ? 22 ns write data setup time t wds 0.5 t cyc ? 27 ? 0.5 t cyc ? 15 ? ns write data hold time t wdh 0.5 t cyc ? 20 ? 0.5 t cyc ? 8 ? ns wr setup time t wcs 0.5 t cyc ? 15 ? 0.5 t cyc ? 10 ? ns wr hold time t wch 0.5 t cyc ? 15 ? 0.5 t cyc ? 10 ? ns ras precharge time t pch 1.5 t cyc ? 30 ? 1.5 t cyc ? 15 ? ns figure 25.11 to figure 25.13 cas precharge time 1 t cp1 1.0 t cyc ? 20 ? 1.0 t cyc ? 8 ? ns cas precharge time 2 t cp2 0.5 t cyc ? 20 ? 0.5 t cyc ? 8 ? ns cas delay time 1 t casd1 ? 30 ? 20 ns cas delay time 2 t casd2 ? 30 ? 18 ns oe delay time 1 t oed1 ? 30 ? 18 ns oe delay time 2 t oed2 ? 30 ? 18 ns cas setup time t csr 0.5 t cyc ? 25 ? 0.5 t cyc ? 8 ? ns wait setup time t wts 40 ? 25 ? ns figure 25.8 wait hold time t wth 10 ? 5 ? ns breq setup time t brqs 60 ? 30 ? ns figure 25.14 back delay time t bacd ? 30 ? 15 ns bus-floating time t bzd ? 60 ? 40 ns breqo delay time t brqod ? 40 ? 25 ns figure 25.15 notes: 1. av cc = 3.3 v to 5.5 v if the a/d and d/a converters are not used (used as i/o ports). 2. v ref = 3.3 v to av cc if the a/d and d/a converters are not used (used as i/o ports).
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 949 of 1220 rej09b0186-0300o t rsd2 t 1 t ad as a23 to a0 t asd rd (read) cs7 to cs0 t 2 t as t asd t acc2 t rsd1 t acc3 t rds t rdh t wrd2 t wdd t wsw1 t wdh d15 to d0 (read) wr (write) d15 to d0 (write) t ah t wrd2 t csd1 t as t ah t as figure 25.6 basic bus timing (two-state access)
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 950 of 1220 rej09b0186-0300o t rsd2 t 2 as a23 to a0 t asd rd (read) t 3 t as t as t ah t asd t acc4 t rsd1 t acc5 t rds t rdh t wrd1 t wrd2 t wds t wsw2 t wdh t ah d15 to d0 (read) wr (write) d15 to d0 (write) t 1 t wdd t ad t csd1 cs7 to cs0 figure 25.7 basic bus timing (three-state access)
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 951 of 1220 rej09b0186-0300o t w as a23 to a0 rd (read) t 3 d15 to d0 (read) wr (write) d15 to d0 (write) cs7 to cs0 t 2 t wts t 1 t wth t wts t wth wait figure 25.8 basic bus timing (three-state access with one wait state)
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 952 of 1220 rej09b0186-0300o t rsd2 t 1 as a23 to a0 t 2 t ah t acc3 t rds d15 to d0 (read) t 2 or t 3 t as t 1 t asd t asd t rdh t ad cs7 to cs0 rd (read) figure 25.9 burst rom access timing (two-state access)
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 953 of 1220 rej09b0186-0300o t 1 as a23 to a0 t 1 t acc1 d15 to d0 (read) t 2 or t 3 t rdh t ad cs7 to cs0 rd (read) t rds t rsd2 figure 25.10 burst rom access timing (one-state access)
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 954 of 1220 rej09b0186-0300o t ad t c1 t c2 t r t p t ad t as t pch t csd t acc4 t csd2 t casd2 t acc2 t oed2 t acc3 t rds t rdh t wrd1 t wdd t wds t wdh t wcs t wch t wrd1 t oed1 t acc2 t casd1 t casd1 t acc1 t casd1 t cp1 t cp2 t ah a23 to a0 d15 to d0 (read) cs5 to cs2 (ras) hwr , lwr (write) cal , lcas (rcts=0) cal to lcas (when rcts is set to 1) (read) oe (when oes is set to 1) (read) d15 to d0 (write) figure 25.11 dram access timing
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 955 of 1220 rej09b0186-0300o t casd1 tr c1 tr c2 tr r tr p cs5 to cs2 (ras) cas , lcas t csd2 t csr t csd1 t casd1 figure 25.12 dram cbr refresh timing t casd1 tr c tr c tr r tr p cs5 to cs2 (ras) cas , lcas t csd2 t csr t csd2 t casd1 figure 25.13 dram self-refresh timing
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 956 of 1220 rej09b0186-0300o breq back a23 to a0 cs7 to cs0 , as , rd , hwr , l wr t bzd t bzd t bacd t bacd t brqs t brqs figure 25.14 external bus release timing breqo t brqod t brqod figure 25.15 external bus request output timing
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 957 of 1220 rej09b0186-0300o 25.3.4 dmac timing table 25.8 shows the dmac t iming. table 25.8 dmac timing condition a: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 3.0 v to 5.5 v, av cc = 3.6 v to 5.5 v * 1 , v ref = 3.6 v to av cc * 2 , v ss = av ss = pllv ss = 0 v, = 2 to 16 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition b: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = av ss = pllv ss = 0 v, = 2 to 25 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition a condition b item symbol min. max. min. max. unit test conditions dreq setup time t drqs 40 ? 25 ? ns figure 25.19 dreq hold time t drqh 10 ? 10 ? tend delay time t ted ? 30 ? 20 figure 25.18 dack delay time 1 t dacd1 ? 30 ? 18 ns figure 25.16 dack delay time 2 t dacd2 ? 30 ? 18 figure 25.17 notes: 1. av cc = 3.3 v to 5.5 v if the a/d and d/a converters are not used (used as i/o ports). 2. v ref = 3.3 v to av cc if the a/d and d/a converters are not used (used as i/o ports).
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 958 of 1220 rej09b0186-0300o a23 to a0 as cs7 to cs0 t 1 t 2 rd (read) d15 to d0 (read) d15 to d0 (write) hwr to lwr dack0, dack1 t dacd1 t dacd2 figure 25.16 dmac single address transfer timing/two-state access
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 959 of 1220 rej09b0186-0300o a23 to a0 as cs7 to cs0 t 1 t 2 rd (read) d15 to d0 (read) d15 to d0 (write) hwr to lwr dack0, dack1 t dacd1 t dacd2 t 2 figure 25.17 dmac single address transfer timing/three-state access tend0 , tend1 t 1 t 2 or t 3 t ted t ted figure 25.18 dmac tend output timing
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 960 of 1220 rej09b0186-0300o dreq0 , dreq1 t drqs t drqh figure 25.19 dmac dreq input timing
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 961 of 1220 rej09b0186-0300o 25.3.5 timing of on-chip supporting modules table 25.9 lists the t iming of on-chip supporting m odules. table 25.9 timing of on-chip supporting modules condition a: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 3.0 v to 5.5 v, av cc = 3.6 v to 5.5 v * 2 , v ref = 3.6 v to av cc * 3 , v ss = av ss = pllv ss = 0 v, = 32.768 khz * 1 , 2 to 16 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide- range specifications) condition b: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = av ss = pllv ss = 0 v, = 32.768 khz * 1 , 2 to 25 mhz, t a = ?20c to +75c (regular specifications), t a = ?40c to +85c (wide-range specifications) condition a condition b item symbol min. max. min. max. unit test conditions i/o port output data delay time t pw d ? 60 ? 40 ns figure 25.20 input data setup time t prs 40 ? 25 ? input data hold time t prh 40 ? 25 ? ppg pulse output delay time t pod ? 60 ? 40 ns figure 25.21 tpu timer output delay time t tocd ? 60 ? 40 ns figure 25.22 timer input setup time t tics 40 ? 25 ? timer clock input setup time t tcks 40 ? 25 ? ns figure 25.23 single edge t tckwh 1.5 ? 1.5 ? t cyc timer clock pulse width both edges t tckwl 2.5 ? 2.5 ?
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 962 of 1220 rej09b0186-0300o condition a condition b item symbol min. max. min. max. unit test conditions tmr timer output delay time t tmod ? 60 ? 40 ns figure 25.24 timer reset input setup time t tmrs 40 ? 25 ? ns figure 25.26 timer clock input setup time t tmcs 40 ? 25 ? ns figure 25.25 single edge t tmcwh 1.5 ? 1.5 ? t cyc timer clock pulse width both edges t tmcwl 2.5 ? 2.5 ? wdt0 overflow output delay time t wovd ? 60 ? 40 ns figure 25.27 wdt1 buzz output delay time t buzd ? 60 ? 40 ns figure 25.28 pwm pulse output delay time t pwod ? 60 ? 40 ns figure 25.29 sci asynchro- nous t scyc 4 ? 4 ? t cyc figure 25.30 input clock cycle synchro- nous 6 ? 6 ? input clock pulse width t sckw 0.4 0.6 0.4 0.6 t scyc input clock rise time t sckr ? 1.5 ? 1.5 t cyc input clock fall time t sckf ? 1.5 ? 1.5 transmit data delay time t txd ? 60 ? 40 ns figure 25.31 receive data setup time (synchronous) t rxs 60 ? 40 ? receive data hold time (synchronous) t rxh 60 ? 40 ? a/d converter trigger input setup time t trgs 60 ? 40 ? ns figure 25.32 notes: 1. only available i/o port, tmr, wdt0, and wdt1. 2. av cc = 3.3 v to 5.5 v if the a/d and d/a converters are not used (used as i/o ports). 3. v ref = 3.3 v to av cc if the a/d and d/a converters are not used (used as i/o ports).
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 963 of 1220 rej09b0186-0300o ports 1, 3, 4, 7, 9 a to g (read) t 2 t 1 t pwd t prh t prs ports 1, 3, 7 a to g (write) figure 25.20 i/o port input/output timing po15 to po0 t pod figure 25.21 ppg output timing t tics t tocd output compare output * input capture input * note: * tioca0 to tioca5, tiocb0 to tiocb5, tiocc0, tiocc3, tiocd0, tiocd3 figure 25.22 tpu input/output timing
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 964 of 1220 rej09b0186-0300o t tcks t tcks tclka to tclkd t tckwh t tckwl figure 25.23 tpu clock input timing t tmod tmo0, tmo1 tmo2, tmo3 figure 25.24 8-bit timer output timing t tmcs t tmcs tmci01, tmci23 t tmcwh t tmcwl figure 25.25 8-bit timer clock input timing t tmrs tmri01, tmri23 figure 25.26 8-bit timer reset input timing
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 965 of 1220 rej09b0186-0300o t wovd t wovd wdtovf figure 25.27 wdt0 output timing t buzd buzz t buzd figure 25.28 wdt1 output timing pwm3 topwm0 t pwod figure 25.29 pwm output timing sck0 to sck4 t sckw t sckr t sckf t scyc figure 25.30 sck clock input timing
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 966 of 1220 rej09b0186-0300o txd0 to txd4 (transit data) rxd0 to rxd4 (receive data) sck0 to sck4 t rxs t rxh t txd figure 25.31 sci input/output timing (clock synchronous mode) adtrg t trgs figure 25.32 a/d converter external trigger input timing
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 967 of 1220 rej09b0186-0300o table 25.10 i 2 c bus timing condition a: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 3.0 v to 5.5 v, av cc = 3.6 v to 5.5 v * 2 , v ref = 3.6 v to av cc * 3 , v ss = av ss = pllv ss = 0 v, ? 20 c to +75 c (regular specifications), t a = ? 40 c to +85 c (wide-range specifications) condition b: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = av ss = pllv ss = 0 v, ? 20 c to +75 c (regular specifications), t a = ? 40 c to +85 c (wide-range specifications) ratings item symbol min. typ. max. unit notes scl input cycle time t scl 12 t cyc ?? ns figure 25.33 scl input high pulse width t sclh 3 t cyc ?? ns scl input low pulse width t scll 5 t cyc ?? ns scl, sda input rise time t sr ?? 7.5 t cyc * 1 ns scl, sda input fall time t sf ?? 300 ns scl, sda input spike pulse elimination time t sp ?? 1 t cyc ns sda input bus free time t buf 5 t cyc ?? ns start condition input hold time t stah 3 t cyc ?? ns retransmission start condition input setup time t stas 3 t cyc ?? ns stop condition input setup time t stos 3 t cyc ?? ns data input setup time t sdas 0.5 t cyc ?? ns data input hold time t sdah 0 ?? ns scl, sda capacitive load c b ?? 400 pf notes: 1. 17.5 t cyc can be set according to the clock selected for use by the i 2 c module. for details, see section 18.4, usage notes. 2. av cc = 3.3 v to 5.5 v if the a/d and d/a converters are not used (used as i/o ports). 3. v ref = 3.3 v to av cc if the a/d and d/a converters are not used (used as i/o ports).
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 968 of 1220 rej09b0186-0300o t buf t stah t stas t sp t stos t sclh t scll t sf t sr t scl t sdah t sdas p * s * s r * v ih v il sda0 to sda1 scl0 to scl1 note: * s, p, and sr indicate the following conditions. s: start condition p: stop condition sr: retransmission start condition figure 25.33 i 2 c bus inteface input/output timing (option)
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 969 of 1220 rej09b0186-0300o 25.4 a/d conversion characteristics table 25.11 lists the a/d conversion characteristics. table 25.11 a/d conversion characteristics condition a: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 3.0 v to 5.5 v, av cc = 3.6 v to 5.5 v * 1 , v ref = 3.6 v to av cc * 2 , v ss = av ss = pllv ss = 0 v, ? 20 c to +75 c (regular specifications), t a = ? 40 c to +85 c (wide-range specifications) condition b: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = av ss = pllv ss = 0 v, ? 20 c to +75 c (regular specifications), t a = ? 40 c to +85 c (wide-range specifications) condition a condition b item min. typ. max. min. typ. max. unit resolution 10 10 10 10 10 10 bits conversion time 16 ?? 10 ?? s analog input capacitance ?? 20 ?? 20 pf permissible signal-source impedance ?? 5 ?? 5k ? nonlinearity error ?? 7.5 ?? 3.5 lsb offset error ?? 7.5 ?? 3.5 lsb full-scale error ?? 7.0 ?? 3.5 lsb quantization ? 0.5 ?? 0.5 ? lsb absolute accuracy ?? 8.0 ?? 4.0 lsb notes: 1. av cc = 3.3 v to 5.5 v if the a/d and d/a converters are not used (used as i/o ports). 2. v ref = 3.3 v to av cc if the a/d and d/a converters are not used (used as i/o ports).
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 970 of 1220 rej09b0186-0300o 25.5 d/a conversion characteristics table 25.12 shows the d/a conversion characteristics. table 25.12 d/a conversion characteristics condition a: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 3.0 v to 5.5 v, av cc = 3.6 v to 5.5 v * 1 , v ref = 3.6 v to av cc * 2 , v ss = av ss = pllv ss = 0 v, ? 20 c to +75 c (regular specifications), t a = ? 40 c to +85 c (wide-range specifications) condition b: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ref = 4.5 v to av cc , v ss = av ss = pllv ss = 0 v, ? 20 c to +75 c (regular specifications), t a = ? 40 c to +85 c (wide-range specifications) condition a condition b item min. typ. max. min. typ. max. unit test conditions resolution 8 8 8 888bits conversion time ?? 10 ?? 10 s 20-pf capacitive load absolute accuracy ? 2.0 3.0 ? 1.5 2.0 lsb 2-m ? resistive load ?? 2.0 ?? 1.5 lsb 4-m ? resistive load notes: 1. av cc = 3.3 v to 5.5 v if the a/d and d/a converters are not used (used as i/o ports). 2. v ref = 3.3 v to av cc if the a/d and d/a converters are not used (used as i/o ports).
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 971 of 1220 rej09b0186-0300o 25.6 flash memory characteristics table 25.13 flash memory characteristics conditions: v cc = pllv cc = 3.0 v to 3.6 v, pv cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = pllv ss = 0 v, t a = ? 20 c to +75 c (regular specifications), t a = ? 40 c to +85 c (wide-range specifications) item symbol min. typ. max. unit programming time * 1 * 2 * 4 t p ? 10 200 ms/128 bytes erase time * 1 * 3 * 5 t e ? 50 1000 ms/block number of rewrites n wec ?? 100 times programming wait time after swe1 bit setting * 1 x0 1 ?? s wait time after psu1 bit setting * 1 y50 ?? s wait time after p1 bit setting * 1 * 4 z0 ?? 30 s z1 ?? 10 s z2 ?? 200 s wait time after p1 bit clearing * 1 5 ?? s wait time after psu1 bit clearing * 1 5 ?? s wait time after pv1 bit setting * 1 4 ?? s wait time after h'ff dummy write * 1 2 ?? s wait time after pv1 bit clearing * 1 2 ?? s maximum number of writes * 1 * 4 n1 ?? 6times n2 ?? 994 times common wait time after swe1 bit clearing * 1 x1 100 ?? s erasing wait time after swe1 bit setting * 1 x1 ?? s wait time after esu1 bit setting * 1 y 100 ?? s wait time after e1 bit setting * 1 * 5 z ?? 10 ms wait time after e1 bit clearing * 1 10 ?? s wait time after esu1 bit clearing * 1 10 ?? s wait time after ev1 bit setting * 1 6 ?? s wait time after h'ff dummy write * 1 2 ?? s wait time after ev1 bit clearing * 1 4 ?? s maximum number of erases * 1 * 5 n ?? 100 times notes: 1. follow the program/erase algorithms when making the time settings.
section 25 electrical characteristics rev. 3.00 jan 11, 2005 page 972 of 1220 rej09b0186-0300o 2. programming time per 128 bytes. (indicates the total time during which the p1 bit is set in flash memory control register 1 (flmcr1). does not include the program-verify time.) 3. time to erase one block. (indicates the time during which the e1 bit is set in flmcr1. does not include the erase-verify time.) 4. maximum programming time (t p (max.) = wait time after p1 bit setting (z) maximum number of writes (n)) (z0 + z1) 6 + z2 994 5. maximum erase time (t e (max.) = wait time after e1 bit setting (z) maximum number of erases (n)) 25.7 usage note although both the f-ztat and masked rom versions fully meet the electrical specifications listed in this manual, due to differences in the fabrication process, the on-chip rom, and the layout patterns, there will be differences in the actual values of the electrical characteristics, the operating margins, the noise margins, and other aspects. therefore, if a system is evaluated using the f-ztat version, a similar evaluation should also be performed using the masked rom version.
appendix a instruction set rev. 3.00 jan 11, 2005 page 973 of 1220 rej09b0186-0300o appendix a instruction set a.1 instruction list operand notation rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register) mac multiply-and-accumulate register (32-bit register) (ead) destination operand (eas) source operand exr extended control register ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement +add ? subtract multiply divide logical and logical or logical exclusive or transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right ? logical not (logical complement) ( ) < > contents of operand :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7).
appendix a instruction set rev. 3.00 jan 11, 2005 page 974 of 1220 rej09b0186-0300o condition code notation symbol changes according to the result of instruction * undetermined (no guaranteed value) 0 always cleared to 0 1 always set to 1 ? not affected by execution of the instruction
appendix a instruction set rev. 3.00 jan 11, 2005 page 975 of 1220 rej09b0186-0300o table a.1 instruction set (1) data transfer instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?ern/@ern+ @aa @(d,pc) @@aa ? mnemonic mov mov.b #xx:8,rd b 2 mov.b rs,rd b 2 mov.b @ers,rd b 2 mov.b @(d:16,ers),rd b 4 mov.b @(d:32,ers),rd b 8 mov.b @ers+,rd b 2 mov.b @aa:8,rd b 2 mov.b @aa:16,rd b 4 mov.b @aa:32,rd b 6 mov.b rs,@erd b 2 mov.b rs,@(d:16,erd) b 4 mov.b rs,@(d:32,erd) b 8 mov.b rs,@-erd b 2 mov.b rs,@aa:8 b 2 mov.b rs,@aa:16 b 4 mov.b rs,@aa:32 b 6 mov.w #xx:16,rd w 4 mov.w rs,rd w 2 mov.w @ers,rd w 2 #xx:8 rd8 ? ? 0 ? 1 rs8 rd8 ? ? 0 ? 1 @ers rd8 ? ? 0 ? 2 @(d:16,ers) rd8 ? ? 0 ? 3 @(d:32,ers) rd8 ? ? 0 ? 5 @ers rd8,ers32+1 ers32 ? ? 0 ? 3 @aa:8 rd8 ? ? 0 ? 2 @aa:16 rd8 ? ? 0 ? 3 @aa:32 rd8 ? ? 0 ? 4 rs8 @erd ? ? 0 ? 2 rs8 @(d:16,erd) ? ? 0 ? 3 rs8 @(d:32,erd) ? ? 0 ? 5 erd32-1 erd32,rs8 @erd ? ? 0 ? 3 rs8 @aa:8 ? ? 0 ? 2 rs8 @aa:16 ? ? 0 ? 3 rs8 @aa:32 ? ? 0 ? 4 #xx:16 rd16 ? ? 0 ? 2 rs16 rd16 ? ? 0 ? 1 @ers rd16 ? ? 0 ? 2 operation condition code ihnzvc advanced no. of states * 1 ??????????????????? ???????????????????
appendix a instruction set rev. 3.00 jan 11, 2005 page 976 of 1220 rej09b0186-0300o addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic mov mov.w @(d:16,ers),rd w 4 mov.w @(d:32,ers),rd w 8 mov.w @ers+,rd w 2 mov.w @aa:16,rd w 4 mov.w @aa:32,rd w 6 mov.w rs,@erd w 2 mov.w rs,@(d:16,erd) w 4 mov.w rs,@(d:32,erd) w 8 mov.w rs,@-erd w 2 mov.w rs,@aa:16 w 4 mov.w rs,@aa:32 w 6 mov.l #xx:32,erd l 6 mov.l ers,erd l 2 mov.l @ers,erd l 4 mov.l @(d:16,ers),erd l 6 mov.l @(d:32,ers),erd l 10 mov.l @ers+,erd l 4 mov.l @aa:16,erd l 6 mov.l @aa:32,erd l 8 @(d:16,ers) rd16 ? ? 0 ? 3 @(d:32,ers) rd16 ? ? 0 ? 5 @ers rd16,ers32+2 ers32 ? ? 0 ? 3 @aa:16 rd16 ? ? 0 ? 3 @aa:32 rd16 ? ? 0 ? 4 rs16 @erd ? ? 0 ? 2 rs16 @(d:16,erd) ? ? 0 ? 3 rs16 @(d:32,erd) ? ? 0 ? 5 erd32-2 erd32,rs16 @erd ? ? 0 ? 3 rs16 @aa:16 ? ? 0 ? 3 rs16 @aa:32 ? ? 0 ? 4 #xx:32 erd32 ? ? 0 ? 3 ers32 erd32 ? ? 0 ? 1 @ers erd32 ? ? 0 ? 4 @(d:16,ers) erd32 ? ? 0 ? 5 @(d:32,ers) erd32 ? ? 0 ? 7 @ers erd32,ers32+4 @ers32 ? ? 0 ? 5 @aa:16 erd32 ? ? 0 ? 5 @aa:32 erd32 ? ? 0 ? 6 operation condition code ihnzvc advanced no. of states * 1 ??????????????????? ???????????????????
appendix a instruction set rev. 3.00 jan 11, 2005 page 977 of 1220 rej09b0186-0300o addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic mov pop push ldm stm movfpe movtpe mov.l ers,@erd l 4 mov.l ers,@(d:16,erd) l 6 mov.l ers,@(d:32,erd) l 10 mov.l ers,@-erd l 4 mov.l ers,@aa:16 l 6 mov.l ers,@aa:32 l 8 pop.w rn w 2 pop.l ern l 4 push.w rn w 2 push.l ern l 4 ldm @sp+,(erm-ern) l 4 stm (erm-ern),@-sp l 4 movfpe @aa:16,rd movtpe rs,@aa:16 ers32 @erd ? ? 0 ? 4 ers32 @(d:16,erd) ? ? 0 ? 5 ers32 @(d:32,erd) ? ? 0 ? 7 erd32-4 erd32,ers32 @ erd ? ? 0 ? 5 ers32 @aa:16 ? ? 0 ? 5 ers32 @aa:32 ? ? 0 ? 6 @sp rn16,sp+2 sp ? ? 0 ? 3 @sp ern32,sp+4 sp ? ? 0 ? 5 sp-2 sp,rn16 @sp ? ? 0 ? 3 sp-4 sp,ern32 @sp ? ? 0 ? 5 (@sp ern32,sp+4 sp) ? ? ? ? ? ? 7/9/11 [1] repeated for each register restored (sp-4 sp,ern32 @sp) ? ? ? ? ? ? 7/9/11 [1] repeated for each register saved [2] [2] operation condition code ihnzvc advanced no. of states * 1 ?????????? ?????????? cannot be used in the h8s/2643 group cannot be used in the h8s/2643 group
appendix a instruction set rev. 3.00 jan 11, 2005 page 978 of 1220 rej09b0186-0300o (2) arithmetic instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic add addx adds inc daa sub add.b #xx:8,rd b 2 add.b rs,rd b 2 add.w #xx:16,rd w 4 add.w rs,rd w 2 add.l #xx:32,erd l 6 add.l ers,erd l 2 addx #xx:8,rd b 2 addx rs,rd b 2 adds #1,erd l 2 adds #2,erd l 2 adds #4,erd l 2 inc.b rd b 2 inc.w #1,rd w 2 inc.w #2,rd w 2 inc.l #1,erd l 2 inc.l #2,erd l 2 daa rd b 2 sub.b rs,rd b 2 sub.w #xx:16,rd w 4 rd8+#xx:8 rd8 ? 1 rd8+rs8 rd8 ? 1 rd16+#xx:16 rd16 ? [3] 2 rd16+rs16 rd16 ? [3] 1 erd32+#xx:32 erd32 ? [4] 3 erd32+ers32 erd32 ? [4] 1 rd8+#xx:8+c rd8 ? [5] 1 rd8+rs8+c rd8 ? [5] 1 erd32+1 erd32 ? ? ? ? ? ? 1 erd32+2 erd32 ? ? ? ? ? ? 1 erd32+4 erd32 ? ? ? ? ? ? 1 rd8+1 rd8 ? ? ? 1 rd16+1 rd16 ? ? ? 1 rd16+2 rd16 ? ? ? 1 erd32+1 erd32 ? ? ? 1 erd32+2 erd32 ? ? ? 1 rd8 decimal adjust rd8 ? * * 1 rd8-rs8 rd8 ? 1 rd16-#xx:16 rd16 ? [3] 2 operation condition code ihnzvc advanced no. of states * 1 ??? ? ???????? ?? ????? ???????? ???????? ???????? ?????? ???????? ?? ??
appendix a instruction set rev. 3.00 jan 11, 2005 page 979 of 1220 rej09b0186-0300o addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic sub subx subs dec das mulxu mulxs sub.w rs,rd w 2 sub.l #xx:32,erd l 6 sub.l ers,erd l 2 subx #xx:8,rd b 2 subx rs,rd b 2 subs #1,erd l 2 subs #2,erd l 2 subs #4,erd l 2 dec.b rd b 2 dec.w #1,rd w 2 dec.w #2,rd w 2 dec.l #1,erd l 2 dec.l #2,erd l 2 das rd b 2 mulxu.b rs,rd b 2 mulxu.w rs,erd w 2 mulxs.b rs,rd b 4 mulxs.w rs,erd w 4 rd16-rs16 rd16 ? [3] 1 erd32-#xx:32 erd32 ? [4] 3 erd32-ers32 erd32 ? [4] 1 rd8-#xx:8-c rd8 ? [5] 1 rd8-rs8-c rd8 ? [5] 1 erd32-1 erd32 ? ? ? ? ? ? 1 erd32-2 erd32 ? ? ? ? ? ? 1 erd32-4 erd32 ? ? ? ? ? ? 1 rd8-1 rd8 ? ? ? 1 rd16-1 rd16 ? ? ? 1 rd16-2 rd16 ? ? ? 1 erd32-1 erd32 ? ? ? 1 erd32-2 erd32 ? ? ? 1 rd8 decimal adjust rd8 ? * * ? 1 rd8 rs8 rd16 (unsigned multiplication) ? ? ? ? ? ? 3 rd16 rs16 erd32 ? ? ? ? ? ? 4 (unsigned multiplication) rd8 rs8 rd16 (signed multiplication) ? ? ? ? 4 rd16 rs16 erd32 ? ? ? ? 5 (signed multiplication) operation condition code ihnzvc advanced no. of states * 1 ?? ?? ?????? ?????? ????? ??? ????? ????? ????? ??
appendix a instruction set rev. 3.00 jan 11, 2005 page 980 of 1220 rej09b0186-0300o addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic divxu divxs cmp neg extu divxu.b rs,rd b 2 divxu.w rs,erd w 2 divxs.b rs,rd b 4 divxs.w rs,erd w 4 cmp.b #xx:8,rd b 2 cmp.b rs,rd b 2 cmp.w #xx:16,rd w 4 cmp.w rs,rd w 2 cmp.l #xx:32,erd l 6 cmp.l ers,erd l 2 neg.b rd b 2 neg.w rd w 2 neg.l erd l 2 extu.w rd w 2 extu.l erd l 2 rd16 rs8 rd16 (rdh: remainder, ? ? [6] [7] ? ? 12 rdl: quotient) (unsigned division) erd32 rs16 erd32 (ed: remainder, ? ? [6] [7] ? ? 20 rd: quotient) (unsigned division) rd16 rs8 rd16 (rdh: remainder, ? ? [8] [7] ? ? 13 rdl: quotient) (signed division) erd32 rs16 erd32 (ed: remainder, ? ? [8] [7] ? ? 21 rd: quotient) (signed division) rd8-#xx:8 ? 1 rd8-rs8 ? 1 rd16-#xx:16 ? [3] 2 rd16-rs16 ? [3] 1 erd32-#xx:32 ? [4] 3 erd32-ers32 ? [4] 1 0-rd8 rd8 ? 1 0-rd16 rd16 ? 1 0-erd32 erd32 ? 1 0 ( of rd16) ? ? 0 0 ? 1 0 ( of erd32) ? ? 0 0 ? 1 operation condition code ihnzvc advanced no. of states * 1 ??? ?? ??????????? ????????? ????????? ?????????
appendix a instruction set rev. 3.00 jan 11, 2005 page 981 of 1220 rej09b0186-0300o addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic exts tas * 3 mac clrmac ldmac stmac exts.w rd w 2 exts.l erd l 2 tas @erd b 4 mac @ern+, @erm+ 4 clrmac ldmac ers,mach ldmac ers,macl stmac mach,erd stmac macl,erd ( of rd16) ? ? 0 ? 1 ( of rd16) ( of erd32) ? ? 0 ? 1 ( of erd32) @erd-0 ccr set, (1) ? ? 0 ? 4 ( < bit 7 > of @erd) @ernx@erm+mac mac ? ? ? ? ? ? 4 (signal multiplication) [11] [11] [11] @ern+2 ern, erm+2 erm 0 mach, macl ? ? ? ? ? ? 2 [12] ers mach ? ? ? ? ? ? 2 [12] ers macl ? ? ? ? ? ? 2 [12] mach erd ? ? ? 1 [12] macl erd ? ? ? 1 [12] operation condition code ihnzvc advanced no. of states * 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? l l l l 2 2 2 2 2
appendix a instruction set rev. 3.00 jan 11, 2005 page 982 of 1220 rej09b0186-0300o (3) logical instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic and or xor not and.b #xx:8,rd b 2 and.b rs,rd b 2 and.w #xx:16,rd w 4 and.w rs,rd w 2 and.l #xx:32,erd l 6 and.l ers,erd l 4 or.b #xx:8,rd b 2 or.b rs,rd b 2 or.w #xx:16,rd w 4 or.w rs,rd w 2 or.l #xx:32,erd l 6 or.l ers,erd l 4 xor.b #xx:8,rd b 2 xor.b rs,rd b 2 xor.w #xx:16,rd w 4 xor.w rs,rd w 2 xor.l #xx:32,erd l 6 xor.l ers,erd l 4 not.b rd b 2 not.w rd w 2 not.l erd l 2 rd8 #xx:8 rd8 ? ? 0 ? 1 rd8 rs8 rd8 ? ? 0 ? 1 rd16 #xx:16 rd16 ? ? 0 ? 2 rd16 rs16 rd16 ? ? 0 ? 1 erd32 #xx:32 erd32 ? ? 0 ? 3 erd32 ers32 erd32 ? ? 0 ? 2 rd8 ? #xx:8 rd8 ? ? 0 ? 1 rd8 ? rs8 rd8 ? ? 0 ? 1 rd16 ? #xx:16 rd16 ? ? 0 ? 2 rd16 ? rs16 rd16 ? ? 0 ? 1 erd32 ? #xx:32 erd32 ? ? 0 ? 3 erd32 ? ers32 erd32 ? ? 0 ? 2 rd8 #xx:8 rd8 ? ? 0 ? 1 rd8 rs8 rd8 ? ? 0 ? 1 rd16 #xx:16 rd16 ? ? 0 ? 2 rd16 rs16 rd16 ? ? 0 ? 1 erd32 #xx:32 erd32 ? ? 0 ? 3 erd32 ers32 erd32 ? ? 0 ? 2 ? rd8 rd8 ? ? 0 ? 1 ? rd16 rd16 ? ? 0 ? 1 ? erd32 erd32 ? ? 0 ? 1 operation condition code ihnzvc advanced no. of states * 1 ????????????????????? ?????????????????????
appendix a instruction set rev. 3.00 jan 11, 2005 page 983 of 1220 rej09b0186-0300o (4) shift instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic shal shar shll shal.b rd b 2 shal.b #2,rd b 2 shal.w rd w 2 shal.w #2,rd w 2 shal.l erd l 2 shal.l #2,erd l 2 shar.b rd b 2 shar.b #2,rd b 2 shar.w rd w 2 shar.w #2,rd w 2 shar.l erd l 2 shar.l #2,erd l 2 shll.b rd b 2 shll.b #2,rd b 2 shll.w rd w 2 shll.w #2,rd w 2 shll.l erd l 2 shll.l #2,erd l 2 ? ? 1 ? ? 1 ? ? 1 ? ? 1 ? ? 1 ? ? 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 operation condition code ihnzvc advanced no. of states * 1 ?????????????????? ?????????????????? ?????? ?????????????????? c msb lsb msb lsb 0 c msb lsb c 0
appendix a instruction set rev. 3.00 jan 11, 2005 page 984 of 1220 rej09b0186-0300o addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic shlr rotxl rotxr shlr.b rd b 2 shlr.b #2,rd b 2 shlr.w rd w 2 shlr.w #2,rd w 2 shlr.l erd l 2 shlr.l #2,erd l 2 rotxl.b rd b 2 rotxl.b #2,rd b 2 rotxl.w rd w 2 rotxl.w #2,rd w 2 rotxl.l erd l 2 rotxl.l #2,erd l 2 rotxr.b rd b 2 rotxr.b #2,rd b 2 rotxr.w rd w 2 rotxr.w #2,rd w 2 rotxr.l erd l 2 rotxr.l #2,erd l 2 ? ? ? 0 0 1 ? ? ? 0 0 1 ? ? ? 0 0 1 ? ? ? 0 0 1 ? ? ? 0 0 1 ? ? ? 0 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 operation condition code ihnzvc advanced no. of states * 1 ?????????????????? ?????????????????? ???????????? c msb lsb 0 c msb lsb c msb lsb
appendix a instruction set rev. 3.00 jan 11, 2005 page 985 of 1220 rej09b0186-0300o ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? ? 0 1 ? ? 0 1 ? ? ? 0 1 1 ? ? 0 1 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic rotl rotr rotl.b rd b 2 rotl.b #2,rd b 2 rotl.w rd w 2 rotl.w #2,rd w 2 rotl.l erd l 2 rotl.l #2,erd l 2 rotr.b rd b 2 rotr.b #2,rd b 2 rotr.w rd w 2 rotr.w #2,rd w 2 rotr.l erd l 2 rotr.l #2,erd l 2 operation condition code ihnzvc advanced no. of states * 1 ???????????? ???????????? ???????????? c msb lsb c msb lsb
appendix a instruction set rev. 3.00 jan 11, 2005 page 986 of 1220 rej09b0186-0300o (5) bit-manipulation instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic bset bclr bset #xx:3,rd b 2 bset #xx:3,@erd b 4 bset #xx:3,@aa:8 b 4 bset #xx:3,@aa:16 b 6 bset #xx:3,@aa:32 b 8 bset rn,rd b 2 bset rn,@erd b 4 bset rn,@aa:8 b 4 bset rn,@aa:16 b 6 bset rn,@aa:32 b 8 bclr #xx:3,rd b 2 bclr #xx:3,@erd b 4 bclr #xx:3,@aa:8 b 4 bclr #xx:3,@aa:16 b 6 bclr #xx:3,@aa:32 b 8 bclr rn,rd b 2 bclr rn,@erd b 4 bclr rn,@aa:8 b 4 bclr rn,@aa:16 b 6 (#xx:3 of rd8) 1 ? ? ? ? ? ? 1 (#xx:3 of @erd) 1 ? ? ? ? ? ? 4 (#xx:3 of @aa:8) 1 ? ? ? ? ? ? 4 (#xx:3 of @aa:16) 1 ? ? ? ? ? ? 5 (#xx:3 of @aa:32) 1 ? ? ? ? ? ? 6 (rn8 of rd8) 1 ? ? ? ? ? ? 1 (rn8 of @erd) 1 ? ? ? ? ? ? 4 (rn8 of @aa:8) 1 ? ? ? ? ? ? 4 (rn8 of @aa:16) 1 ? ? ? ? ? ? 5 (rn8 of @aa:32) 1 ? ? ? ? ? ? 6 (#xx:3 of rd8) 0 ? ? ? ? ? ? 1 (#xx:3 of @erd) 0 ? ? ? ? ? ? 4 (#xx:3 of @aa:8) 0 ? ? ? ? ? ? 4 (#xx:3 of @aa:16) 0 ? ? ? ? ? ? 5 (#xx:3 of @aa:32) 0 ? ? ? ? ? ? 6 (rn8 of rd8) 0 ? ? ? ? ? ? 1 (rn8 of @erd) 0 ? ? ? ? ? ? 4 (rn8 of @aa:8) 0 ? ? ? ? ? ? 4 (rn8 of @aa:16) 0 ? ? ? ? ? ? 5 operation condition code ihnzvc advanced no. of states * 1
appendix a instruction set rev. 3.00 jan 11, 2005 page 987 of 1220 rej09b0186-0300o addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic bclr bnot btst bclr rn,@aa:32 b 8 bnot #xx:3,rd b 2 bnot #xx:3,@erd b 4 bnot #xx:3,@aa:8 b 4 bnot #xx:3,@aa:16 b 6 bnot #xx:3,@aa:32 b 8 bnot rn,rd b 2 bnot rn,@erd b 4 bnot rn,@aa:8 b 4 bnot rn,@aa:16 b 6 bnot rn,@aa:32 b 8 btst #xx:3,rd b 2 btst #xx:3,@erd b 4 btst #xx:3,@aa:8 b 4 btst #xx:3,@aa:16 b 6 (rn8 of @aa:32) 0 ? ? ? ? ? ? 6 (#xx:3 of rd8) [ ? (#xx:3 of rd8)] ? ? ? ? ? ? 1 (#xx:3 of @erd) ? ? ? ? ? ? 4 [ ? (#xx:3 of @erd)] (#xx:3 of @aa:8) ? ? ? ? ? ? 4 [ ? (#xx:3 of @aa:8)] (#xx:3 of @aa:16) ? ? ? ? ? ? 5 [ ? (#xx:3 of @aa:16)] (#xx:3 of @aa:32) ? ? ? ? ? ? 6 [ ? (#xx:3 of @aa:32)] (rn8 of rd8) [ ? (rn8 of rd8)] ? ? ? ? ? ? 1 (rn8 of @erd) [ ? (rn8 of @erd)] ? ? ? ? ? ? 4 (rn8 of @aa:8) [ ? (rn8 of @aa:8)] ? ? ? ? ? ? 4 (rn8 of @aa:16) ? ? ? ? ? ? 5 [ ? (rn8 of @aa:16)] (rn8 of @aa:32) ? ? ? ? ? ? 6 [ ? (rn8 of @aa:32)] ? (#xx:3 of rd8) z ? ? ? ? ? 1 ? (#xx:3 of @erd) z ? ? ? ? ? 3 ? (#xx:3 of @aa:8) z ? ? ? ? ? 3 ? (#xx:3 of @aa:16) z ? ? ? ? ? 4 operation condition code ihnzvc advanced no. of states * 1 ????
appendix a instruction set rev. 3.00 jan 11, 2005 page 988 of 1220 rej09b0186-0300o addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic btst bld bild bst btst #xx:3,@aa:32 b 8 btst rn,rd b 2 btst rn,@erd b 4 btst rn,@aa:8 b 4 btst rn,@aa:16 b 6 btst rn,@aa:32 b 8 bld #xx:3,rd b 2 bld #xx:3,@erd b 4 bld #xx:3,@aa:8 b 4 bld #xx:3,@aa:16 b 6 bld #xx:3,@aa:32 b 8 bild #xx:3,rd b 2 bild #xx:3,@erd b 4 bild #xx:3,@aa:8 b 4 bild #xx:3,@aa:16 b 6 bild #xx:3,@aa:32 b 8 bst #xx:3,rd b 2 bst #xx:3,@erd b 4 bst #xx:3,@aa:8 b 4 ? (#xx:3 of @aa:32) z ? ? ? ? ? 5 ? (rn8 of rd8) z ? ? ? ? ? 1 ? (rn8 of @erd) z ? ? ? ? ? 3 ? (rn8 of @aa:8) z ? ? ? ? ? 3 ? (rn8 of @aa:16) z ? ? ? ? ? 4 ? (rn8 of @aa:32) z ? ? ? ? ? 5 (#xx:3 of rd8) c ? ? ? ? ? 1 (#xx:3 of @erd) c ? ? ? ? ? 3 (#xx:3 of @aa:8) c ? ? ? ? ? 3 (#xx:3 of @aa:16) c ? ? ? ? ? 4 (#xx:3 of @aa:32) c ? ? ? ? ? 5 ? (#xx:3 of rd8) c ? ? ? ? ? 1 ? (#xx:3 of @erd) c ? ? ? ? ? 3 ? (#xx:3 of @aa:8) c ? ? ? ? ? 3 ? (#xx:3 of @aa:16) c ? ? ? ? ? 4 ? (#xx:3 of @aa:32) c ? ? ? ? ? 5 c (#xx:3 of rd8) ? ? ? ? ? ? 1 c (#xx:3 of @erd) ? ? ? ? ? ? 4 c (#xx:3 of @aa:8) ? ? ? ? ? ? 4 operation condition code ihnzvc advanced no. of states * 1 ?????????? ??????
appendix a instruction set rev. 3.00 jan 11, 2005 page 989 of 1220 rej09b0186-0300o addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic bst bist band biand bor bst #xx:3,@aa:16 b 6 bst #xx:3,@aa:32 b 8 bist #xx:3,rd b 2 bist #xx:3,@erd b 4 bist #xx:3,@aa:8 b 4 bist #xx:3,@aa:16 b 6 bist #xx:3,@aa:32 b 8 band #xx:3,rd b 2 band #xx:3,@erd b 4 band #xx:3,@aa:8 b 4 band #xx:3,@aa:16 b 6 band #xx:3,@aa:32 b 8 biand #xx:3,rd b 2 biand #xx:3,@erd b 4 biand #xx:3,@aa:8 b 4 biand #xx:3,@aa:16 b 6 biand #xx:3,@aa:32 b 8 bor #xx:3,rd b 2 bor #xx:3,@erd b 4 c (#xx:3 of @aa:16) ? ? ? ? ? ? 5 c (#xx:3 of @aa:32) ? ? ? ? ? ? 6 ? c (#xx:3 of rd8) ? ? ? ? ? ? 1 ? c (#xx:3 of @erd) ? ? ? ? ? ? 4 ? c (#xx:3 of @aa:8) ? ? ? ? ? ? 4 ? c (#xx:3 of @aa:16) ? ? ? ? ? ? 5 ? c (#xx:3 of @aa:32) ? ? ? ? ? ? 6 c (#xx:3 of rd8) c ? ? ? ? ? 1 c (#xx:3 of @erd) c ? ? ? ? ? 3 c (#xx:3 of @aa:8) c ? ? ? ? ? 3 c (#xx:3 of @aa:16) c ? ? ? ? ? 4 c (#xx:3 of @aa:32) c ? ? ? ? ? 5 c [ ? (#xx:3 of rd8)] c ? ? ? ? ? 1 c [ ? (#xx:3 of @erd)] c ? ? ? ? ? 3 c [ ? (#xx:3 of @aa:8)] c ? ? ? ? ? 3 c [ ? (#xx:3 of @aa:16)] c ? ? ? ? ? 4 c [ ? (#xx:3 of @aa:32)] c ? ? ? ? ? 5 c (#xx:3 of rd8) c ? ? ? ? ? 1 c (#xx:3 of @erd) c ? ? ? ? ? 3 operation condition code ihnzvc advanced no. of states * 1 ????????????
appendix a instruction set rev. 3.00 jan 11, 2005 page 990 of 1220 rej09b0186-0300o addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic bor bior bxor bixor bor #xx:3,@aa:8 b 4 bor #xx:3,@aa:16 b 6 bor #xx:3,@aa:32 b 8 bior #xx:3,rd b 2 bior #xx:3,@erd b 4 bior #xx:3,@aa:8 b 4 bior #xx:3,@aa:16 b 6 bior #xx:3,@aa:32 b 8 bxor #xx:3,rd b 2 bxor #xx:3,@erd b 4 bxor #xx:3,@aa:8 b 4 bxor #xx:3,@aa:16 b 6 bxor #xx:3,@aa:32 b 8 bixor #xx:3,rd b 2 bixor #xx:3,@erd b 4 bixor #xx:3,@aa:8 b 4 bixor #xx:3,@aa:16 b 6 bixor #xx:3,@aa:32 b 8 c (#xx:3 of @aa:8) c ? ? ? ? ? 3 c (#xx:3 of @aa:16) c ? ? ? ? ? 4 c (#xx:3 of @aa:32) c ? ? ? ? ? 5 c [ ? (#xx:3 of rd8)] c ? ? ? ? ? 1 c [ ? (#xx:3 of @erd)] c ? ? ? ? ? 3 c [ ? (#xx:3 of @aa:8)] c ? ? ? ? ? 3 c [ ? (#xx:3 of @aa:16)] c ? ? ? ? ? 4 c [ ? (#xx:3 of @aa:32)] c ? ? ? ? ? 5 c (#xx:3 of rd8) c ? ? ? ? ? 1 c (#xx:3 of @erd) c ? ? ? ? ? 3 c (#xx:3 of @aa:8) c ? ? ? ? ? 3 c (#xx:3 of @aa:16) c ? ? ? ? ? 4 c (#xx:3 of @aa:32) c ? ? ? ? ? 5 c [ ? (#xx:3 of rd8)] c ? ? ? ? ? 1 c [ ? (#xx:3 of @erd)] c ? ? ? ? ? 3 c [ ? (#xx:3 of @aa:8)] c ? ? ? ? ? 3 c [ ? (#xx:3 of @aa:16)] c ? ? ? ? ? 4 c [ ? (#xx:3 of @aa:32)] c ? ? ? ? ? 5 operation condition code ihnzvc advanced no. of states * 1 ??????????????????
appendix a instruction set rev. 3.00 jan 11, 2005 page 991 of 1220 rej09b0186-0300o (6) branch instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic bcc always ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 never ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 c z=0 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 c z=1 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 c=0 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 c=1 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 z=0 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 z=1 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 v=0 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 operation condition code branching condition ihnzvc advanced no. of states * 1 bra d:8(bt d:8) ? 2 if condition is true then bra d:16(bt d:16) ? 4 pc pc+d brn d:8(bf d:8) ? 2 else next; brn d:16(bf d:16) ? 4 bhi d:8 ? 2 bhi d:16 ? 4 bls d:8 ? 2 bls d:16 ? 4 bcc d:b(bhs d:8) ? 2 bcc d:16(bhs d:16) ? 4 bcs d:8(blo d:8) ? 2 bcs d:16(blo d:16) ? 4 bne d:8 ? 2 bne d:16 ? 4 beq d:8 ? 2 beq d:16 ? 4 bvc d:8 ? 2 bvc d:16 ? 4
appendix a instruction set rev. 3.00 jan 11, 2005 page 992 of 1220 rej09b0186-0300o addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic bcc v=1 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 n=0 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 n=1 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 n v=0 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 n v=1 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 z (n v)=0 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 z (n v)=1 ? ? ? ? ? ? 2 ? ? ? ? ? ? 3 operation condition code branching condition ihnzvc advanced no. of states * 1 bvs d:8 ? 2 bvs d:16 ? 4 bpl d:8 ? 2 bpl d:16 ? 4 bmi d:8 ? 2 bmi d:16 ? 4 bge d:8 ? 2 bge d:16 ? 4 blt d:8 ? 2 blt d:16 ? 4 bgt d:8 ? 2 bgt d:16 ? 4 ble d:8 ? 2 ble d:16 ? 4
appendix a instruction set rev. 3.00 jan 11, 2005 page 993 of 1220 rej09b0186-0300o addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic jmp bsr jsr rts jmp @ern ? 2 jmp @aa:24 ? 4 jmp @@aa:8 ? 2 bsr d:8 ? 2 bsr d:16 ? 4 jsr @ern ? 2 jsr @aa:24 ? 4 jsr @@aa:8 ? 2 rts ? 2 pc ern ? ? ? ? ? ? 2 pc aa:24 ? ? ? ? ? ? 3 pc @aa:8 ? ? ? ? ? ? 5 pc @-sp,pc pc+d:8 ? ? ? ? ? ? 4 pc @-sp,pc pc+d:16 ? ? ? ? ? ? 5 pc @-sp,pc ern ? ? ? ? ? ? 4 pc @-sp,pc aa:24 ? ? ? ? ? ? 5 pc @-sp,pc @aa:8 ? ? ? ? ? ? 6 pc @sp+ ? ? ? ? ? ? 5 operation condition code ihnzvc advanced no. of states * 1
appendix a instruction set rev. 3.00 jan 11, 2005 page 994 of 1220 rej09b0186-0300o (7) system control instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic trapa rte sleep ldc trapa #xx:2 ? rte ? sleep ? ldc #xx:8,ccr b 2 ldc #xx:8,exr b 4 ldc rs,ccr b 2 ldc rs,exr b 2 ldc @ers,ccr w 4 ldc @ers,exr w 4 ldc @(d:16,ers),ccr w 6 ldc @(d:16,ers),exr w 6 ldc @(d:32,ers),ccr w 10 ldc @(d:32,ers),exr w 10 ldc @ers+,ccr w 4 ldc @ers+,exr w 4 ldc @aa:16,ccr w 6 ldc @aa:16,exr w 6 ldc @aa:32,ccr w 8 ldc @aa:32,exr w 8 pc @-sp,ccr @-sp, 1 ? ? ? ? ? 8 [9] exr @-sp, pc exr @sp+,ccr @sp+, 5 [9] pc @sp+ transition to power-down state ? ? ? ? ? ? 2 #xx:8 ccr 1 #xx:8 exr ? ? ? ? ? ? 2 rs8 ccr 1 rs8 exr ? ? ? ? ? ? 1 @ers ccr 3 @ers exr ? ? ? ? ? ? 3 @(d:16,ers) ccr 4 @(d:16,ers) exr ? ? ? ? ? ? 4 @(d:32,ers) ccr 6 @(d:32,ers) exr ? ? ? ? ? ? 6 @ers ccr,ers32+2 ers32 4 @ers exr,ers32+2 ers32 ? ? ? ? ? ? 4 @aa:16 ccr 4 @aa:16 exr ? ? ? ? ? ? 4 @aa:32 ccr 5 @aa:32 exr ? ? ? ? ? ? 5 operation condition code ihnzvc advanced no. of states * 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
appendix a instruction set rev. 3.00 jan 11, 2005 page 995 of 1220 rej09b0186-0300o addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic stc andc orc xorc nop stc ccr,rd b 2 stc exr,rd b 2 stc ccr,@erd w 4 stc exr,@erd w 4 stc ccr,@(d:16,erd) w 6 stc exr,@(d:16,erd) w 6 stc ccr,@(d:32,erd) w 10 stc exr,@(d:32,erd) w 10 stc ccr,@-erd w 4 stc exr,@-erd w 4 stc ccr,@aa:16 w 6 stc exr,@aa:16 w 6 stc ccr,@aa:32 w 8 stc exr,@aa:32 w 8 andc #xx:8,ccr b 2 andc #xx:8,exr b 4 orc #xx:8,ccr b 2 orc #xx:8,exr b 4 xorc #xx:8,ccr b 2 xorc #xx:8,exr b 4 nop ? 2 ccr rd8 ? ? ? ? ? ? 1 exr rd8 ? ? ? ? ? ? 1 ccr @erd ? ? ? ? ? ? 3 exr @erd ? ? ? ? ? ? 3 ccr @(d:16,erd) ? ? ? ? ? ? 4 exr @(d:16,erd) ? ? ? ? ? ? 4 ccr @(d:32,erd) ? ? ? ? ? ? 6 exr @(d:32,erd) ? ? ? ? ? ? 6 erd32-2 erd32,ccr @erd ? ? ? ? ? ? 4 erd32-2 erd32,exr @erd ? ? ? ? ? ? 4 ccr @aa:16 ? ? ? ? ? ? 4 exr @aa:16 ? ? ? ? ? ? 4 ccr @aa:32 ? ? ? ? ? ? 5 exr @aa:32 ? ? ? ? ? ? 5 ccr #xx:8 ccr 1 exr #xx:8 exr ? ? ? ? ? ? 2 ccr #xx:8 ccr 1 exr #xx:8 exr ? ? ? ? ? ? 2 ccr #xx:8 ccr 1 exr #xx:8 exr ? ? ? ? ? ? 2 pc pc+2 ? ? ? ? ? ? 1 operation condition code ihnzvc advanced no. of states * 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
appendix a instruction set rev. 3.00 jan 11, 2005 page 996 of 1220 rej09b0186-0300o (8) block transfer instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @ ? ern/@ern+ @aa @(d,pc) @@aa ? mnemonic eepmov notes: 1. the number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. 2. n is the initial value of r4l or r4. 3. only register er0, er1, er4, or er5 should be used when using the tas instruction. [1] seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. [2] cannot be used in the h8s/2643 group. [3] set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. [4] set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. [5] retains its previous value when the result is zero; otherwise cleared to 0. [6] set to 1 when the divisor is negative; otherwise cleared to 0. [7] set to 1 when the divisor is zero; otherwise cleared to 0. [8] set to 1 when the quotient is negative; otherwise cleared to 0. [9] one additional state is required for execution when exr is valid. eepmov.b ? 4 eepmov.w ? 4 if r4l 0 ? ? ? ? ? ? 4+2n * 2 repeat @er5 @er6 er5+1 er5 er6+1 er6 r4l-1 r4l until r4l=0 else next; if r4 0 ? ? ? ? ? ? 4+2n * 2 repeat @er5 @er6 er5+1 er5 er6+1 er6 r4-1 r4 until r4=0 else next; operation condition code ihnzvc advanced no. of states * 1
appendix a instruction set rev. 3.00 jan 11, 2005 page 997 of 1220 rej09b0186-0300o a.2 instruction codes table a.2 shows the instruction codes.
appendix a instruction set rev. 3.00 jan 11, 2005 page 998 of 1220 rej09b0186-0300o table a.2 instruction codes add.b #xx:8,rd add.b rs,rd add.w #xx:16,rd add.w rs,rd add.l #xx:32,erd add.l ers,erd adds #1,erd adds #2,erd adds #4,erd addx #xx:8,rd addx rs,rd and.b #xx:8,rd and.b rs,rd and.w #xx:16,rd and.w rs,rd and.l #xx:32,erd and.l ers,erd andc #xx:8,ccr andc #xx:8,exr band #xx:3,rd band #xx:3,@erd band #xx:3,@aa:8 band #xx:3,@aa:16 band #xx:3,@aa:32 bra d:8 (bt d:8) bra d:16 (bt d:16) brn d:8 (bf d:8) brn d:16 (bf d:16) mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion add adds addx and andc band bcc b b w w l l l l l b b b b w w l l b b b b b b b ? ? ? ? 1 0 0 ers imm erd 0 0 0 0 0 0 erd erd erd erd erd erd ers imm imm 0erd 0imm 0imm 0 0 0 8 0 7 0 7 0 0 0 0 9 0 e 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4 5 rd 8 9 9 a a b b b rd e rd 6 9 6 a 1 6 1 6 c e a a 0 8 1 8 rd rd rd rd rd rd rd 0 1 rd 0 0 0 0 0 6 0 7 7 6 6 6 6 0 0 76 0 76 0 imm imm imm imm abs disp disp rs 1 rs 1 0 8 9 rs rs 6 rs 6 f 4 1 3 0 1 imm imm abs disp disp imm imm abs imm
appendix a instruction set rev. 3.00 jan 11, 2005 page 999 of 1220 rej09b0186-0300o bhi d:8 bhi d:16 bls d:8 bls d:16 bcc d:8 (bhs d:8) bcc d:16 (bhs d:16) bcs d:8 (blo d:8) bcs d:16 (blo d:16) bne d:8 bne d:16 beq d:8 beq d:16 bvc d:8 bvc d:16 bvs d:8 bvs d:16 bpl d:8 bpl d:16 bmi d:8 bmi d:16 bge d:8 bge d:16 blt d:8 blt d:16 bgt d:8 bgt d:16 ble d:8 ble d:16 mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bcc ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 8 a 8 b 8 c 8 d 8 e 8 f 8 2 3 4 5 6 7 8 9 a b c d e f disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp 0 0 0 0 0 0 0 0 0 0 0 0 0 0
appendix a instruction set rev. 3.00 jan 11, 2005 page 1000 of 1220 rej09b0186-0300o bclr #xx:3,rd bclr #xx:3,@erd bclr #xx:3,@aa:8 bclr #xx:3,@aa:16 bclr #xx:3,@aa:32 bclr rn,rd bclr rn,@erd bclr rn,@aa:8 bclr rn,@aa:16 bclr rn,@aa:32 biand #xx:3,rd biand #xx:3,@erd biand #xx:3,@aa:8 biand #xx:3,@aa:16 biand #xx:3,@aa:32 bild #xx:3,rd bild #xx:3,@erd bild #xx:3,@aa:8 bild #xx:3,@aa:16 bild #xx:3,@aa:32 bior #xx:3,rd bior #xx:3,@erd bior #xx:3,@aa:8 bior #xx:3,@aa:16 bior #xx:3,@aa:32 mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bclr biand bild bior b b b b b b b b b b b b b b b b b b b b b b b b b 0 0 0 1 0 1 0 1 0 imm erd erd imm erd imm erd imm erd 0 1 1 1 imm imm imm imm 0 1 1 1 imm imm imm imm 7 7 7 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 2 d f a a 2 d f a a 6 c e a a 7 c e a a 4 c e a a 1 3 rn 1 3 1 3 1 3 1 3 rd 0 8 8 rd 0 8 8 rd 0 0 0 rd 0 0 0 rd 0 0 0 7 7 6 6 7 7 7 7 7 7 2 2 2 2 6 6 7 7 4 4 rn rn 0 0 0 0 0 0 0 0 0 0 7 6 7 7 7 2 2 6 7 4 rn 0 0 0 0 0 7 6 7 7 7 2 2 6 7 4 rn 0 0 0 0 0 abs abs abs abs abs abs abs abs abs abs abs abs abs abs abs 0 0 1 1 1 1 1 1 imm imm imm imm imm imm imm imm
appendix a instruction set rev. 3.00 jan 11, 2005 page 1001 of 1220 rej09b0186-0300o bist #xx:3,rd bist #xx:3,@erd bist #xx:3,@aa:8 bist #xx:3,@aa:16 bist #xx:3,@aa:32 bixor #xx:3,rd bixor #xx:3,@erd bixor #xx:3,@aa:8 bixor #xx:3,@aa:16 bixor #xx:3,@aa:32 bld #xx:3,rd bld #xx:3,@erd bld #xx:3,@aa:8 bld #xx:3,@aa:16 bld #xx:3,@aa:32 bnot #xx:3,rd bnot #xx:3,@erd bnot #xx:3,@aa:8 bnot #xx:3,@aa:16 bnot #xx:3,@aa:32 bnot rn,rd bnot rn,@erd bnot rn,@aa:8 bnot rn,@aa:16 bnot rn,@aa:32 mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bist bixor bld bnot b b b b b b b b b b b b b b b b b b b b b b b b b 1 0 1 0 0 0 0 0 0 imm erd imm erd imm erd imm erd erd imm imm imm imm imm imm imm imm 1 1 0 0 imm imm imm imm 1 1 0 0 imm imm imm imm 1 1 1 1 0 0 0 0 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 7 d f a a 5 c e a a 7 c e a a 1 d f a a 1 d f a a 1 3 1 3 1 3 1 3 rn 1 3 rd 0 8 8 rd 0 0 0 rd 0 0 0 rd 0 8 8 rd 0 8 8 6 6 7 7 7 7 7 7 6 6 7 7 5 5 7 7 1 1 1 1 rn rn 0 0 0 0 0 0 0 0 0 0 6 7 7 7 6 7 5 7 1 1rn 0 0 0 0 0 6 7 7 7 6 7 5 7 1 1rn 0 0 0 0 0 abs abs abs abs abs abs abs abs abs abs abs abs abs abs abs
appendix a instruction set rev. 3.00 jan 11, 2005 page 1002 of 1220 rej09b0186-0300o bor #xx:3,rd bor #xx:3,@erd bor #xx:3,@aa:8 bor #xx:3,@aa:16 bor #xx:3,@aa:32 bset #xx:3,rd bset #xx:3,@erd bset #xx:3,@aa:8 bset #xx:3,@aa:16 bset #xx:3,@aa:32 bset rn,rd bset rn,@erd bset rn,@aa:8 bset rn,@aa:16 bset rn,@aa:32 bsr d:8 bsr d:16 bst #xx:3,rd bst #xx:3,@erd bst #xx:3,@aa:8 bst #xx:3,@aa:16 bst #xx:3,@aa:32 btst #xx:3,rd btst #xx:3,@erd btst #xx:3,@aa:8 btst #xx:3,@aa:16 btst #xx:3,@aa:32 btst rn,rd btst rn,@erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bor bset bsr bst btst b b b b b b b b b b b b b b b ? ? b b b b b b b b b b b b 0 0 0 0 0 0 0 0 0 0 imm erd imm erd erd imm erd imm erd erd abs abs abs disp abs abs imm imm imm imm imm imm imm imm 0 0 0 0 imm imm imm imm 0 0 0 0 imm imm imm imm 0 0 0 0 0 0 0 0 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 5 5 6 7 7 6 6 7 7 7 6 6 6 7 4 c e a a 0 d f a a 0 d f a a 5 c 7 d f a a 3 c e a a 3 c 1 3 1 3 rn 1 3 0 1 3 1 3 rn rd 0 0 0 rd 0 8 8 rd 0 8 8 0 rd 0 8 8 rd 0 0 0 rd 0 7 7 7 7 6 6 6 6 7 7 6 4 4 0 0 0 0 7 7 3 3 3 rn rn rn 0 0 0 0 0 0 0 0 0 0 0 7 7 6 6 7 4 0 0 7 3 rn 0 0 0 0 0 7 7 6 6 7 4 0 0 7 3 rn 0 0 0 0 0 abs abs abs disp abs abs abs abs abs abs abs
appendix a instruction set rev. 3.00 jan 11, 2005 page 1003 of 1220 rej09b0186-0300o btst rn,@aa:8 btst rn,@aa:16 btst rn,@aa:32 bxor #xx:3,rd bxor #xx:3,@erd bxor #xx:3,@aa:8 bxor #xx:3,@aa:16 bxor #xx:3,@aa:32 clrmac cmp.b #xx:8,rd cmp.b rs,rd cmp.w #xx:16,rd cmp.w rs,rd cmp.l #xx:32,erd cmp.l ers,erd daa rd das rd dec.b rd dec.w #1,rd dec.w #2,rd dec.l #1,erd dec.l #2,erd divxs.b rs,rd divxs.w rs,erd divxu.b rs,rd divxu.w rs,erd eepmov.b eepmov.w mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion btst bxor clrmac cmp daa das dec divxs divxu eepmov b b b b b b b b ? b b w w l l b b b w w l l b w b w ? ? 0 0 1 imm erd ers 0 0 0 0 0 erd erd erd erd erd imm imm 0erd 0imm 0imm 0 0 7 6 6 7 7 7 6 6 0 a 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 e a a 5 c e a a 1 rd c 9 d a f f f a b b b b 1 1 1 3 b b 1 3 1 3 a rs 2 rs 2 0 0 0 5 d 7 f d d rs rs 5 d 0 0 rd 0 0 0 0 rd rd rd rd rd rd rd rd 0 0 rd c 4 6 7 7 5 5 5 5 3 5 5 1 3 9 9 rn rs rs 8 8 0 0 0 rd f f 6 7 3 5 rn 0 0 6 7 3 5 rn 0 0 abs abs imm abs abs imm abs abs imm
appendix a instruction set rev. 3.00 jan 11, 2005 page 1004 of 1220 rej09b0186-0300o exts.w rd exts.l erd extu.w rd extu.l erd inc.b rd inc.w #1,rd inc.w #2,rd inc.l #1,erd inc.l #2,erd jmp @ern jmp @aa:24 jmp @@aa:8 jsr @ern jsr @aa:24 jsr @@aa:8 ldc #xx:8,ccr ldc #xx:8,exr ldc rs,ccr ldc rs,exr ldc @ers,ccr ldc @ers,exr ldc @(d:16,ers),ccr ldc @(d:16,ers),exr ldc @(d:32,ers),ccr ldc @(d:32,ers),exr ldc @ers+,ccr ldc @ers+,exr ldc @aa:16,ccr ldc @aa:16,exr mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion exts extu inc jmp jsr ldc w l w l b w w l l ? ? ? ? ? ? b b b b w w w w w w w w w w 0 0 ern ern 0 0 0 0 erd erd erd erd ers ers ers ers ers ers ers ers 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 5 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 7 7 7 a b b b b 9 a b d e f 7 1 3 3 1 1 1 1 1 1 1 1 1 1 d f 5 7 0 5 d 7 f 4 0 1 4 4 4 4 4 4 4 4 4 4 rd rd rd rd rd 0 0 1 rs rs 0 1 0 1 0 1 0 1 0 1 0 6 6 6 6 7 7 6 6 6 6 7 9 9 f f 8 8 d d b b 0 0 0 0 0 0 0 0 0 0 0 0 6 6 b b 2 2 0 0 abs abs abs abs imm imm disp disp abs abs disp disp
appendix a instruction set rev. 3.00 jan 11, 2005 page 1005 of 1220 rej09b0186-0300o 0 0 rd abs rs rd ldc @aa:32,ccr ldc @aa:32,exr ldm.l @sp+, (ern-ern+1) ldm.l @sp+, (ern-ern+2) ldm.l @sp+, (ern-ern+3) ldmac ers,mach ldmac ers,macl mac @ern+,@erm+ mov.b #xx:8,rd mov.b rs,rd mov.b @ers,rd mov.b @(d:16,ers),rd mov.b @(d:32,ers),rd mov.b @ers+,rd mov.b @aa:8,rd mov.b @aa:16,rd mov.b @aa:32,rd mov.b rs,@erd mov.b rs,@(d:16,erd) mov.b rs,@(d:32,erd) mov.b rs,@-erd mov.b rs,@aa:8 mov.b rs,@aa :16 mov.b rs,@aa:32 mov.w #xx:16,rd mov.w rs,rd mov.w @ers,rd mov.w @(d:16,ers),rd mov.w @(d:32,ers),rd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion ldc ldm * 3 ldmac mac mov w w l l l l l ? b b b b b b b b b b b b b b b b w w w w w 0 0 0 0 1 1 0 1 0 0 0 ers ers ers ers erd erd erd erd ers ers ers 0 0 0 ern+1 ern+2 ern+3 0 0 0 0 0 0 0 0 f 0 6 6 7 6 2 6 6 6 6 7 6 3 6 6 7 0 6 6 7 1 1 1 1 1 3 3 1 rd c 8 e 8 c rd a a 8 e 8 c rs a a 9 d 9 f 8 4 4 1 2 3 2 3 6 rs 0 2 8 a 0 rs 0 1 0 0 0 ers ers 0 rd rd rd 0 rd rd rd rs rs 0 rs rs rs rd rd rd rd 0 6 6 6 6 6 6 6 6 6 b b d d d d a a b 2 2 7 7 7 2 a 2 imm abs abs disp abs disp abs imm disp abs abs abs abs disp disp disp 0 0 0 em 0 em
appendix a instruction set rev. 3.00 jan 11, 2005 page 1006 of 1220 rej09b0186-0300o mov.w @ers+,rd mov.w @aa:16,rd mov.w @aa:32,rd mov.w rs,@erd mov.w rs,@(d:16,erd) mov.w rs,@(d:32,erd) mov.w rs,@-erd mov.w rs,@aa:16 mov.w rs,@aa:32 mov.l #xx:32,erd mov.l ers,erd mov.l @ers,erd mov.l @(d:16,ers),erd mov.l @(d:32,ers),erd mov.l @ers+,erd mov.l @aa:16 ,erd mov.l @aa:32 ,erd mov.l ers,@erd mov.l ers,@(d:16,erd) mov.l ers,@(d:32,erd) * 1 mov.l ers,@-erd mov.l ers,@aa:16 mov.l ers,@aa:32 movfpe @aa:16,rd movtpe rs,@aa:16 mulxs.b rs,rd mulxs.w rs,erd mulxu.b rs,rd mulxu.w rs,erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion mov movfpe movtpe mulxs mulxu w w w w w w w w w l l l l l l l l l l l l l l b b b w b w 0 1 1 0 1 1 ers erd erd erd erd ers 0 0 0 erd erd erd ers ers ers ers erd erd erd erd 0 0 0 0 0 0 0 0 0 0 0 erd erd erd erd erd ers ers ers ers ers erd 0 0 erd ers 0 0 0 0 1 1 0 1 6 6 6 6 6 7 6 6 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 5 d b b 9 f 8 d b b a f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 2 0 2 8 a 0 0 0 0 0 0 0 0 0 0 0 0 0 c c rs rs rd rd rd rs rs 0 rs rs rs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd 6 6 6 7 6 6 6 6 6 7 6 6 6 5 5 b 9 f 8 d b b 9 f 8 d b b 0 2 a 0 2 8 a rs rs rs 0 0 rd 6 6 b b 2 a abs disp abs abs abs imm disp abs disp abs disp abs abs cannot be used in the h8s/2643 group disp disp
appendix a instruction set rev. 3.00 jan 11, 2005 page 1007 of 1220 rej09b0186-0300o neg.b rd neg.w rd neg.l erd nop not.b rd not.w rd not.l erd or.b #xx:8,rd or.b rs,rd or.w #xx:16,rd or.w rs,rd or.l #xx:32,erd or.l ers,erd orc #xx:8,ccr orc #xx:8,exr pop.w rn pop.l ern push.w rn push.l ern rotl.b rd rotl.b #2, rd rotl.w rd rotl.w #2, rd rotl.l erd rotl.l #2, erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion neg nop not or orc pop push rotl b w l ? b w l b b w w l l b b w l w l b b w w l l 0 0 0 0 0 erd erd erd erd erd 1 1 1 0 1 1 1 c 1 7 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 7 7 7 0 7 7 7 rd 4 9 4 a 1 4 1 d 1 d 1 2 2 2 2 2 2 8 9 b 0 0 1 3 rs 4 rs 4 f 4 7 0 f 0 8 c 9 d b f rd rd 0 rd rd rd rd rd 0 1 rn 0 rn 0 rd rd rd rd imm imm 6 0 6 6 4 4 d d ers 0 0 0 erd ern ern 0 7 f imm imm imm
appendix a instruction set rev. 3.00 jan 11, 2005 page 1008 of 1220 rej09b0186-0300o rotr.b rd rotr.b #2, rd rotr.w rd rotr.w #2, rd rotr.l erd rotr.l #2, erd rotxl.b rd rotxl.b #2, rd rotxl.w rd rotxl.w #2, rd rotxl.l erd rotxl.l #2, erd rotxr.b rd rotxr.b #2, rd rotxr.w rd rotxr.w #2, rd rotxr.l erd rotxr.l #2, erd rte rts shal.b rd shal.b #2, rd shal.w rd shal.w #2, rd shal.l erd shal.l #2, erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion rotr rotxl rotxr rte rts shal b b w w l l b b w w l l b b w w l l ? ? b b w w l l 0 0 0 0 0 0 0 0 erd erd erd erd erd erd erd erd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 3 3 3 3 3 3 2 2 2 2 2 2 3 3 3 3 3 3 6 4 0 0 0 0 0 0 8 c 9 d b f 0 4 1 5 3 7 0 4 1 5 3 7 7 7 8 c 9 d b f rd rd rd rd rd rd rd rd rd rd rd rd 0 0 rd rd rd rd
appendix a instruction set rev. 3.00 jan 11, 2005 page 1009 of 1220 rej09b0186-0300o shar.b rd shar.b #2, rd shar.w rd shar.w #2, rd shar.l erd shar.l #2, erd shll.b rd shll.b #2, rd shll.w rd shll.w #2, rd shll.l erd shll.l #2, erd shlr.b rd shlr.b #2, rd shlr.w rd shlr.w #2, rd shlr.l erd shlr.l #2, erd sleep stc.b ccr,rd stc.b exr,rd stc.w ccr,@erd stc.w exr,@erd stc.w ccr,@(d:16,erd) stc.w exr,@(d:16,erd) stc.w ccr,@(d:32,erd) stc.w exr,@(d:32,erd) stc.w ccr,@-erd stc.w exr,@-erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion shar shll shlr sleep stc b b w w l l b b w w l l b b w w l l ? b b w w w w w w w w 0 0 0 0 0 0 erd erd erd erd erd erd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 8 c 9 d b f 0 4 1 5 3 7 0 4 1 5 3 7 8 0 1 4 4 4 4 4 4 4 4 rd rd rd rd rd rd rd rd rd rd rd rd 0 rd rd 0 1 0 1 0 1 0 1 erd erd erd erd erd erd erd erd 1 1 1 1 0 0 1 1 6 6 6 6 7 7 6 6 9 9 f f 8 8 d d 0 0 0 0 0 0 0 0 6 6 b b a a 0 0 disp disp disp disp
appendix a instruction set rev. 3.00 jan 11, 2005 page 1010 of 1220 rej09b0186-0300o stc.w ccr,@aa:16 stc.w exr,@aa:16 stc.w ccr,@aa:32 stc.w exr,@aa:32 stm.l(ern-ern+1), @-sp stm.l (ern-ern+2), @-sp stm.l (ern-ern+3), @-sp stmac mach,erd stmac macl,erd sub.b rs,rd sub.w #xx:16,rd sub.w rs,rd sub.l #xx:32,erd sub.l ers,erd subs #1,erd subs #2,erd subs #4,erd subx #xx:8,rd subx rs,rd tas @erd trapa #x:2 xor.b #xx:8,rd xor.b rs,rd xor.w #xx:16,rd xor.w rs,rd xor.l #xx:32,erd xor.l ers,erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion stc stm * 3 stmac sub subs subx tas * 2 trapa xor w w w w l l l l l b w w l l l l l b b b ? b b w w l l 1 00 ers imm 0 0 0 0 0 0 erd erd erd erd erd erd erd ers 0 0 0 0 ern ern ern erd 0 0 0 0 0 0 0 0 0 0 0 1 7 1 7 1 1 1 1 b 1 0 5 d 1 7 6 7 0 1 1 1 1 1 1 1 2 2 8 9 9 a a b b b rd e 1 7 rd 5 9 5 a 1 4 4 4 4 1 2 3 3 3 rs 3 rs 3 0 8 9 rs e rs 5 rs 5 f 0 1 0 1 0 0 0 rd rd rd rd 0 0 rd rd rd 0 6 6 6 6 6 6 6 7 6 b b b b d d d b 5 8 8 a a f f f 0 0 0 0 c abs abs abs abs imm imm imm imm imm imm 0 ers 0 ers
appendix a instruction set rev. 3.00 jan 11, 2005 page 1011 of 1220 rej09b0186-0300o xorc #xx:8,ccr xorc #xx:8,exr mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion xorc b b 0 0 5 1 4 1 0 5 imm imm notes: 1. 2. 3. bit 7 of the 4th byte of the mov.l ers, @(d:32,erd) instruction can be either 1 or 0. only register er0, er1, er4, or er5 should be used when using the tas instruction. only register er0 to er6 should be used when using the stm/ldm instruction. legend: address register 32-bit register register field general register register field general register register field general register 000 001 111 er0 er1 er7 0000 0001 0111 1000 1001 1111 r0 r1 r7 e0 e1 e7 0000 0001 0111 1000 1001 1111 r0h r1h r7h r0l r1l r7l 16-bit register 8-bit register imm: abs: disp: rs, rd, rn: ers, erd, ern, erm: the register fields specify general registers as follows. immediate data (2, 3, 8, 16, or 32 bits) absolute address (8, 16, 24, or 32 bits) displacement (8, 16, or 32 bits) register field (4 bits specifying an 8-bit or 16-bit register. the symbols rs, rd, and rn correspond to operand symbols rs, rd, and rn.) register field (3 bits specifying an address register or 32-bit register. the symbols ers, erd, ern, and erm correspond to oper and symbols ers, erd, ern, and erm.)
appendix a instruction set rev. 3.00 jan 11, 2005 page 1012 of 1220 rej09b0186-0300o a.3 operation code map table a.3 shows the operation code map. instruction code 1st byte 2nd byte ah al bh bl instruction when most significant bit of bh is 0. instruction when most significant bit of bh is 1. 0 nop bra mulxu bset ah note: * cannot be used in the h8s/2643 group. al 0 1 2 3 4 5 6 7 8 9 a b c d e f 1 brn divxu bnot 2 bhi mulxu bclr 3 bls divxu btst stc stmac ldc ldmac 4 orc or bcc rts or bor bior 6 andc and bne rte and 5 xorc xor bcs bsr xor bxor bixor band biand 7 ldc beq trapa bst bist bld bild 8 bvc mov 9 bvs a bpl jmp b bmi eepmov c bge bsr d blt mov e addx subx bgt jsr f ble mov.b add addx cmp subx or xor and mov add sub mov mov cmp table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(3) table a.3 operation code map (1) **
appendix a instruction set rev. 3.00 jan 11, 2005 page 1013 of 1220 rej09b0186-0300o instruction code 1st byte 2nd byte ah al bh bl 01 0a 0b 0f 10 11 12 13 17 1a 1b 1f 58 6a 79 7a 0 mov inc adds daa dec subs das bra mov mov mov shll shlr rotxl rotxr not 1 ldm brn add add 2 bhi mov cmp cmp 3 stm not bls sub sub 4 shll shlr rotxl rotxr bcc movfpe * or or 5 inc extu dec bcs xor xor 6 mac bne and and 7 inc shll shlr rotxl rotxr extu dec beq ldc stc 8 sleep bvc mov adds shal shar rotl rotr neg subs 9 bvs a clrmac bpl mov b neg bmi add mov sub cmp c shal shar rotl rotr bge movtpe * d inc exts dec blt e tas bgt f inc shal shar rotl rotr exts dec ble bh ah al table a.3(3) table a.3(3) table a.3(3) table a.3(4) table a.3(4) table a.3 operation code map (2) * * note: * cannot be used in the h8s/2643 group.
appendix a instruction set rev. 3.00 jan 11, 2005 page 1014 of 1220 rej09b0186-0300o instruction code 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl r is the register specification field. aa is the absolute address specification. instruction when most significant bit of dh is 0. instruction when most significant bit of dh is 1. notes: ah al bh bl ch cl 01c05 01d05 01f06 7cr06 * 1 7cr07 * 1 7dr06 * 1 7dr07 * 1 7eaa6 * 2 7eaa7 * 2 7faa6 * 2 7faa7 * 2 0 mulxs bset bset bset bset 1 divxs bnot bnot bnot bnot 2 mulxs bclr bclr bclr bclr 3 divxs btst btst btst btst 4 or 5 xor 6 and 789abcdef 1. 2. bor bior bxor bixor band biand bld bild bst bist bor bior bxor bixor band biand bld bild bst bist table a.3 operation code map (3)
appendix a instruction set rev. 3.00 jan 11, 2005 page 1015 of 1220 rej09b0186-0300o instruction code 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl instruction when most significant bit of fh is 0. instruction when most significant bit of fh is 1. 5th byte 6th byte eh el fh fl instruction code 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl instruction when most significant bit of hh is 0. instruction when most significant bit of hh is 1. note: * aa is the absolute address specification. 5th byte 6th byte eh el fh fl 7th byte 8th byte gh gl hh hl 6a10aaaa6 * 6a10aaaa7 * 6a18aaaa6 * 6a18aaaa7 * ahalbhblchcldhdleh el 0 bset 1 bnot 2 bclr 3 btst bor bior bxor bixor band biand bld bild bst bist 456789abcdef 6a30aaaaaaaa6 * 6a30aaaaaaaa7 * 6a38aaaaaaaa6 * 6a38aaaaaaaa7 * ahalbhbl ... fhflgh gl 0 bset 1 bnot 2 bclr 3 btst bor bior bxor bixor band biand bld bild bst bist 456789abcdef table a.3 operation code map (4)
appendix a instruction set rev. 3.00 jan 11, 2005 page 1016 of 1220 rej09b0186-0300o a.4 number of states required for instruction execution the tables in this section can be used to calculate the number of states required for instruction execution by the cpu. table a.5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. table a.4 indicates the number of states required for each cycle. the number of states required for execution of an instruction can be calculated from these two tables as follows: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. bset #0, @ffffc7:8 from table a.5: i = l = 2, j = k = m = n = 0 from table a.4: si = 4, sl = 2 number of states required for execution = 2 4 + 2 2 = 12 2. jsr @@30 from table a.5: i = j = k = 2, l = m = n = 0 from table a.4: si = sj = s k = 4 number of states required for execution = 2 4 + 2 4 + 2 4 = 24
appendix a instruction set rev. 3.00 jan 11, 2005 page 1017 of 1220 rej09b0186-0300o table a.4 number of states per cycle access conditions on-chip supporting external device module 8-bit bus 16-bit bus cycle on-chip memory 8-bit bus 16-bit bus 2-state access 3-state access 2-state access 3-state access instruction fetch s i 1 4 2 4 6 + 2m 2 3 + m branch address read s j stack operation s k byte data access s l 223 + m word data access s m 4 4 6 + 2m internal operation s n 11 1 1111 legend: m: number of wait states inserted into external device access
appendix a instruction set rev. 3.00 jan 11, 2005 page 1018 of 1220 rej09b0186-0300o table a.5 number of cycles in instruction execution instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n add add.b #xx:8,rd 1 add.b rs,rd 1 add.w #xx:16,rd 2 add.w rs,rd 1 add.l #xx:32,erd 3 add.l ers,erd 1 adds adds #1/2/4,erd 1 addx addx #xx:8,rd 1 addx rs,rd 1 and and.b #xx:8,rd 1 and.b rs,rd 1 and.w #xx:16,rd 2 and.w rs,rd 1 and.l #xx:32,erd 3 and.l ers,erd 2 andc andc #xx:8,ccr 1 andc #xx:8,exr 2 band band #xx:3,rd 1 band #xx:3,@erd 2 1 band #xx:3,@aa:8 2 1 band #xx:3,@aa:16 3 1 band #xx:3,@aa:32 4 1 bcc bra d:8 (bt d:8) 2 brn d:8 (bf d:8) 2 bhi d:8 2 bls d:8 2 bcc d:8 (bhs d:8) 2 bcs d:8 (blo d:8) 2 bne d:8 2 beq d:8 2 bvc d:8 2 bvs d:8 2
appendix a instruction set rev. 3.00 jan 11, 2005 page 1019 of 1220 rej09b0186-0300o instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n bcc bpl d:8 2 bmi d:8 2 bge d:8 2 blt d:8 2 bgt d:8 2 ble d:8 2 bra d:16 (bt d:16) 2 1 brn d:16 (bf d:16) 2 1 bhi d:16 2 1 bls d:16 2 1 bcc d:16 (bhs d:16) 2 1 bcs d:16 (blo d:16) 2 1 bne d:16 2 1 beq d:16 2 1 bvc d:16 2 1 bvs d:16 2 1 bpl d:16 2 1 bmi d:16 2 1 bge d:16 2 1 blt d:16 2 1 bgt d:16 2 1 ble d:16 2 1 bclr bclr #xx:3,rd 1 bclr #xx:3,@erd 2 2 bclr #xx:3,@aa:8 2 2 bclr #xx:3,@aa:16 3 2 bclr #xx:3,@aa:32 4 2 bclr rn,rd 1 bclr rn,@erd 2 2 bclr rn,@aa:8 2 2 bclr rn,@aa:16 3 2 bclr rn,@aa:32 4 2
appendix a instruction set rev. 3.00 jan 11, 2005 page 1020 of 1220 rej09b0186-0300o instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n biand biand #xx:3,rd 1 biand #xx:3,@erd 2 1 biand #xx:3,@aa:8 2 1 biand #xx:3,@aa:16 3 1 biand #xx:3,@aa:32 4 1 bild bild #xx:3,rd 1 bild #xx:3,@erd 2 1 bild #xx:3,@aa:8 2 1 bild #xx:3,@aa:16 3 1 bild #xx:3,@aa:32 4 1 bior bior #xx:8,rd 1 bior #xx:8,@erd 2 1 bior #xx:8,@aa:8 2 1 bior #xx:8,@aa:16 3 1 bior #xx:8,@aa:32 4 1 bist bist #xx:3,rd 1 bist #xx:3,@erd 2 2 bist #xx:3,@aa:8 2 2 bist #xx:3,@aa:16 3 2 bist #xx:3,@aa:32 4 2 bixor bixor #xx:3,rd 1 bixor #xx:3,@erd 2 1 bixor #xx:3,@aa:8 2 1 bixor #xx:3,@aa:16 3 1 bixor #xx:3,@aa:32 4 1 bld bld #xx:3,rd 1 bld #xx:3,@erd 2 1 bld #xx:3,@aa:8 2 1 bld #xx:3,@aa:16 3 1 bld #xx:3,@aa:32 4 1
appendix a instruction set rev. 3.00 jan 11, 2005 page 1021 of 1220 rej09b0186-0300o instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n bnot bnot #xx:3,rd 1 bnot #xx:3,@erd 2 2 bnot #xx:3,@aa:8 2 2 bnot #xx:3,@aa:16 3 2 bnot #xx:3,@aa:32 4 2 bnot rn,rd 1 bnot rn,@erd 2 2 bnot rn,@aa:8 2 2 bnot rn,@aa:16 3 2 bnot rn,@aa:32 4 2 bor bor #xx:3,rd 1 bor #xx:3,@erd 2 1 bor #xx:3,@aa:8 2 1 bor #xx:3,@aa:16 3 1 bor #xx:3,@aa:32 4 1 bset bset #xx:3,rd 1 bset #xx:3,@erd 2 2 bset #xx:3,@aa:8 2 2 bset #xx:3,@aa:16 3 2 bset #xx:3,@aa:32 4 2 bset rn,rd 1 bset rn,@erd 2 2 bset rn,@aa:8 2 2 bset rn,@aa:16 3 2 bset rn,@aa:32 4 2 bsr bsr d:8 2 2 bsr d:16 2 2 1 bst bst #xx:3,rd 1 bst #xx:3,@erd 2 2 bst #xx:3,@aa:8 2 2 bst #xx:3,@aa:16 3 2 bst #xx:3,@aa:32 4 2
appendix a instruction set rev. 3.00 jan 11, 2005 page 1022 of 1220 rej09b0186-0300o instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n btst btst #xx:3,rd 1 btst #xx:3,@erd 2 1 btst #xx:3,@aa:8 2 1 btst #xx:3,@aa:16 3 1 btst #xx:3,@aa:32 4 1 btst rn,rd 1 btst rn,@erd 2 1 btst rn,@aa:8 2 1 btst rn,@aa:16 3 1 btst rn,@aa:32 4 1 bxor bxor #xx:3,rd 1 bxor #xx:3,@erd 2 1 bxor #xx:3,@aa:8 2 1 bxor #xx:3,@aa:16 3 1 bxor #xx:3,@aa:32 4 1 clrmac clrmac 1 1 * 3 cmp cmp.b #xx:8,rd 1 cmp.b rs,rd 1 cmp.w #xx:16,rd 2 cmp.w rs,rd 1 cmp.l #xx:32,erd 3 cmp.l ers,erd 1 daa daa rd 1 das das rd 1 dec dec.b rd 1 dec.w #1/2,rd 1 dec.l #1/2,erd 1 divxs divxs.b rs,rd 2 11 divxs.w rs,erd 2 19 divxu divxu.b rs,rd 1 11 divxu.w rs,erd 1 19
appendix a instruction set rev. 3.00 jan 11, 2005 page 1023 of 1220 rej09b0186-0300o instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n eepmov eepmov.b 2 2n + 2 * 2 eepmov.w 2 2n + 2 * 2 exts exts.w rd 1 exts.l erd 1 extu extu.w rd 1 extu.l erd 1 inc inc.b rd 1 inc.w #1/2,rd 1 inc.l #1/2,erd 1 jmp jmp @ern 2 jmp @aa:24 2 1 jmp @@aa:8 2 2 1 jsr jsr @ern 2 2 jsr @aa:24 2 2 1 jsr @@aa:8 2 2 2 ldc ldc #xx:8,ccr 1 ldc #xx:8,exr 2 ldc rs,ccr 1 ldc rs,exr 1 ldc @ers,ccr 2 1 ldc @ers,exr 2 1 ldc @(d:16,ers),ccr 3 1 ldc @(d:16,ers),exr 3 1 ldc @(d:32,ers),ccr 5 1 ldc @(d:32,ers),exr 5 1 ldc @ers+,ccr 2 1 1 ldc @ers+,exr 2 1 1 ldc @aa:16,ccr 3 1 ldc @aa:16,exr 3 1 ldc @aa:32,ccr 4 1 ldc @aa:32,exr 4 1
appendix a instruction set rev. 3.00 jan 11, 2005 page 1024 of 1220 rej09b0186-0300o instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n ldm * 5 ldm.l @sp+, (ern-ern+1) 24 1 ldm.l @sp+, (ern-ern+2) 26 1 ldm.l @sp+, (ern-ern+3) 28 1 ldmac ldmac ers,mach 1 1 * 3 ldmac ers,macl 1 1 * 3 mac mac @ern+,@erm+ 2 2 mov mov.b #xx:8,rd 1 mov.b rs,rd 1 mov.b @ers,rd 1 1 mov.b @(d:16,ers),rd 2 1 mov.b @(d:32,ers),rd 4 1 mov.b @ers+,rd 1 1 1 mov.b @aa:8,rd 1 1 mov.b @aa:16,rd 2 1 mov.b @aa:32,rd 3 1 mov.b rs,@erd 1 1 mov.b rs,@(d:16,erd) 2 1 mov.b rs,@(d:32,erd) 4 1 mov.b rs,@-erd 1 1 1 mov.b rs,@aa:8 1 1 mov.b rs,@aa:16 2 1 mov.b rs,@aa:32 3 1 mov.w #xx:16,rd 2 mov.w rs,rd 1 mov.w @ers,rd 1 1 mov.w @(d:16,ers),rd 2 1 mov.w @(d:32,ers),rd 4 1 mov.w @ers+,rd 1 1 1 mov.w @aa:16,rd 2 1 mov.w @aa:32,rd 3 1 mov.w rs,@erd 1 1
appendix a instruction set rev. 3.00 jan 11, 2005 page 1025 of 1220 rej09b0186-0300o instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n mov mov.w rs,@(d:16,erd) 2 1 mov.w rs,@(d:32,erd) 4 1 mov.w rs,@-erd 1 1 1 mov.w rs,@aa:16 2 1 mov.w rs,@aa:32 3 1 mov.l #xx:32,erd 3 mov.l ers,erd 1 mov.l @ers,erd 2 2 mov.l @(d:16,ers),erd 3 2 mov.l @(d:32,ers),erd 5 2 mov.l @ers+,erd 2 2 1 mov.l @aa:16,erd 3 2 mov.l @aa:32,erd 4 2 mov.l ers,@erd 2 2 mov.l ers,@(d:16,erd) 3 2 mov.l ers,@(d:32,erd) 5 2 mov.l ers,@-erd 2 2 1 mov.l ers,@aa:16 3 2 mov.l ers,@aa:32 4 2 movfpe movfpe @:aa:16,rd can not be used in the h8s/2643 group movtpe movtpe rs,@:aa:16 mulxs mulxs.b rs,rd 2 2 * 3 mulxs.w rs,erd 2 3 * 3 mulxu mulxu.b rs,rd 1 2 * 3 mulxu.w rs,erd 1 3 * 3 neg neg.b rd 1 neg.w rd 1 neg.l erd 1 nop nop 1 not not.b rd 1 not.w rd 1 not.l erd 1
appendix a instruction set rev. 3.00 jan 11, 2005 page 1026 of 1220 rej09b0186-0300o instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n or or.b #xx:8,rd 1 or.b rs,rd 1 or.w #xx:16,rd 2 or.w rs,rd 1 or.l #xx:32,erd 3 or.l ers,erd 2 orc orc #xx:8,ccr 1 orc #xx:8,exr 2 pop pop.w rn 1 1 1 pop.l ern 2 2 1 push push.w rn 1 1 1 push.l ern 2 2 1 rotl rotl.b rd 1 rotl.b #2,rd 1 rotl.w rd 1 rotl.w #2,rd 1 rotl.l erd 1 rotl.l #2,erd 1 rotr rotr.b rd 1 rotr.b #2,rd 1 rotr.w rd 1 rotr.w #2,rd 1 rotr.l erd 1 rotr.l #2,erd 1 rotxl rotxl.b rd 1 rotxl.b #2,rd 1 rotxl.w rd 1 rotxl.w #2,rd 1 rotxl.l erd 1 rotxl.l #2,erd 1
appendix a instruction set rev. 3.00 jan 11, 2005 page 1027 of 1220 rej09b0186-0300o instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n rotxr rotxr.b rd 1 rotxr.b #2,rd 1 rotxr.w rd 1 rotxr.w #2,rd 1 rotxr.l erd 1 rotxr.l #2,erd 1 rte rte 2 2/3 * 1 1 rts rts 2 2 1 shal shal.b rd 1 shal.b #2,rd 1 shal.w rd 1 shal.w #2,rd 1 shal.l erd 1 shal.l #2,erd 1 shar shar.b rd 1 shar.b #2,rd 1 shar.w rd 1 shar.w #2,rd 1 shar.l erd 1 shar.l #2,erd 1 shll shll.b rd 1 shll.b #2,rd 1 shll.w rd 1 shll.w #2,rd 1 shll.l erd 1 shll.l #2,erd 1 shlr shlr.b rd 1 shlr.b #2,rd 1 shlr.w rd 1 shlr.w #2,rd 1 shlr.l erd 1 shlr.l #2,erd 1 sleep sleep 1 1
appendix a instruction set rev. 3.00 jan 11, 2005 page 1028 of 1220 rej09b0186-0300o instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n stc stc.b ccr,rd 1 stc.b exr,rd 1 stc.w ccr,@erd 2 1 stc.w exr,@erd 2 1 stc.w ccr,@(d:16,erd) 3 1 stc.w exr,@(d:16,erd) 3 1 stc.w ccr,@(d:32,erd) 5 1 stc.w exr,@(d:32,erd) 5 1 stc.w ccr,@-erd 2 1 1 stc.w exr,@-erd 2 1 1 stc.w ccr,@aa:16 3 1 stc.w exr,@aa:16 3 1 stc.w ccr,@aa:32 4 1 stc.w exr,@aa:32 4 1 stm * 5 stm.l (ern-ern+1), @-sp 24 1 stm.l (ern-ern+2), @-sp 26 1 stm.l (ern-ern+3), @-sp 28 1 stmac stmac mach,erd 1 * 3 stmac macl,erd 1 * 3 sub sub.b rs,rd 1 sub.w #xx:16,rd 2 sub.w rs,rd 1 sub.l #xx:32,erd 3 sub.l ers,erd 1 subs subs #1/2/4,erd 1 subx subx #xx:8,rd 1 subx rs,rd 1 tas * 4 tas @erd 2 2 trapa trapa #x:2 2 2 2/3 * 1 2
appendix a instruction set rev. 3.00 jan 11, 2005 page 1029 of 1220 rej09b0186-0300o instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n xor xor.b #xx:8,rd 1 xor.b rs,rd 1 xor.w #xx:16,rd 2 xor.w rs,rd 1 xor.l #xx:32,erd 3 xor.l ers,erd 2 xorc xorc #xx:8,ccr 1 xorc #xx:8,exr 2 notes: 1. 2 when exr is invalid, 3 when exr is valid. 2. when n bytes of data are transferred. 3. an internal operation may require between 0 and 3 additional states, depending on the preceding instruction. 4. only register er0, er1, er4, or er5 should be used when using the tas instruction. 5. only register er0 to er6 should be used when using the stm/ldm instruction.
appendix a instruction set rev. 3.00 jan 11, 2005 page 1030 of 1220 rej09b0186-0300o a.5 bus states during instruction execution table a.6 indicates the types of cycles that occur during instruction execution by the cpu. see table a.4 for the number of states per cycle. how to read the table: instruction jmp@aa:24 r:w 2nd internal operation, 1 state r:w ea 1 2345678 end of instruction order of execution read effective address (word-size read) no read or write read 2nd word of current instruction (word-size read) legend r:b byte-size read r:w word-size read w:b byte-size write w:w word-size write :m transfer of the bus is not performed immediately after this cycle 2nd address of 2nd word (3rd and 4th bytes) 3rd address of 3rd word (5th and 6th bytes) 4th address of 4th word (7th and 8th bytes) 5th address of 5th word (9th and 10th bytes) next address of next instruction ea effective address vec vector address
appendix a instruction set rev. 3.00 jan 11, 2005 page 1031 of 1220 rej09b0186-0300o figure a.1 shows timing waveforms for the address bus and the rd , hwr , and lwr signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. address bus rd hwr , lwr r:w 2nd fetching 2nd byte of instruction at jump address fetching 1nd byte of instruction at jump address fetching 4th byte of instruction fetching 3rd byte of instruction r:w ea high level internal operation figure a.1 address bus, rd , hwr , and lwr timing (8-bit bus, three-state access, no wait states)
appendix a instruction set rev. 3.00 jan 11, 2005 page 1032 of 1220 rej09b0186-0300o instruction add.b #xx:8,rd r:w next add.b rs,rd r:w next add.w #xx:16,rd r:w 2nd r:w next add.w rs,rd r:w next add.l #xx:32,erd r:w 2nd r:w 3rd r:w next add.l ers,erd r:w next adds #1/2/4,erd r:w next addx #xx:8,rd r:w next addx rs,rd r:w next and.b #xx:8,rd r:w next and.b rs,rd r:w next and.w #xx:16,rd r:w 2nd r:w next and.w rs,rd r:w next and.l #xx:32,erd r:w 2nd r:w 3rd r:w next and.l ers,erd r:w 2nd r:w next andc #xx:8,ccr r:w next andc #xx:8,exr r:w 2nd r:w next band #xx:3,rd r:w next band #xx:3,@erd r:w 2nd r:b ea r:w:m next band #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next band #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next band #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bra d:8 (bt d:8) r:w next r:w ea brn d:8 (bf d:8) r:w next r:w ea bhi d:8 r:w next r:w ea bls d:8 r:w next r:w ea bcc d:8 (bhs d:8) r:w next r:w ea bcs d:8 (blo d:8) r:w next r:w ea bne d:8 r:w next r:w ea beq d:8 r:w next r:w ea bvc d:8 r:w next r:w ea bvs d:8 r:w next r:w ea bpl d:8 r:w next r:w ea bmi d:8 r:w next r:w ea bge d:8 r:w next r:w ea blt d:8 r:w next r:w ea bgt d:8 r:w next r:w ea 1 2 3 4 5 6 7 8 9 table a.6 instruction execution cycles
appendix a instruction set rev. 3.00 jan 11, 2005 page 1033 of 1220 rej09b0186-0300o instruction ble d:8 r:w next r:w ea bra d:16 (bt d:16) r:w 2nd internal operation, r:w ea 1 state brn d:16 (bf d:16) r:w 2nd internal operation, r:w ea 1 state bhi d:16 r:w 2nd internal operation, r:w ea 1 state bls d:16 r:w 2nd internal operation, r:w ea 1 state bcc d:16 (bhs d:16) r:w 2nd internal operation, r:w ea 1 state bcs d:16 (blo d:16) r:w 2nd internal operation, r:w ea 1 state bne d:16 r:w 2nd internal operation, r:w ea 1 state beq d:16 r:w 2nd internal operation, r:w ea 1 state bvc d:16 r:w 2nd internal operation, r:w ea 1 state bvs d:16 r:w 2nd internal operation, r:w ea 1 state bpl d:16 r:w 2nd internal operation, r:w ea 1 state bmi d:16 r:w 2nd internal operation, r:w ea 1 state bge d:16 r:w 2nd internal operation, r:w ea 1 state blt d:16 r:w 2nd internal operation, r:w ea 1 state bgt d:16 r:w 2nd internal operation, r:w ea 1 state ble d:16 r:w 2nd internal operation, r:w ea 1 state bclr #xx:3,rd r:w next bclr #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bclr #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bclr #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea 1 2 3 4 5 6 7 8 9
appendix a instruction set rev. 3.00 jan 11, 2005 page 1034 of 1220 rej09b0186-0300o instruction bclr #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bclr rn,rd r:w next bclr rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bclr rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bclr rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bclr rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea biand #xx:3,rd r:w next biand #xx:3,@erd r:w 2nd r:b ea r:w:m next biand #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next biand #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next biand #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bild #xx:3,rd r:w next bild #xx:3,@erd r:w 2nd r:b ea r:w:m next bild #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bild #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bild #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bior #xx:3,rd r:w next bior #xx:3,@erd r:w 2nd r:b ea r:w:m next bior #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bior #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bior #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bist #xx:3,rd r:w next bist #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bixor #xx:3,rd r:w next bixor #xx:3,@erd r:w 2nd r:b ea r:w:m next bixor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bixor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bixor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bld #xx:3,rd r:w next bld #xx:3,@erd r:w 2nd r:b ea r:w:m next bld #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bld #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bld #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bnot #xx:3,rd r:w next 1 2 3 4 5 6 7 8 9
appendix a instruction set rev. 3.00 jan 11, 2005 page 1035 of 1220 rej09b0186-0300o instruction bnot #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bnot rn,rd r:w next bnot rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bnot rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bnot rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bnot rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bor #xx:3,rd r:w next bor #xx:3,@erd r:w 2nd r:b ea r:w:m next bor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bset #xx:3,rd r:w next bset #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bset rn,rd r:w next bset rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bset rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bset rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bset rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bsr d:8 r:w next r:w ea w:w :m stack (h) w:w stack (l) bsr d:16 r:w 2nd internal operation, r:w ea w:w :m stack (h) w:w stack (l) 1 state bst #xx:3,rd r:w next bst #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea btst #xx:3,rd r:w next btst #xx:3,@erd r:w 2nd r:b ea r:w:m next 1 2 3 4 5 6 7 8 9
appendix a instruction set rev. 3.00 jan 11, 2005 page 1036 of 1220 rej09b0186-0300o instruction 1 2 3 4 5 6 7 8 9 btst #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next btst #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next btst #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next btst rn,rd r:w next btst rn,@erd r:w 2nd r:b ea r:w:m next btst rn,@aa:8 r:w 2nd r:b ea r:w:m next btst rn,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next btst rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bxor #xx:3,rd r:w next bxor #xx:3,@erd r:w 2nd r:b ea r:w:m next bxor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bxor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bxor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next clrmac r:w next internal operation, 1 state cmp.b #xx:8,rd r:w next cmp.b rs,rd r:w next cmp.w #xx:16,rd r:w 2nd r:w next cmp.w rs,rd r:w next cmp.l #xx:32,erd r:w 2nd r:w 3rd r:w next cmp.l ers,erd r:w next daa rd r:w next das rd r:w next dec.b rd r:w next dec.w #1/2,rd r:w next dec.l #1/2,erd r:w next divxs.b rs,rd r:w 2nd r:w next internal operation, 11 states divxs.w rs,erd r:w 2nd r:w next internal operation, 19 states divxu.b rs,rd r:w next internal operation, 11 states divxu.w rs,erd r:w next internal operation, 19 states eepmov.b r:w 2nd r:b eas * 1 r:b ead * 1 r:b eas * 2 w:b ead * 2 r:w next eepmov.w r:w 2nd r:b eas * 1 r:b ead * 1 r:b eas * 2 w:b ead * 2 r:w next exts.w rd r:w next repeated n times * 2 exts.l erd r:w next extu.w rd r:w next extu.l erd r:w next inc.b rd r:w next
appendix a instruction set rev. 3.00 jan 11, 2005 page 1037 of 1220 rej09b0186-0300o instruction inc.w #1/2,rd r:w next inc.l #1/2,erd r:w next jmp @ern r:w next r:w ea jmp @aa:24 r:w 2nd internal operation, r:w ea 1 state jmp @@aa:8 r:w next r:w:m aa:8 r:w aa:8 internal operation, r:w ea 1 state jsr @ern r:w next r:w ea w:w :m stack (h) w:w stack (l) jsr @aa:24 r:w 2nd internal operation, r:w ea w:w :m stack (h) w:w stack (l) 1 state jsr @@aa:8 r:w next r:w:m aa:8 r:w aa:8 w:w :m stack (h) w:w stack (l) r:w ea ldc #xx:8,ccr r:w next ldc #xx:8,exr r:w 2nd r:w next ldc rs,ccr r:w next ldc rs,exr r:w next ldc @ers,ccr r:w 2nd r:w next r:w ea ldc @ers,exr r:w 2nd r:w next r:w ea ldc @(d:16,ers),ccr r:w 2nd r:w 3rd r:w next r:w ea ldc @(d:16,ers),exr r:w 2nd r:w 3rd r:w next r:w ea ldc @(d:32,ers),ccr r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next r:w ea ldc @(d:32,ers),exr r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next r:w ea ldc @ers+,ccr r:w 2nd r:w next internal operation, r:w ea 1 state ldc @ers+,exr r:w 2nd r:w next internal operation, r:w ea 1 state ldc @aa:16,ccr r:w 2nd r:w 3rd r:w next r:w ea ldc @aa:16,exr r:w 2nd r:w 3rd r:w next r:w ea ldc @aa:32,ccr r:w 2nd r:w 3rd r:w 4th r:w next r:w ea ldc @aa:32,exr r:w 2nd r:w 3rd r:w 4th r:w next r:w ea ldm.l @sp+, r:w 2nd r:w:m next internal operation, r:w:m stack (h) * 3 r:w stack (l) * 3 (ern ? ern+1) * 9 1 state ldm.l @sp+,(ern ? ern+2) * 9 r:w 2nd r:w next internal operation, r:w:m stack (h) * 3 r:w stack (l) * 3 1 state ldm.l @sp+,(ern ? ern+3) * 9 r:w 2nd r:w next internal operation, r:w:m stack (h) * 3 r:w stack (l) * 3 1 state ldmac ers,mach r:w next internal operation, repeated n times * 3 1 state 1 2 3 4 5 6 7 8 9
appendix a instruction set rev. 3.00 jan 11, 2005 page 1038 of 1220 rej09b0186-0300o instruction ldmac ers,macl r:w next internal operation, 1 state mac @ern+,@erm+ r:w 2nd r:w next r:w eah r:w eam mov.b #xx:8,rd r:w next mov.b rs,rd r:w next mov.b @ers,rd r:w next r:b ea mov.b @(d:16,ers),rd r:w 2nd r:w next r:b ea mov.b @(d:32,ers),rd r:w 2nd r:w 3rd r:w 4th r:w next r:b ea mov.b @ers+,rd r:w next internal operation, r:b ea 1 state mov.b @aa:8,rd r:w next r:b ea mov.b @aa:16,rd r:w 2nd r:w next r:b ea mov.b @aa:32,rd r:w 2nd r:w 3rd r:w next r:b ea mov.b rs,@erd r:w next w:b ea mov.b rs,@(d:16,erd) r:w 2nd r:w next w:b ea mov.b rs,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w next w:b ea mov.b rs,@ ? erd r:w next internal operation, w:b ea 1 state mov.b rs,@aa:8 r:w next w:b ea mov.b rs,@aa:16 r:w 2nd r:w next w:b ea mov.b rs,@aa:32 r:w 2nd r:w 3rd r:w next w:b ea mov.w #xx:16,rd r:w 2nd r:w next mov.w rs,rd r:w next mov.w @ers,rd r:w next r:w ea mov.w @(d:16,ers),rd r:w 2nd r:w next r:w ea mov.w @(d:32,ers),rd r:w 2nd r:w 3rd r:w 4th r:w next r:w ea mov.w @ers+, rd r:w next internal operation, r:w ea 1 state mov.w @aa:16,rd r:w 2nd r:w next r:w ea mov.w @aa:32,rd r:w 2nd r:w 3rd r:w next r:b ea mov.w rs,@erd r:w next w:w ea mov.w rs,@(d:16,erd) r:w 2nd r:w next w:w ea mov.w rs,@(d:32,erd) r:w 2nd r:w 3rd r:e 4th r:w next w:w ea mov.w rs,@ ? erd r:w next internal operation, w:w ea 1 state mov.w rs,@aa:16 r:w 2nd r:w next w:w ea mov.w rs,@aa:32 r:w 2nd r:w 3rd r:w next w:w ea 1 2 3 4 5 6 7 8 9
appendix a instruction set rev. 3.00 jan 11, 2005 page 1039 of 1220 rej09b0186-0300o instruction 1 2 3 4 5 6 7 8 9 mov.l #xx:32,erd r:w 2nd r:w 3rd r:w next mov.l ers,erd r:w next mov.l @ers,erd r:w 2nd r:w:m next r:w:m ea r:w ea+2 mov.l @(d:16,ers),erd r:w 2nd r:w:m 3rd r:w next r:w:m ea r:w ea+2 mov.l @(d:32,ers),erd r:w 2nd r:w:m 3rd r:w:m 4th r:w 5th r:w next r:w:m ea r:w ea+2 mov.l @ers+,erd r:w 2nd r:w:m next internal operation, r:w:m ea r:w ea+2 1 state mov.l @aa:16,erd r:w 2nd r:w:m 3rd r:w next r:w:m ea r:w ea+2 mov.l @aa:32,erd r:w 2nd r:w:m 3rd r:w 4th r:w next r:w:m ea r:w ea+2 mov.l ers,@erd r:w 2nd r:w:m next w:w:m ea w:w ea+2 mov.l ers,@(d:16,erd) r:w 2nd r:w:m 3rd r:w next w:w:m ea w:w ea+2 mov.l ers,@(d:32,erd) r:w 2nd r:w:m 3rd r:w:m 4th r:w 5th r:w next w:w:m ea w:w ea+2 mov.l ers,@ ? erd r:w 2nd r:w:m next internal operation, w:w:m ea w:w ea+2 1 state mov.l ers,@aa:16 r:w 2nd r:w:m 3rd r:w next w:w:m ea w:w ea+2 mov.l ers,@aa:32 r:w 2nd r:w:m 3rd r:w 4th r:w next w:w:m ea w:w ea+2 movfpe @aa:16,rd cannot be used in the h8s/2643 group movtpe rs,@aa:16 mulxs.b rs,rd r:w 2nd r:w next internal operation, 2 states mulxs.w rs,erd r:w 2nd r:w next internal operation, 3 states mulxu.b rs,rd r:w next internal operation, 2 states mulxu.w rs,erd r:w next internal operation, 3 states neg.b rd r:w next neg.w rd r:w next neg.l erd r:w next nop r:w next not.b rd r:w next not.w rd r:w next not.l erd r:w next or.b #xx:8,rd r:w next or.b rs,rd r:w next or.w #xx:16,rd r:w 2nd r:w next or.w rs,rd r:w next or.l #xx:32,erd r:w 2nd r:w 3rd r:w next or.l ers,erd r:w 2nd r:w next orc #xx:8,ccr r:w next orc #xx:8,exr r:w 2nd r:w next
appendix a instruction set rev. 3.00 jan 11, 2005 page 1040 of 1220 rej09b0186-0300o instruction pop.w rn r:w next internal operation, r:w ea 1 state pop.l ern r:w 2nd r:w:m next internal operation, r:w:m ea r:w ea+2 1 state push.w rn r:w next internal operation, w:w ea 1 state push.l ern r:w 2nd r:w:m next internal operation, w:w:m ea w:w ea+2 1 state rotl.b rd r:w next rotl.b #2,rd r:w next rotl.w rd r:w next rotl.w #2,rd r:w next rotl.l erd r:w next rotl.l #2,erd r:w next rotr.b rd r:w next rotr.b #2,rd r:w next rotr.w rd r:w next rotr.w #2,rd r:w next rotr.l erd r:w next rotr.l #2,erd r:w next rotxl.b rd r:w next rotxl.b #2,rd r:w next rotxl.w rd r:w next rotxl.w #2,rd r:w next rotxl.l erd r:w next rotxl.l #2,erd r:w next rotxr.b rd r:w next rotxr.b #2,rd r:w next rotxr.w rd r:w next rotxr.w #2,rd r:w next rotxr.l erd r:w next rotxr.l #2,erd r:w next rte r:w next r:w stack (exr) r:w stack (h) r:w stack (l) internal operation, r:w * 4 1 state rts r:w next r:w:m stack (h) r:w stack (l) internal operation, r:w * 4 1 state shal.b rd r:w next 1 2 3 4 5 6 7 8 9
appendix a instruction set rev. 3.00 jan 11, 2005 page 1041 of 1220 rej09b0186-0300o instruction shal.b #2,rd r:w next shal.w rd r:w next shal.w #2,rd r:w next shal.l erd r:w next shal.l #2,erd r:w next shar.b rd r:w next shar.b #2,rd r:w next shar.w rd r:w next shar.w #2,rd r:w next shar.l erd r:w next shar.l #2,erd r:w next shll.b rd r:w next shll.b #2,rd r:w next shll.w rd r:w next shll.w #2,rd r:w next shll.l erd r:w next shll.l #2,erd r:w next shlr.b rd r:w next shlr.b #2,rd r:w next shlr.w rd r:w next shlr.w #2,rd r:w next shlr.l erd r:w next shlr.l #2,erd r:w next sleep r:w next internal operation:m stc ccr,rd r:w next stc exr,rd r:w next stc ccr,@erd r:w 2nd r:w next w:w ea stc exr,@erd r:w 2nd r:w next w:w ea stc ccr,@(d:16,erd) r:w 2nd r:w 3rd r:w next w:w ea stc exr,@(d:16,erd) r:w 2nd r:w 3rd r:w next w:w ea stc ccr,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next w:w ea stc exr,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next w:w ea stc ccr,@ ? erd r:w 2nd r:w next internal operation, w:w ea 1 state stc exr,@ ? erd r:w 2nd r:w next internal operation, w:w ea 1 state stc ccr,@aa:16 r:w 2nd r:w 3rd r:w next w:w ea stc exr,@aa:16 r:w 2nd r:w 3rd r:w next w:w ea 1 2 3 4 5 6 7 8 9
appendix a instruction set rev. 3.00 jan 11, 2005 page 1042 of 1220 rej09b0186-0300o instruction stc ccr,@aa:32 r:w 2nd r:w 3rd r:w 4th r:w next w:w ea stc exr,@aa:32 r:w 2nd r:w 3rd r:w 4th r:w next w:w ea stm.l(ern ? ern+1),@ ? sp * 9 r:w 2nd r:w:m next internal operation, w:w:m stack (h) * 3 w:w stack (l) * 3 1 state stm.l(ern ? ern+2),@ ? sp * 9 r:w 2nd r:w:m next internal operation, w:w:m stack (h) * 3 w:w stack (l) * 3 1 state stm.l(ern ? ern+3),@ ? sp * 9 r:w 2nd r:w:m next internal operation, w:w:m stack (h) * 3 w:w stack (l) * 3 1 state stmac mach,erd r:w next stmac macl,erd r:w next sub.b rs,rd r:w next sub.w #xx:16,rd r:w 2nd r:w next sub.w rs,rd r:w next sub.l #xx:32,erd r:w 2nd r:w 3rd r:w next sub.l ers,erd r:w next subs #1/2/4,erd r:w next subx #xx:8,rd r:w next subx rs,rd r:w next tas @erd * 8 r:w 2nd r:w next r:b:m ea w:b ea trapa #x:2 r:w next internal operation, w:w stack (l) w:w stack (h) w:w stack (exr) r:w:m vec r:w vec+2 internal operation, r:w * 7 1 state 1 state xor.b #xx8,rd r:w next xor.b rs,rd r:w next xor.w #xx:16,rd r:w 2nd r:w next xor.w rs,rd r:w next xor.l #xx:32,erd r:w 2nd r:w 3rd r:w next xor.l ers,erd r:w 2nd r:w next xorc #xx:8,ccr r:w next xorc #xx:8,exr r:w 2nd r:w next 1 2 3 4 5 6 7 8 9
appendix a instruction set rev. 3.00 jan 11, 2005 page 1043 of 1220 rej09b0186-0300o instruction reset exception handling r:w vec r:w vec+2 internal operation, r:w * 5 1 state interrupt exception handling r:w * 6 internal operation, w:w stack (l) w:w stack (h) w:w stack (exr) r:w:m vec r:w vec+2 internal operation, r:w * 7 1 state 1 state notes: 1. eas is the contents of er5. ead is the contents of er6. 2. eas is the contents of er5. ead is the contents of er6. both registers are incremented by 1 after execution of the instruct ion. n is the initial value of r4l or r4. if n = 0, these bus cycles are not executed. 3. repeated two times to save or restore two registers, three times for three registers, or four times for four registers. 4. start address after return. 5. start address of the program. 6. prefetch address, equal to two plus the pc value pushed onto the stack. in recovery from sleep mode or software standby mod e the read operation is replaced by an internal operation. 7. start address of the interrupt-handling routine. 8. only register er0, er1, er4, or er5 should be used when using the tas instruction. 9. only re g ister er0 to er6 should be used when usin g the stm/ldm instruction. 1 2 3 4 5 6 7 8 9
appendix a instruction set rev. 3.00 jan 11, 2005 page 1044 of 1220 rej09b0186-0300o a.6 condition code modification this section indicates the effect of each cpu instruction on the condition code. the notation used in the table is defined below. m = 31 for longword operands 15 for word operands 7 for byte operands si di ri dn ? 0 1 * z' c' the i-th bit of the source operand the i-th bit of the destination operand the i-th bit of the result the specified bit in the destination operand not affected modified according to the result of the instruction (see definition) always cleared to 0 always set to 1 undetermined (no guaranteed value) z flag before instruction execution c flag before instruction execution
appendix a instruction set rev. 3.00 jan 11, 2005 page 1045 of 1220 rej09b0186-0300o table a.7 condition code modification instruction h n z v c definition add h = sm ? 4 dm ? 4 + dm ? 4 rmC4 + sm ? 4 rmC4 n = rm z = rm rmC1 ...... r0 v = sm dm rm + sm dm rm c = sm dm + dm rm + sm rm adds ????? addx h = sm ? 4 dm ? 4 + dm ? 4 rmC4 + sm ? 4 rmC4 n = rm z = z' rm ...... r0 v = sm dm rm + sm dm rm c = sm dm + dm rm + sm rm and ? 0 ? n = rm z = rm rmC1 ...... r0 andc stores the corresponding bits of the result. no flags change when the operand is exr. band ???? c = c' dn bcc ????? bclr ????? biand ???? c = c' dn bild ???? c = dn bior ???? c = c' + dn bist ????? bixor ???? c = c' dn + c' dn bld ???? c = dn bnot ????? bor ???? c = c' + dn bset ????? bsr ????? bst ????? btst ?? ?? z = dn bxor ???? c = c' dn + c' dn clrmac ?????
appendix a instruction set rev. 3.00 jan 11, 2005 page 1046 of 1220 rej09b0186-0300o instruction h n z v c definition cmp h = sm ? 4 dmC4 + dmC4 rm ? 4 + sm ? 4 rm ? 4 n = rm z = rm rmC1 ...... r0 v = sm dm rm + sm dm rm c = sm dm + dm rm + sm rm daa * * n = rm z = rm rmC1 ...... r0 c: decimal arithmetic carry das * * n = rm z = rm rmC1 ...... r0 c: decimal arithmetic borrow dec ? ? n = rm z = rm rmC1 ...... r0 v = dm rm divxs ? ?? n = sm dm + sm dm z = sm smC1 ...... s0 divxu ? ?? n = sm z = sm smC1 ...... s0 eepmov ????? exts ? 0 ? n = rm z = rm rmC1 ...... r0 extu ? 0 0 ? z = rm rmC1 ...... r0 inc ? ? n = rm z = rm rmC1 ...... r0 v = dm rm jmp ????? jsr ????? ldc stores the corresponding bits of the result. no flags change when the operand is exr. ldm ????? ldmac ????? mac ?????
appendix a instruction set rev. 3.00 jan 11, 2005 page 1047 of 1220 rej09b0186-0300o instruction h n z v c definition mov ? 0 ? n = rm z = rm rmC1 ...... r0 movfpe can not be used in h8s/2643 group movtpe mulxs ? ?? n = r2m z = r2m r2mC1 ...... r0 mulxu ????? neg h = dm ? 4 + rm ? 4 n = rm z = rm rmC1 ...... r0 v = dm rm c = dm + rm nop ????? not ? 0 ? n = rm z = rm rmC1 ...... r0 or ? 0 ? n = rm z = rm rmC1 ...... r0 orc stores the corresponding bits of the result. no flags change when the operand is exr. pop ? 0 ? n = rm z = rm rmC1 ...... r0 push ? 0 ? n = rm z = rm rmC1 ...... r0 rotl ? 0 n = rm z = rm rmC1 ...... r0 c = dm (1-bit shift) or c = dm ? 1 (2-bit shift) rotr ? 0 n = rm z = rm rmC1 ...... r0 c = d0 (1-bit shift) or c = d1 (2-bit shift)
appendix a instruction set rev. 3.00 jan 11, 2005 page 1048 of 1220 rej09b0186-0300o instruction h n z v c definition rotxl ? 0 n = rm z = rm rmC1 ...... r0 c = dm (1-bit shift) or c = dm ? 1 (2-bit shift) rotxr ? 0 n = rm z = rm rmC1 ...... r0 c = d0 (1-bit shift) or c = d1 (2-bit shift) rte stores the corresponding bits of the result. rts ????? shal ? n = rm z = rm rmC1 ...... r0 v = dm dm ? 1 + dm dmC1 (1-bit shift) v = dm dm ? 1 dm ? 2 dm dmC1 dmC2 (2-bit shift) c = dm (1-bit shift) or c = dm ? 1 (2-bit shift) shar ? 0 n = rm z = rm rmC1 ...... r0 c = d0 (1-bit shift) or c = d1 (2-bit shift) shll ? 0 n = rm z = rm rmC1 ...... r0 c = dm (1-bit shift) or c = dm ? 1 (2-bit shift) shlr ? 0 0 n = rm z = rm rmC1 ...... r0 c = d0 (1-bit shift) or c = d1 (2-bit shift) sleep ????? stc ????? stm ????? stmac ? ? n = 1 if mac instruction resulted in negative value in mac register z = 1 if mac instruction resulted in zero value in mac register v = 1 if mac instruction resulted in overflow
appendix a instruction set rev. 3.00 jan 11, 2005 page 1049 of 1220 rej09b0186-0300o instruction h n z v c definition sub h = sm ? 4 dmC4 + dmC4 rm ? 4 + sm ? 4 rm ? 4 n = rm z = rm rmC1 ...... r0 v = sm dm rm + sm dm rm c = sm dm + dm rm + sm rm subs ????? subx h = sm ? 4 dmC4 + dmC4 rm ? 4 + sm ? 4 rm ? 4 n = rm z = z' rm ...... r0 v = sm dm rm + sm dm rm c = sm dm + dm rm + sm rm tas ? 0 ? n = dm z = dm dmC1 ...... d0 trapa ????? xor ? 0 ? n = rm z = rm rmC1 ...... r0 xorc stores the corresponding bits of the result. no flags change when the operand is exr.
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1050 of 1220 rej09b0186-0300o appendix b internal i/o register b.1 addresses address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width (bits) h'fdac dadr2 d/a2, d/a3 8 h'fdad dadr3 h'fdae dacr23 daoe1 daoe0 dae ? ? ? ? ? h'fdb0 ircr ire ircks2 ircks1 ircks0 ? ? ? ? sci0, irda h'fdb4 scrx ? iicx1 iicx0 iice flshe ? ? ? iic h'fdb5 ddcswr ? ? ? ? clr3 clr2 clr1 clr0 h'fdb8 dadrah0/ dacr0 da13/ test da12/ pwme da11/? da10/? da9/ oeb da8/ oea da7/os da6/cks pwm0 h'fdb9 dadral0 da5 da4 da3 da2 da1 da0 cfs ? h'fdba dadrbh0/ dacnth0 da13/ da12/ da11/ da10/ da9/ da8/ da7/ da6/ h'fdbb dadrbl0/ dacntl0 da5/ da4/ da3/ da2/ da1/ da0/ cfs/ regs h'fdbc dadrah1/ dacr1 da13/ test da12/ pwme da11/? da10/? da9/ oeb da8/ oea da7/os da6/cks pwm1 h'fdbd dadral1 da5 da4 da3 da2 da1 da0 cfs ? h'fdbe dadrbh1/ dacnth1 da13/ da12/ da11/ da10/ da9/ da8/ da7/ da6/ h'fdbf dadrbl1/ dacntl1 da5/ da4/ da3/ da2/ da1/ da0/ cfs/ regs h'fdc0 h'fdc1 h'fdc2 tcr2 tcr3 tcsr2 cmieb cmieb cmfb cmiea cmiea cmfa ovie ovie ovf cclr1 cclr1 ? cclr0 cclr0 os3 cks2 cks2 os2 cks1 cks1 os1 cks0 cks0 os0 tmr2, tmr3 16 h'fdc3 tcsr3 cmfb cmfa ovf ? os3 os2 os1 os0 h'fdc4 tcora2 h'fdc5 tcora3 h'fdc6 tcorb2 h'fdc7 tcorb3 h'fdc8 tcnt2 h'fdc9 tcnt3 h'fdd0 h'fdd1 smr3 smr3 brr3 c/ a gm chr blk pe pe o/ e o/ e stop bcp1 mp bcp0 cks1 cks1 cks0 cks0 sci3, smart card interface 8 h'fdd2 scr3 tie rie te re mpie teie cke1 cke0 h'fdd3 tdr3
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1051 of 1220 rej09b0186-0300o address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width (bits) h'fdd4 h'fdd5 ssr3 ssr3 rdr3 tdre tdre rdrf rdrf orer orer fer ers per per tend tend mpb mpb mpbt mpbt h'fdd6scmr3????sdirsinv?smif sci3, smart card interface 8 h'fdd8 h'fdd9 smr4 smr4 brr4 c/ a gm chr blk pe pe o/ e o/ e stop bcp1 mp bcp0 cks1 cks1 cks0 cks0 h'fdda scr4 tie rie te re mpie teie cke1 cke0 h'fddb tdr4 h'fddc ssr4 tdre rdrf orer fer per tend mpb mpbt ssr4 tdre rdrf orer ers per tend mpb mpbt h'fddd rdr4 h'fddescmr4????sdirsinv?smif sci4, smart card interface h'fde4 sbycr ssby sts2 sys1 sts0 ope ? ? ? system h'fde5 syscr macs ? intm1 intm0 nmieg mrese ? rame h'fde6 sckcr pstop ? ? ? stcs sck2 sck1 sck0 h'fde7mdcr?????mds2mds1mds0 h'fde8 mstpcra mstpa7 mstpa6 mstpa5 mstpa4 mstpa3 mstpa2 mstpa1 mstpa0 h'fde9 mstpcrb mstpb7 mstpb6 mstpb5 mstpb4 mstpb3 mstpb2 mstpb1 mstpb0 h'fdea mstpcrc mstpc7 mstpc6 mstpc5 mstpc4 mstpc3 mstpc2 mstpc1 mstpc0 h'fdeb pfcr css07 css36 buzze lcass ae3 ae2 ae1 ae0 h'fdec lpwrcr dton lson nesel substp rfcut ? stc1 stc0 h'fe00bara???????? pbc h'fe01 baa23 baa22 baa21 baa20 baa19 baa18 baa17 baa16 h'fe02 baa15 baa14 baa13 baa12 baa11 baa10 baa9 baa8 h'fe03 baa7 baa6 baa5 baa4 baa3 baa2 baa1 baa0 h'fe04barb???????? h'fe05 baa23 baa22 baa21 baa20 baa19 baa18 baa17 baa16 h'fe06 baa15 baa14 baa13 baa12 baa11 baa10 baa9 baa8 h'fe07 baa7 baa6 baa5 baa4 baa3 baa2 baa1 baa0 h'fe08 bcra cmfa cda bamra2 bamra1 bamra0 csela1 csela0 biea h'fe09 bcrb cmfb cdb bamrb2 bamrb1 bamrb0 cselb1 cselb0 bieb h'fe12 iscrh irq7scb irq7sca irq6scb irq6sca irq5scb irq5sca irq4scb irq4sca h'fe13 iscrl irq3scb irq3sca irq2scb irq2sca irq1scb irq1sca irq0scb irq0sca h'fe14 ier irq7e irq6e irq5e irq4e irq3e irq2e irq1e irq0e h'fe15 isr irq7f irq6f irq5f irq4f irq3f irq2f irq1f irq0f interrupt controller
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1052 of 1220 rej09b0186-0300o address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width (bits) h'fe16 dtcera dtcea7 dtcea6 dtcea5 dtcea4 dtcea3 dtcea2 dtcea1 dtcea0 dtc 8 h'fe17 dtcerb dtceb7 dtceb6 dtceb5 dtceb4 dtceb3 dtceb2 dtceb1 dtceb0 h'fe18 dtcerc dtcec7 dtcec6 dtcec5 dtcec4 dtcec3 dtcec2 dtcec1 dtcec0 h'fe19 dtcerd dtced7 dtced6 dtced5 dtced4 dtced3 dtced2 dtced1 dtced0 h'fe1a dtcere dtcee7 dtcee6 dtcee5 dtcee4 dtcee3 dtcee2 dtcee1 dtcee0 h'fe1b dtcerf dtcef7 dtcef6 dtcef5 dtcef4 dtcef3 dtcef2 dtcef1 dtcef0 h'fe1e dtceri dtcei7 dtcei6 dtcei5 dtcei4 dtcei3 dtcei2 dtcei1 dtcei0 h'fe1f dtvecr swdte dtvec6 dtvec5 dtvec4 dtvec3 dtvec2 dtvec1 dtvec0 h'fe26 pcr g3cms1 g3cms0 g2cms1 g2cms0 g1cms1 g1cms0 g0cms1 g0cms0 ppg h'fe27 pmr g3inv g2inv g1inv g0inv g3nov g2nov g1nov g0nov h'fe28 nderh nder15 nder14 nder13 nder12 nder11 nder10 nder9 nder8 h'fe29 nderl nder7 nder6 nder5 nder4 nder3 nder2 nder1 nder0 h'fe2a podrh pod15 pod14 pod13 pod12 pod11 pod10 pod9 pod8 h'fe2b podrl pod7 pod6 pod5 pod4 pod3 pod2 pod1 pod0 h'fe2c ndrh ndr15 ndr14 ndr13 ndr12 ndr11 ndr10 ndr9 ndr8 h'fe2d ndrl ndr7 ndr6 ndr5 ndr4 ndr3 ndr2 ndr1 ndr0 h'fe2e ndrh ? ? ? ? ndr11 ndr10 ndr9 ndr8 h'fe2f ndrl ? ? ? ? ndr3 ndr2 ndr1 ndr0 h'fe30 p1ddr p17ddr p16ddr p15ddr p14ddr p13ddr p12ddr p11ddr p10ddr port h'fe31 p2ddr p27ddr p26ddr p25ddr p24ddr p23ddr p22ddr p21ddr p20ddr h'fe32 p3ddr p37ddr p36ddr p35ddr p34ddr p33ddr p32ddr p31ddr p30ddr h'fe34p5ddr?????p52ddrp51ddrp50ddr h'fe36 p7ddr p77ddr p76ddr p75ddr p74ddr p73ddr p72ddr p71ddr p70ddr h'fe37 p8ddr ? p86ddr p85ddr p84ddr p83ddr p82ddr p81ddr p80ddr h'fe39 paddr pa7ddr pa6ddr pa5ddr pa4ddr pa3ddr pa2ddr pa1ddr pa0ddr h'fe3a pbddr pb7ddr pb6ddr pb5ddr pb4ddr pb3ddr pb2ddr pb1ddr pb0ddr h'fe3b pcddr pc7ddr pc6ddr pc5ddr pc4ddr pc3ddr pc2ddr pc1ddr pc0ddr h'fe3c pdddr pd7ddr pd6ddr pd5ddr pd4ddr pd3ddr pd2ddr pd1ddr pd0ddr h'fe3d peddr pe7ddr pe6ddr pe5ddr pe4ddr pe3ddr pe2ddr pe1ddr pe0ddr h'fe3e pfddr pf7ddr pf6ddr pf5ddr pf4ddr pf3ddr pf2ddr pf1ddr pf0ddr h'fe3f pgddr ? ? ? pg4ddr pg3ddr pg2ddr pg1ddr pg0ddr h'fe40 papcr pa7pcr pa6pcr pa5pcr pa4pcr pa3pcr pa2pcr pa1pcr pa0pcr h'fe41 pbpcr pb7pcr pb6pcr pb5pcr pb4pcr pb3pcr pb2pcr pb1pcr pb0pcr h'fe42 pcpcr pc7pcr pc6pcr pc5pcr pc4pcr pc3pcr pc2pcr pc1pcr pc0pcr h'fe43 pdpcr pd7pcr pd6pcr pd5pcr pd4pcr pd3pcr pd2pcr pd1pcr pd0pcr h'fe44 pepcr pe7pcr pe6pcr pe5pcr pe4pcr pe3pcr pe2pcr pe1pcr pe0pcr h'fe46 p3odr p37odr p36odr p35odr p34odr p33odr p32odr p31odr p30odr
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1053 of 1220 rej09b0186-0300o address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width (bits) h'fe47 paodr pa7odr pa6odr pa5odr pa4odr pa3odr pa2odr pa1odr pa0odr port 8 h'fe48 pbodr pb7odr pb6odr pb5odr pb4odr pb3odr pb2odr pb1odr pb0odr h'fe49 pcodr pc7odr pc6odr pc5odr pc4odr pc3odr pc2odr pc1odr pc0odr h'fe80 tcr3 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu3 16 h'fe81 tmdr3 ? ? bfb bfa md3 md2 md1 md0 h'fe82 tior3h iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'fe83 tior3l iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 h'fe84 tier3 ttge ? ? tciev tgied tgiec tgieb tgiea h'fe85 tsr3 ? ? ? tcfv tgfd tgfc tgfb tgfa h'fe86 tcnt3 h'fe87 h'fe88 tgr3a h'fe89 h'fe8a tgr3b h'fe8b h'fe8c tgr3c h'fe8d h'fe8e tgr3d h'fe8f h'fe90 tcr4 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu4 h'fe91 tmdr4 ? ? ? ? md3 md2 md1 md0 h'fe92 tior4 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'fe94 tier4 ttge ? tcieu tciev ? ? tgieb tgiea h'fe95 tsr4 tcfd ? tcfu tcfv ? ? tgfb tgfa h'fe96 tcnt4 h'fe97 h'fe98 tgr4a h'fe99 h'fe9a tgr4b h'fe9b h'fea0 tcr5 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu5 h'fea1 tmdr5 ? ? ? ? md3 md2 md1 md0 h'fea2 tior5 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'fea4 tier5 ttge ? tcieu tciev ? ? tgieb tgiea h'fea5 tsr5 tcfd ? tcfu tcfv ? ? tgfb tgfa h'fea6 tcnt5 h'fea7
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1054 of 1220 rej09b0186-0300o address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width (bits) h'fea8 tgr5a tpu5 16 h'fea9 h'feaa tgr5b h'feab h'feb0 tstr ? ? cst5 cst4 cst3 cst2 cst1 cst0 tpu h'feb1 tsyr ? ? sync5 sync4 sync3 sync2 sync1 sync0 h'fec0 ipra ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 interrupt 8 h'fec1 iprb ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 controller h'fec2 iprc ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 h'fec3 iprd ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 h'fec4 ipre ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 h'fec5 iprf ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 h'fec6 iprg ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 h'fec7 iprh ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 h'fec8 ipri ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 h'fec9 iprj ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 h'feca iprk ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 h'fecb iprl ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 h'fece ipro ? ipr6 ipr5 ipr4 ? ipr2 ipr1 ipr0 h'fed0 abwcr abw7 abw6 abw5 abw4 abw3 abw2 abw1 abw0 bus h'fed1 astcr ast7 ast6 ast5 ast4 ast3 ast2 ast1 ast0 controller h'fed2 wcrh w71 w70 w61 w60 w51 w50 w41 w40 h'fed3 wcrl w31 w30 w21 w20 w11 w10 w01 w00 h'fed4 bcrh icis1 icis0 brstrm brsts1 brsts0 rmts2 rmts1 rmst0 h'fed5 bcrl brle breqoe ? oes dds rcts wdbe waite h'fed6 mcr tpc be rcdm cw2 mxc1 mxc0 rlw1 rlw0 h'fed7 dramcr rfshe cbrm rmode cmf cmie cks2 cks1 cks0 h'fed8 rtcnt h'fed9 rtcor h'fedb ramer ? ? ? ? rams ram2 ram1 ram0 flash h'fee0mar0ah???????? dmac16 h'fee1 h'fee2 mar0al h'fee3 h'fee4 ioar0a h'fee5
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1055 of 1220 rej09b0186-0300o address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width (bits) h'fee6 etcr0a dmac 16 h'fee7 h'fee8mar0bh???????? h'fee9 h'feea mar0bl h'feeb h'feec ioar0b h'feed h'feee etcr0b h'feef h'fef0mar1ah???????? h'fef1 h'fef2 mar1al h'fef3 h'fef4 ioar1a h'fef5 h'fef6 etcr1a h'fef7 h'fef8mar1bh???????? h'fef9 h'fefa mar1bl h'fefb h'fefc ioar1b h'fefd h'fefe etcr1b h'feff h'ff00 p1dr p17dr p16dr p15dr p14dr p13dr p12dr p11dr p10dr port 8 h'ff01 p2dr p27dr p26dr p25dr p24dr p23dr p22dr p21dr p20dr h'ff02 p3dr p37dr p36dr p35dr p34dr p33dr p32dr p31dr p30dr h'ff04p5dr?????p52drp51drp50dr h'ff05? ???????? h'ff06 p7dr p77dr p76dr p75dr p74dr p73dr p72dr p71dr p70dr h'ff07 p8dr ? p86dr p85dr p84dr p83dr p82dr p81dr p80dr h'ff09 padr pa7dr pa6dr pa5dr pa4dr pa3dr pa2dr pa1dr pa0dr h'ff0a pbdr pb7dr pb6dr pb5dr pb4dr pb3dr pb2dr pb1dr pb0dr h'ff0b pcdr pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr h'ff0c pddr pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1056 of 1220 rej09b0186-0300o address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width (bits) h'ff0d pedr pe7dr pe6dr pe5dr pe4dr pe3dr pe2dr pe1dr pe0dr port 8 h'ff0e pfdr pf7dr pf6dr pf5dr pf4dr pf3dr pf2dr pf1dr pf0dr h'ff0f pgdr ? ? ? pg4dr pg3dr pg2dr pg1dr pg0dr h'ff10 tcr0 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu0 16 h'ff11 tmdr0 ? ? bfb bfa md3 md2 md1 md0 h'ff12 tior0h iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ff13 tior0l iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 h'ff14 tier0 ttge ? ? tciev tgied tgiec tgieb tgiea h'ff15 tsr0 ? ? ? tcfv tgfd tgfc tgfb tgfa h'ff16 tcnt0 h'ff17 h'ff18 tgr0a h'ff19 h'ff1a tgr0b h'ff1b h'ff1c tgr0c h'ff1d h'ff1e tgr0d h'ff1f h'ff20 tcr1 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu1 h'ff21 tmdr1 ? ? ? ? md3 md2 md1 md0 h'ff22 tior1 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ff24 tier1 ttge ? tcieu tciev ? ? tgieb tgiea h'ff25 tsr1 tcfd ? tcfu tcfv ? ? tgfb tgfa h'ff26 tcnt1 h'ff27 h'ff28 tgr1a h'ff29 h'ff2a tgr1b h'ff2b h'ff30 tcr2 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu2 h'ff31 tmdr2 ? ? ? ? md3 md2 md1 md0 h'ff32 tior2 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ff34 tier2 ttge ? tcieu tciev ? ? tgieb tgiea h'ff35 tsr2 tcfd ? tcfu tcfv ? ? tgfb tgfa
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1057 of 1220 rej09b0186-0300o address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width (bits) h'ff36 tcnt2 tpu2 16 h'ff37 h'ff38 tgr2a h'ff39 h'ff3a tgr2b h'ff3b h'ff60 dmawer ? ? ? ? we1b we1a we0b we0a dmac 8 h'ff61 dmatcr ? ? tee1 tee0 ? ? ? ? h'ff62 dmacr0a dtsz dtid rpe dtdir dtf3 dtf2 dtf1 dtf0 16 h'ff63 dmacr0b dtsz dtid rpe dtdir dtf3 dtf2 dtf1 dtf0 h'ff64 dmacr1a dtsz dtid rpe dtdir dtf3 dtf2 dtf1 dtf0 h'ff65 dmacr1b dtsz dtid rpe dtdir dtf3 dtf2 dtf1 dtf0 h'ff66 dmabcrh fae1 fae0 sae1 sae0 dta1b dta1a dta0b dta0a h'ff67 dmabcrl dte1b dte1a dte0b dte0a dtie1b dtie1a dtie0b dtie0a h'ff68 h'ff69 h'ff6a tcr0 tcr1 tcsr0 cmieb cmieb cmfb cmiea cmiea cmfa ovie ovie ovf cclr1 cclr1 adte cclr0 cclr0 os3 cks2 cks2 os2 cks1 cks1 os1 cks0 cks0 os0 tmr0, tmr1 h'ff6b tcsr1 cmfb cmfa ovf ? os3 os2 os1 os0 h'ff6c tcora0 h'ff6d tcora1 h'ff6e tcorb0 h'ff6f tcorb1 h'ff70 tcnt0 h'ff71 tcnt1 h'ff74 (write) tcsr0/ tcnt0 ovf wt/ it tme ? ? cks2 cks1 cks0 wdt0 h'ff75 (read) tcnt0 h'ff76 (write) rstcsr wovf rste rsts ? ? ? ? ? h'ff77 (read) rstcsr wovf rste rsts ? ? ? ? ? h'ff78 smr0 smr0 iccr0 c/ a gm ice chr blk ieic pe pe mst o/ e o/ e trs stop bcp1 acke mp bcp0 bbsy cks1 cks1 iric cks0 cks0 scp sci0, iic0, smart card interface 8
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1058 of 1220 rej09b0186-0300o address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width (bits) h'ff79 brr0 sci0, iic0, 8 icsr0 estp stop irtr aasx al aas adz ackb smart card h'ff7a scr0 tie rie te re mpie teie cke1 cke0 interface h'ff7b tdr0 h'ff7c h'ff7d ssr0 ssr0 rdr0 tdre tdre rdrf rdrf orer orer fer ers per per tend tend mpb mpb mpbt mpbt h'ff7escmr0????sdirsinv?smif icdr0/ sarx0 icdr7/ svax6 icdr6/ svax5 icdr5/ svax4 icdr4/ svax3 icdr3/ svax2 icdr2/ svax1 icdr1/ svax0 icdr0/ fsx h'ff7f icmr0/ sar0 mls/ sva6 wait/ sva5 cks2/ sva4 cks1/ sva3 cks0/ sva2 bc2/ sva1 bc1/ sva0 bc0/ fs h'ff80 smr1 smr1 iccr1 c/ a gm ice chr blk ieic pe pe mst o/ e o/ e trs stop bcp1 acke mp bcp0 bbsy cks1 cks1 iric cks0 cks0 scp sci1, iic1, smart card interface h'ff81 brr1 icsr1 estp stop irtr aasx al aas adz ackb h'ff82 scr1 tie rie te re mpie teie cke1 cke0 h'ff83 tdr1 h'ff84 ssr1 tdre rdrf orer fer per tend mpb mpbt ssr1 tdre rdrf orer ers per tend mpb mpbt h'ff85 rdr1 h'ff86scmr1????sdirsinv?smif icdr1/ sarx1 icdr7/ svarx6 icdr6/ svarx5 icdr5/ svarx4 icdr4/ svarx3 icdr3/ svarx2 icdr2/ svarx1 icdr1/ svarx0 icdr0/ fsx h'ff87 icmr1/ sar1 mls/ sva6 wait/ sva5 cks2/ sva4 cks1/ sva3 cks0/ sva2 bc2/ sva1 bc1/ sva0 bc0/ fs iic1 h'ff88 h'ff89 smr2 smr2 brr2 c/ a gm chr blk pe pe o/ e o/ e stop bcp1 mp bcp0 cks1 cks1 cks0 cks0 sci2, smart card interface h'ff8a scr2 tie rie te re mpie teie cke1 cke0 h'ff8b tdr2
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1059 of 1220 rej09b0186-0300o address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width (bits) h'ff8c ssr2 tdre rdrf orer fer per tend mpb mpbt sci2, 8 ssr2 tdre rdrf orer fer per tend mpb mpbt smart card h'ff8d rdr2 interface h'ff8e scmr2 ? ? ? ? sdir sinv ? smif h'ff90 addrah ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d h'ff91 addral ad1 ad0 ?????? h'ff92 addrbh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ff93 addrbl ad1 ad0 ?????? h'ff94 addrch ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ff95 addrcl ad1 ad0 ?????? h'ff96 addrdh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ff97 addrdl ad1 ad0 ?????? h'ff98 adcsr adf adie adst scan ch3 ch2 ch1 ch0 h'ff99 adcr trgs1 trgs0 ? ? cks1 cks0 ? ? h'ffa2 (write) tcsr1/ tcnt1 ovf wt/ it tme pss rst/ nmi cks2 cks1 cks0 wdt1 16 h'ffa3 (read) tcnt1 h'ffa4 dadr0 d/a0, 8 h'ffa5 dadr1 d/a1 h'ffa6 dacr01 daoe1 daoe0 dae ? ? ? ? ? h'ffa8 flmcr1 fwe swe1 esu1 psu1 ev1 pv1 e1 p1 flash h'ffa9flmcr2fler??????? h'ffaa ebr1 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 h'ffab ebr2 ? ? ? ? eb11 eb10 eb9 eb8 h'ffacflpwcrpdwnd??????? h'ffb0 port1 p17 p16 p15 p14 p13 p12 p11 p10 port h'ffb1 port2 p27 p26 p25 p24 p23 p22 p21 p20 h'ffb2 port3 p37 p36 p35 p34 p33 p32 p31 p30 h'ffb3 port4 p47 p46 p45 p44 p43 p42 p41 p40 h'ffb4port5?????p52p51p50 h'ffb6 port7 p77 p76 p75 p74 p73 p72 p71 p70 h'ffb7 port8 ? p86 p85 p84 p83 p82 p81 p80 h'ffb8 port9 p97 p96 p95 p94 p93 p92 p91 p90
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1060 of 1220 rej09b0186-0300o address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width (bits) h'ffb9 porta pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 port 8 h'ffba portb pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 h'ffbb portc pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 h'ffbc portd pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 h'ffbd porte pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 h'ffbe portf pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 h'ffbf portg ? ? ? pg4 pg3 pg2 pg1 pg0
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1061 of 1220 rej09b0186-0300o b.2 functions dadr0?d/a data register 0 dadr1?d/a data register 1 dadr2?d/a data register 2 dadr3?d/a data register 3 h'ffa4 h'ffa5 h'fdac h'fdad d/a0 d/a1 d/a2 d/a3 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : dacr01?d/a control register 01 dacr23?d/a control register 23 h'ffa6 h'fdae d/a0, 1 d/a2, 3 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 0 r/w 4 ? 1 ? 3 ? 1 ? 0 ? 1 ? 2 ? 1 ? 1 ? 1 ? bit initial value r/w : : : d/a output enable 1 0 disables analog output da1 (da3) 1 enables channel 1 d/a conversion. also enables analog output da1 (da3) d/a output enable 0 0 disables analog output da0 (da2) 1 enables channel 0 d/a conversion. also enables analog output da0 (da2) d/a enable daoe1 daoe0 dae description 0 0 * disables channel 0, 1 (channel 2, 3) d/a conversion 1 0 enables channel 0 (channel 2) d/a conversion disables channel 1 (channel 3) d/a conversion 1 enables channel 0, 1 (channel 2, 3) d/a conversion 1 0 0 disables channel 0 (channel 2) d/a conversion enables channel 1 (channel 3) d/a conversion 1 enables channel 0, 1 (channel 2, 3) d/a conversion 1 * enables channel 0, 1 (channel 2, 3) d/a conversion * : don?t care
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1062 of 1220 rej09b0186-0300o ircr?irda control register h'fdb0 sci0, irda 7 ire 0 r/w 6 ircks2 0 r/w 5 ircks1 0 r/w 4 ircks0 0 r/w 3 ? 0 ? 0 ? 0 ? 2 ? 0 ? 1 ? 0 ? irda enable 0 txd0/irtxd and rxd0/irrxd pins function as txd0 and rxd0 1 txd0/irtxd and rxd0/irrxd pins function as irtx0 and irrxd irda clock select 2 to 0 bit 6 bit 5 bit 4 description ircks2 ircks1 ircks0 0 0 0 b 3/16 (3/16ths of bit rate) 1 /2 1 0 /4 1 /8 1 0 0 /16 1 /32 1 0 /64 1 /128 bit initial value r/w : : : scrx?serial control register x h'fdb4 iic 7 ? 0 r/w 6 iicx1 0 r/w 5 iicx0 0 r/w 4 iice 0 r/w 3 flshe 0 r/w 0 ? 0 r/w 2 ? 0 r/w 1 ? 0 r/w i 2 c transfer rate select 1, 0 i 2 c master enable 0 disables cpu access of i 2 c bus interface data register and control register 1 enables cpu access of i 2 c bus interface data register and control register 0 flash control registers deselected in area h'ffffa8 to h'ffffac 1 flash control registers selected in area h'ffffa8 to h'ffffac flash memory control register enable bit initial value r/w : : : the master mode transfer rate is selected in combination with cks2 to cks0 in icmr. for details, see the section on the i 2 c bus mode register.
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1063 of 1220 rej09b0186-0300o ddcswr?ddc switch register h'fdb5 iic 7 ? 0 r/(w) * 1 6 ? 0 r/(w) * 1 5 ? 0 r/(w) * 1 4 ? 0 r/(w) * 1 3 clr3 1 w * 2 0 clr0 1 w * 2 2 clr2 1 w * 2 1 clr1 1 w * 2 notes: 1. should always be written with 0. 2. always read as 1. reserved bit bit initial value r/w : : : iic clear 3 to 0 clr3 clr2 clr1 clr0 0 0 ? ? 1 0 0 1 1 0 1 1 ? ? ? setting prohibited setting prohibited iic0 internal latch cleared iic1 internal latch cleared iic0 and iic1 internal latch cleared invalid setting description
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1064 of 1220 rej09b0186-0300o dacr0?pwm (d/a) control register 0 dacr1?pwm (d/a) control register 1 h'fdb8 h'fdbc pwm0 pwm1 7 test 0 r/w 6 pwme 0 r/w 5 ? 1 ? 4 ? 1 ? 3 oeb 0 r/w 0 cks 0 r/w 2 oea 0 r/w 1 os 0 r/w test mode 0 pwm (d/a) in user status and operating normally 1 pwm (d/a) in test status and will not return correct result of conversion pwm enable 0 dacnt operates as 14-bit up-counter 1 count stops when dacnt = h'0003 output enable b 0 pwm (d/a) channel b output (pwm1/pwm3 output pin) disabled 1 pwm (d/a) channel b output (pwm1/pwm3 output pin) enabled output enable a 0 pwm (d/a) channel a output (pwm0/pwm2 output pin) disabled 1 pwm (d/a) channel a output (pwm0/pwm2 output pin) enabled output select 0 direct pwm output 1 inverted pwm output clock select 0 resolution (t) = system clock cycle (tcyc) 1 resolution (t) = system clock cycle (tcyc) 2 bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1065 of 1220 rej09b0186-0300o dadrah0?pwm (d/a) data register ah0 dadral0?pwm (d/a) data register al0 dadrbh0?pwm (d/a) data register bh0 dadrbl0?pwm (d/a) data register bl0 dadrah1?pwm (d/a) data register ah1 dadral1?pwm (d/a) data register al1 dadrbh1?pwm (d/a) data register bh1 dadrbl1?pwm (d/a) data register bl1 h'fdb8 h'fdb9 h'fdba h'fdbb h'fdbc h'fdbd h'fdbe h'fdbf pwm0 pwm0 pwm0 pwm0 pwm1 pwm1 pwm1 pwm1 15 13 da13 1 r/w 14 12 da12 1 r/w 13 11 da11 1 r/w 12 10 da10 1 r/w 11 9 da9 1 r/w 8 6 da6 1 r/w 10 8 da8 1 r/w 9 7 da7 1 r/w 7 5 da5 1 r/w 6 4 da4 1 r/w 5 3 da3 1 r/w 4 2 da2 1 r/w 3 1 da1 1 r/w 0 ? ? 1 ? 2 0 da0 1 r/w 1 ? cfs 1 r/w dadrh dadrl da13 1 r/w da12 1 r/w da11 1 r/w da10 1 r/w da9 1 r/w da6 1 r/w da8 1 r/w da7 1 r/w da5 1 r/w da4 1 r/w da3 1 r/w da2 1 r/w da1 1 r/w regs 1 r/w da0 1 r/w cfs 1 r/w carrier frequency select 0 basic cycle = resolution (t) 64. dadr range = h'0401 to h'fffd 1 basic cycle = resolution (t) 256. dadr range = h'0103 to h'ffff carrier frequency select 0 basic cycle = resolution (t) 64. dadr range = h'0401 to h'fffd 1 basic cycle = resolution (t) 256. dadr range = h'0103 to h'ffff register select 0 dadra and dadrb access enabled 1 dacr and dacnt access enabled d/a data 13 to 0 d/a data 13 to 0 bit (cpu) bit (data) dadra initial value r/w : : : : dadrb initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1066 of 1220 rej09b0186-0300o dacnth0?pwm (d/a) counter h0 dacntl0?pwm (d/a) counter l0 dacnth1?pwm (d/a) counter h1 dacntl1?pwm (d/a) counter l1 h'fdba h'fdbb h'fdbe h'fdbf pwm0 pwm0 pwm1 pwm1 15 7 0 r/w 14 6 0 r/w 13 5 0 r/w 12 4 0 r/w 11 3 0 r/w 8 0 0 r/w 10 2 0 r/w 9 1 0 r/w 7 8 0 r/w 6 9 0 r/w 5 10 0 r/w 4 11 0 r/w 3 12 0 r/w 0 ? regs 1 r/w 2 13 0 r/w 1 ? 1 ? dacnth dacntl register select 0 dadra and dadrb access enabled 1 dacr and dacnt access enabled bit (cpu) bit (counter) initial value r/w : : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1067 of 1220 rej09b0186-0300o tcr0?timer control register 0 tcr1?timer control register 1 tcr2?timer control register 2 tcr3?timer control register 3 h'ff68 h'ff69 h'fdc0 h'fdc1 tmr0 tmr1 tmr2 tmr3 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w cmfb interrupt request (cmib) disabled cmfb interrupt request (cmib) enabled 0 1 0 compare match interrupt enable b cmfa interrupt request (cmia) disabled cmfa interrupt request (cmia) enabled 1 compare match interrupt enable a ovf interrupt request (ovi) disabled ovf interrupt request (ovi) enabled 0 1 timer overflow interrupt enable internal clock: counting on falling edge of /8192 internal clock: counting on falling edge of /8 internal clock: counting on falling edge of /64 clock input disabled description counter clear 1, 0 clock select 2 to 0 0 1 0 cks0 0 cks2 cks1 0 1 1 external clock: counting on both rising and falling edges external clock: counting on rising edge external clock: counting on falling edge channel 0: counting on tcnt1 overflow signal * channel 1: counting on tcnt0 compare match a * channel 2: counting on tcnt3 overflow signal * channel 3: counting on tcnt2 compare match a * 0 1 0 1 0 1 1 cleared by rising edge of external reset input cleared by compare match a cleared by compare match b clearing disabled 0 1 0 cclr0 description cclr1 0 1 1 bit initial value r/w : : : note: * no countup clock is generated if the channel 0 (channel 2) clock input is the tcnt1 (tcnt3) overflow signal, and that the channel 1 (channel 3) clock input is the tcnt0 (tcnt2) compare match signal. do not, therefore, attempt to make such a setting.
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1068 of 1220 rej09b0186-0300o tcsr0?timer control/status register 0 tcsr1?timer control/status register 1 tcsr2?timer control/status register 2 tcsr3?timer control/status register 3 h'ff6a h'ff6b h'fdc2 h'fdc3 tmr0 tmr1 tmr2 tmr3 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 ? 1 ? 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w tcsr1, tcsr3 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 ? 0 r/w 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w note: * onl y 0 can be written to bits 7 to 5 ( to clear these fla g s ) . tcsr2 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 adte 0 r/w 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w tcsr0 bit 7: compare match flag b 0 [clearing conditions] ? reading cmfb then writing 0 to cmfb when cmfb = 1 ? when dtc is started by cmib interrupt and dtc mrb disel bit is 0 [setting condition] ? when tcnt=tcorb 1 bit 6: compare match flag a 0 [clearing conditions] ? reading cmfa then writing 0 to cmfa when cmfa = 1 ? when dtc is started by cmia interrupt and dtc mrb disel bit is 0 [setting condition] ? when tcnt=tcora 1 bit 5: timer overflow flag 0 [clearing condition] ? reading ovf then writing 0 to ovf when ovf = 1 [setting condition] ? when tcnt changes from h ? ff to h ? 00 1 bit 4: a/d trigger enable 0 a/d conversion start request by compare match a disabled a/d conversion start request by compare match a enabled 1 bits 3 to 0: output select 3 to 0 no change at compare match b 0 output at compare match b 1 output at compare match b inverted output each compare match b (toggle output) 0 1 0 os2 description description os3 0 1 1 no change at compare match a 0 output at compare match a 1 output at compare match a inverted output each compare match a (toggle output) 0 1 0 os0 os1 0 1 1 bit initial value r/w : : : bit initial value r/w : : : bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1069 of 1220 rej09b0186-0300o tcora0?time constant register a0 tcora1?time constant register a1 tcora2?time constant register a2 tcora3?time constant register a3 h'ff6c h'ff6d h'fdc4 h'fdc5 tmr0 tmr1 tmr2 tmr3 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcora0 (tcora2) tcora1 (tcora3) bit initial value r/w : : : tcorb0?time constant register b0 tcorb1?time constant register b1 tcorb2?time constant register b2 tcorb3?time constant register b3 h'ff6e h'ff6f h'fdc6 h'fdc7 tmr0 tmr1 tmr2 tmr3 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcorb0 (tcorb2) tcorb1 (tcorb3) bit initial value r/w : : : tcnt0?timer counter 0 tcnt1?timer counter 1 tcnt2?timer counter 2 tcnt3?timer counter 3 h'ff70 h'ff71 h'fdc8 h'fdc9 tmr0 tmr1 tmr2 tmr3 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w tcnt0 (tcnt2) tcnt1 (tcnt3) bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1070 of 1220 rej09b0186-0300o smr0?serial mode register 0 smr1?serial mode register 1 smr2?serial mode register 2 smr3?serial mode register 3 smr4?serial mode register 4 h'ff78 h'ff80 h'ff88 h'fdd0 h'fdd8 sci0 sci1 sci2 sci3 sci4 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w communication mode 0 asynchronous mode 1 clocked synchronous mode parity enable 0 parity bit addition and checking disabled 1 parity bit addition and checking enabled * stop bit length 0 1 stop bit: in transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. 1 2 stop bits: in transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. parity mode 0 even parity * 1 1 odd parity * 2 clock select 1 and 0 cks1 cks0 description 0 0 clock 1 /4 clock 1 0 /16 clock 1 /64 clock bit initial value r/w : : : multiprocessor mode multiprocessor function disabled multiprocessor format selected 0 1 notes: 1. when even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. note: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/ e bit. character length 0 8-bit data 1 7-bit data * note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted, and it is not possible to choose between lsb-first or msb-first transfer.
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1071 of 1220 rej09b0186-0300o smr0?serial mode register 0 smr1?serial mode register 1 smr2?serial mode register 2 smr3?serial mode register 3 smr4?serial mode register 4 h'ff78 h'ff80 h'ff88 h'fdd0 h'fdd8 smart card interface 7 gm 0 r/w 6 blk 0 r/w 5 pe 0 r/w 4 o/e 0 r/w 3 bcp1 0 r/w 0 cks0 0 r/w 2 bcp0 0 r/w 1 cks1 0 r/w note: set bit 5 to 1 when usin g the smart card interface. gsm mode 0 operation in normal smart card interface mode (1) tend flag set 12.5etu (11.5etu in block transfer mode) after start of first bit (2) on/off control only of clock output 1 operation in gsm mode smart card interface mode (1) tend flag set 11.0etu after start of first bit (2) in addition to on/off control of clock output, high/low control also enabled (set by scr) note: etu: elementary time unit (time for transfer of 1 bit). block transfer mode 0 operation of normal smart card interface mode (1) error signal output, detection, and automatic resending of data (2) txi interrupt generated by tend flag (3) tend flag set 12.5etu after start of transmission (after 11.0etu in gsm mode) 1 operation in block transfer mode (1) no error signal output, detection, or automatic resending of data (2) txi interrupt generated by tdre flag (3) tend flag set 11.5etu after start of transmission (after 11.0etu in gsm mode) basic clock pulse 1, 0 bcp1 bcp0 0 0 32 clock 1 64 clock 1 0 372 clock 1 256 clock bit initial value r/w : : : description
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1072 of 1220 rej09b0186-0300o brr0?bit rate register 0 brr1?bit rate register 1 brr2?bit rate register 2 brr3?bit rate register 3 brr4?bit rate register 4 h'ff79 h'ff81 h'ff89 h'fdd1 h'fdd9 sci0 sci1 sci2 sci3 sci4 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1073 of 1220 rej09b0186-0300o scr0?serial control register 0 scr1?serial control register 1 scr2?serial control register 2 scr3?serial control register 3 scr4?serial control register 4 h'ff7a h'ff82 h'ff8a h'fdd2 h'fdda sci0 sci1 sci2 sci3 sci4 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w transmit interrupt enable 0 disable transmit data empty interrupt (txi) requests 1 enable transmit data empty interrupt (txi) requests receive interrupt enable 0 disable receive data full interrupt (rxi) requests and receive error interrupt (eri) requests * 1 enable receive data full interrupt (rxi) requests and receive error interrupt (eri) requests transmit enable 0 disable transmit operation * 1 1 enable transmit operation * 2 receive enable 0 disable receive operation * 1 1 enable receive operation * 2 multiprocessor interrupt enable 0 multiprocessor interrupt disabled (normal receive operations) [clearing conditions] ? clear the mpie bit to 0 ? when data mpb=1 is received 1 multiprocessor interrupt enabled * until data is received that the multiprocessor bit = 1, receive interrupt (rxi) requests, receive error interrupt (eri) requests, and ssr rdrf, fer, and orer flags cannot be set. transmit end interrupt enable 0 transmit end interrupt (tei) requests disabled * 1 transmit end interrupt (tei) requests enabled * clock enable 1, 0 bit 1 bit 0 description cke1 cke0 0 0 async mode internal clock/sck pin set as i/o port * 1 clock sync mode internal clock/sck pin set for sync clock output * 1 1 async mode internal clock/sck pin set for clock output * 2 clock sync mode internal clock/sck pin set for sync clock output 1 0 async mode external clock/sck pin set for clock input * 3 clock sync mode external clock/sck pin set for sync clock input 1 async mode external clock/sck pin set for clock input * 3 clock sync mode external clock/sck pin set for sync clock input notes: 1. clearing the re bit has no effect on the rdrf, fer, per, or orer flags. 2. serial receiving starts on detection of the start bit when in async mode, or on detection of sync clock input in clock sync mode. before setting the re bit to 1, be sure to set the smr to decide the receive format. notes: 1. the ssr tdre flag is set to 1 (fixed). 2. transmission starts when, in this state, transmit data is written to tdr and the ssr tdre flag is cleared to 0. before setting the te bit to 1, be sure to set the smr to decide the transmit format. notes: 1. 2. 3. initial value clock output at same frequency as bit rate clock input at 16 times frequency of bit rate note: to clear txi interrupt requests, clear the tdre flag to 0 after reading ? 1 ? , or clear the tie bit to 0. note: * to cancel rxi and eri interrupt requests, either clear the rdrf or fer, per, or orer flags after reading ? 1 ? , or clear the rie bit to 0. note: * to cancel a tei, clear ssr tdre flag to 0 after reading tdre=1, then either clear the tend flag to 0 or clear the teie bit to 0. note: * on reception of receive data that includes mpb=0, the receive data is not sent from the rsr to the rdr, and, on detection of receive errors, the ssr rdrf, fer and orer flags are not set. on reception of receive data that includes mpb=1, the ssr mpb bit is set to 1 and the mpie bit is automatically cleared to 0. if an rxi or eri interrupt request occurs (when the scr tie or rie bit is set to 1), the fer and orer flags can be set. bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1074 of 1220 rej09b0186-0300o tdr0?transmit data register 0 tdr1?transmit data register 1 tdr2?transmit data register 2 tdr3?transmit data register 3 tdr4?transmit data register 4 h'ff7b h'ff83 h'ff8b h'fdd3 h'fddb sci0 sci1 sci2 sci3 sci4 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1075 of 1220 rej09b0186-0300o ssr0?serial status register 0 ssr1?serial status register 1 ssr2?serial status register 2 ssr3?serial status register 3 ssr4?serial status register 4 h'ff7c h'ff84 h'ff8c h'fdd4 h'fddc sci0 sci1 sci2 sci3 sci4 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r transmit data register empty (tdre) 0 [clearing conditions] ? writing 0 to tdre after reading tdre = 1 ? when data written to tdr by dmac or dtc by txi interrupt request 1 [setting conditions] ? when scr te bit = 0 ? when data is sent from tdr to tsr and data can be written to tdr receive data register full (rdrf) 0 [clearing conditions] ? writing 0 to rdrf after reading rdrf = 1 ? after reading rdr data by dmac or dtc by rxi interrupt request 1 [setting condition] ? when receive data is sent from rsr to rdr on normal completion of serial receive operation overrun error (orer) 0 [clearing condition] * 1 ? writing 0 to orer after reading orer = 1 1 [setting condition] ? on completion of next serial receive operation when rdrf = 1 * 2 framing error (fer) 0 [clearing condition] * 1 ? writing 0 to fer after reading fer = 1 1 [setting condition] ? when sci checks if the stop bit at the end of receive data is 1 on completion of receiving, the stop bit is found to be 0 parity error (per) 0 [clearing condition] * 1 ? writing 0 to per after reading per = 1 1 [setting condition] ? when receiving, when the number of 1s in receive data plus parity bit does not match the even or odd parity specified in the smr o/ e bit * 2 transmit end (tend) 0 [clearing conditions] ? writing 0 to tdre flag after reading tdre = 1 ? when data is written to tdr by dmac or dtc by txi interrupt request 1 [setting conditions] ? when scr te bit = 0 ? when tdre = 1 at transfer of last bit of any byte of serial transmit character notes: 1. the fer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. in 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. if a framing error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the fer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. notes: 1. the orer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. the receive data prior to the overrun error is retained in rdr, and the data received subsequently is lost. also, subsequen t serial reception cannot be continued while the orer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. note: rdr and the rdrf flag are not affected and retain their previous values when an error is detected during reception or whe n the re bit in scr is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost. multiprocessor bit (mpb) 0 [clearing condition] * ? when data ? multiprocessor bit = 0 ? is received 1 [setting condition] ? when data ? multiprocessor bit = 1 ? is received note: * the existing status is continued when, in multi- processor format, the scr re bit is cleared to 0. multiprocessor bit transfer (mpbt) 0 transfer data ? multiprocessor bit = 0 ? 1 transfer data ? multiprocessor bit = 1 ? notes: 1. the per flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the per flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. bit initial value r/w : : : note: * only 0 can be written to these bits (to clear these flags).
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1076 of 1220 rej09b0186-0300o rdr0?receive data register 0 rdr1?receive data register 1 rdr2?receive data register 2 rdr3?receive data register 3 rdr4?receive data register 4 h'ff7d h'ff85 h'ff8d h'fdd5 h'fddd sci0 sci1 sci2 sci3 sci4 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value r/w : : : scmr0?smart card mode register 0 scmr1?smart card mode register 1 scmr2?smart card mode register 2 scmr3?smart card mode register 3 scmr4?smart card mode register 4 h'ff7e h'ff86 h'ff8e h'fdd6 h'fdde sci0 sci1 sci2 sci3 sci4 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 ? 1 ? smart card data transfer direction 0 sends tdr contents lsb first receive data stored in rdr as lsb first 1 sends tdr contents msb first receive data stored in rdr as msb first smart card data invert 0 tdr contents are transmitted without modification receive data is stored in rdr without modification 1 tdr contents are inverted before being transmitted receive data is stored in rdr in inverted form smart card interface mode select 0 operates as normal sci (smart card interface function disabled) 1 enables smart card interface function bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1077 of 1220 rej09b0186-0300o sbycr?standby control register h'fde4 system 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ope 1 r/w 0 ? 0 ? 2 ? 0 ? 1 ? 0 ? software standby 0 when the sleep command is executed in high-speed or medium-speed modes, the operation enters sleep mode when the sleep command is executed in sub-active mode, the operation enters sub-sleep mode 1 when the sleep command is executed in high-speed and medium-speed modes, operation enters software standby mode, sub-active mode, and watch mode when the sleep command is executed in sub-active mode, operation enters watch mode and high-speed mode output port enable 0 in software standby mode, watch mode, and during direct transfer, the address bus and bus control signal are in the high-impedance state 1 in software standby mode, watch mode, and during direct transfer, the address bus and bus control signal remain in the output state standby timer select 2 to 0 sts2 sts1 sts0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 bit initial value r/w : : : standby time: 8192 states standby time: 16384 states standby time: 32768 states standby time: 65536 states standby time: 131072 states standby time: 262144 states reserved standby time: 16 states description
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1078 of 1220 rej09b0186-0300o syscr?system control register h'fde5 system 7 macs 0 r/w 6 ? 0 ? 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 mrese 0 r/w 1 ? 0 ? 0 mac saturation manual reset disabled pins p74/tmo2/ mres can be used as p74/tmo2 i/o pins manual reset enabled pins p74/tmo2/ mres can be used as mres input pins 1 non-saturating calculation for mac instruction saturating calculation for mac instruction 0 1 interrupt control mode 1, 0 internal ram disabled internal ram enabled 0 1 nmi edge select ram enable manual reset select bit 0 0 0 interrupt controlled by bit i intm0 description intm1 interrupt control mode 1 ? do not set 0 1 2 interrupt controlled by bits i2 to i0 and ipr 1 ? do not set bit initial value r/w : : : pin 0 1 1 1 res mres reset type power-on reset manual reset operation state 0 1 interrupt request issued on falling edge of nmi input interrupt request issued on rising edge of nmi input 0 1
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1079 of 1220 rej09b0186-0300o sckcr?system clock control register h'fde6 system 7 pstop 0 r/w 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 stcs 0 r/w 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w bit initial value r/w : : : clock output disable pstop high-speed mode, sleep mode, software standby mode, hardware standby medium-speed mode, sub-sleep mode watch mode, direct transition mode sub-active mode 0 output output high level (fixed) high impedance 1 high level (fixed) high level (fixed) high level (fixed) high impedance frequency multiplier switching mode select 0 specified multiplier valid after transferring to software standby mode, watch mode, and sub-active mode 1 specified multiplier valid immediately after setting value in stc bit system clock select 2 to 0 sck2 sck1 sck0 0 0 0 1 1 0 1 1 0 0 1 1 ? ? bus master set to high-speed mode. medium-speed clock: /2 medium-speed clock: //4 medium-speed clock: 8 medium-speed clock: /16 medium-speed clock: /32 description
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1080 of 1220 rej09b0186-0300o mdcr?mode control register h'fde7 system 7 ? 1 r/w 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 ? 0 ? 0 mds0 ? * r 2 mds2 ? * r 1 mds1 ? * r mode select 2 to 0 * input level determined b y mode pins. bit initial value r/w note: * determined b y pins md2 to md0. : : : mstpcra?module stop control register a h'fde8 system 7 mstpa7 0 r/w 6 mstpa6 0 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w 0 mstpa0 1 r/w module stop 0 module stop mode is cleared 1 module stop mode is set bit initial value r/w : : : mstpcrb?module stop control register b h'fde9 system 7 mstpb7 1 r/w 6 mstpb6 1 r/w 5 mstpb5 1 r/w 4 mstpb4 1 r/w 3 mstpb3 1 r/w 2 mstpb2 1 r/w 1 mstpb1 1 r/w 0 mstpb0 1 r/w module stop 0 module stop mode canceled 1 module stop mode enabled bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1081 of 1220 rej09b0186-0300o mstpcrc?module stop control register c h'fdea system 7 mstpc7 1 r/w 6 mstpc6 1 r/w 5 mstpc5 1 r/w 4 mstpc4 1 r/w 3 mstpc3 1 r/w 2 mstpc2 1 r/w 1 mstpc1 1 r/w 0 mstpc0 1 r/w module stop module stop mode canceled module stop mode enabled 0 1 bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1082 of 1220 rej09b0186-0300o pfcr?pin function control register h'fdeb system 7 css07 0 r/w 6 css36 0 r/w 5 buzze 0 r/w 4 lcass 0 r/w 3 ae3 1/0 r/w 0 ae0 1/0 r/w 2 ae2 1/0 r/w 1 ae1 0 r/w selects cs0 selects cs7 0 1 0 cs0 / cs7 select selects cs3 selects cs6 1 bit initial value r/w : : : cs3 / cs6 select functions as pf1 input pin functions as buzz output pin 0 1 buzz output enable lcas signal output from pf2 lcas signal output from pf6 0 1 lcas output pin select bit address output enable 3 to 0 * note: * in expanded mode with rom, bits ae3 to ae0 are initialized to b'0000. in romless expanded mode, bits ae3 to ae0 are initialized to b'1101. address pins a0 to a7 are made address outputs by setting the corresponding ddr bits to 1. 0 0 ae0 ae1 1 0 0 1 a8 to a23 address output disabled a8 address output enabled. a9 to a23 address output disabled a8 and a9 address output enabled. a10 to a23 address output disabled 0 ae2 0 0 0 ae3 0 0 1 1 0 0 a8 to a11 address output enabled. a12 to a23 address output disabled a8 to a10 address output enabled. a11 to a23 address output disabled a8 to a12 address output enabled. a13 to a23 address output disabled 0 1 0 0 1 0 0 1 1 1 a8 to a13 address output enabled. a14 to a23 address output disabled a8 to a14 address output enabled. a15 to a23 address output disabled a8 to a15 address output enabled. a16 to a23 address output disabled 1 1 1 0 0 0 0 0 1 0 0 1 a8 to a16 address output enabled. a17 to a23 address output disabled a8 to a17 address output enabled. a18 to a23 address output disabled a8 to a18 address output enabled. a19 to a23 address output disabled 0 0 0 1 1 1 1 1 0 0 1 0 a8 to a19 address output enabled. a20 to a23 address output disabled a8 to a20 address output enabled. a21 to a23 address output disabled 0 1 1 1 1 1 0 1 1 1 a8 to a21 address output enabled. a22 and a23 address output disabled a8 to a23 address output enabled 1 1 1 1 bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1083 of 1220 rej09b0186-0300o lpwrcr?low-power control register h'fdec system 7 dton 0 r/w 6 lson 0 r/w 5 nesel 0 r/w 4 substp 0 r/w 3 rfcut 0 r/w 0 stc0 0 r/w 2 ? 0 r/w 1 stc1 0 r/w direct transfer on flag 0 when the sleep command is executed in high-speed mode or medium-speed mode, operation transfers to sleep mode, software standby mode, or watch mode * when the sleep command is executed in sub-active mode, operation transfers to sub-sleep mode or watch mode 1 when the sleep command is executed in high-speed mode or medium-speed mode, operation transfers directly to sub-active mode * , or transfers to sleep mode or software standby mode when the sleep command is executed in sub-active mode, operation transfers directly to high-speed mode or transfers to sub-sleep mode note: * always select high-speed mode when transferring to watch mode or sub-active mode. low-speed on flag 0 when the sleep command is executed in high-speed mode or medium-speed mode, operation transfers to sleep mode, software standby mode, or watch mode * when the sleep command is executed in sub-active mode, operation transfers to watch mode, or directly to high-speed mode operation transfers to high-speed mode after watch mode is canceled 1 when the sleep command is executed in high-speed mode, operation transfers to watch mode or sub-active mode when the sleep command is executed in sub-active mode, operation transfers to sub-sleep mode or watch mode operation transfers to sub-active mode immediately watch mode is canceled note: * always select high-speed mode when transferring to watch mode or sub-active mode. a system clock frequency multiplied by the multiplication factor (stc1 and stc0) should not exceed the maximum operating frequency defined in section 25, electrical characteristics. current consumption and noise can be reduced by using this function's pll 4 setting and lowering the external clock frequency. note: noise elimination sampling frequency select 0 sampling uses /32 clock 1 sampling uses /4 clock subclock enable 0 subclock generation enabled 1 subclock generation disabled oscillator circuit feedback resistor control bit 0 feedback resistor on when main clock operating; off when not operation 1 feedback resistor off frequency multiplier stc1 stc0 0 0 1 1 2 1 0 4 1 do not set bit initial value r/w : : : bit initial value r/w : : : description
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1084 of 1220 rej09b0186-0300o bara?break address register a barb?break address register b h'fe00 h'fe04 pbc pbc ? ? 31 ? ? 24 r/w baa 23 23 0 unde- fined unde- fined r/w baa 22 22 0 r/w baa 21 21 0 r/w baa 20 20 0 r/w baa 19 19 0 r/w baa 18 18 0 r/w baa 17 17 0 r/w baa 16 16 0 r/w 0 baa 7 7 r/w 0 baa 6 6 r/w 0 baa 5 5 r/w 0 baa 4 4 r/w 0 baa 3 3 r/w 0 baa 2 2 r/w 0 baa 1 1 r/ w 0 baa 0 0 break address 23 to 0 note: the bit confi g uration of barb is the same as that of bara. bit : initial value r/w : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1085 of 1220 rej09b0186-0300o bcra?break control register a bcrb?break control register b h'fe08 h'fe09 pbc pbc r/(w) * 0 cmfa 7 r/w 0 cda 6 r/w 0 bamra2 5 r/w 0 bamra1 4 r/w 0 bamra0 3 r/w 0 csela1 2 r/w 0 csela0 1 r/w 0 biea 0 notes: the bit configuration of bcrb is the same as that of bcra. * only 0 can be written to these bits (to clear these flags). bamra 0 0 1 all bits, without masking bara, included in break condition baa0 (lsb) masked and not included in break condition baa1 and baa0 (low 2 bits) masked and not included in break condition baa2 to baa0 (low 3 bits) masked and not included in break condition baa3 to baa0 (low 4 bits) masked and not included in break condition baa7 to baa0 (low 8 bits) masked and not included in break condition baa11 to baa0 (low 12 bits) masked and not included in break condition baa15 to baa0 (low 16 bits) masked and not included in break condition 0 bamra 1 0 0 bamra 2 0 0 1 0 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 when the cpu is the bus master, pc break performed when the cpu or dtc is the bus master, pc break performed 0 1 [clearing condition] writing 0 to cmfa after reading cmfa = 1 [setting condition] when channel a conditions are true 0 1 condition match flag a cpu cycle/dtc cycle select a break address mask register a2 to a0 disables pc break interrupt enables pc break interrupt 0 1 break interrupt enable break condition select 0 0 csela0 description description sets instruction fetch as break condition sets data read cycle as break condition sets data write cycle as break condition sets data read/write cycle as break condition csela1 1 0 0 1 1 1 bit : initial value r/w : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1086 of 1220 rej09b0186-0300o iscrh?irq sense control register h iscrl?irq sense control register l h'fe12 h'fe13 interrupt controller interrupt controller 15 irq7scb 0 r/w 14 irq7sca 0 r/w 13 irq6scb 0 r/w 12 irq6sca 0 r/w 11 irq5scb 0 r/w 8 irq4sca 0 r/w 10 irq5sca 0 r/w 9 irq4scb 0 r/w 7 irq3scb 0 r/w 6 irq3sca 0 r/w 5 irq2scb 0 r/w 4 irq2sca 0 r/w 3 irq1scb 0 r/w 0 irq0sca 0 r/w 2 irq1sca 0 r/w 1 irq0scb 0 r/w bit initial value r/w : : : iscrl bit initial value r/w : : : iscrh irq7 sense control a, b to irq0 sense control a, 0 0 interrupt request issued when irq7 to irq0 input level low interrupt request issued on falling edge of irq7 to irq0 input interrupt request issued on rising edge of irq7 to irq0 input interrupt request issued on both falling and rising edges of irq7 to irq0 input irq7sca to irq0sca description irq7scb to irq0scb 1 0 1 1 ier?irq enable register h'fe14 interrupt controller 7 irq7e 0 r/w 6 irq6e 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 0 irq0e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w irq7 to ira0 enable disables irqn interrupt enables irqn interrupt 0 1 (n = 7 to 0) bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1087 of 1220 rej09b0186-0300o isr?irq status register h'fe15 interrupt controller 7 irq7f 0 r/(w) * 6 irq6f 0 r/(w) * 5 irq5f 0 r/(w) * 4 irq4f 0 r/(w) * 3 irq3f 0 r/(w) * 0 irq0f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * note: * onl y 0 can be written to these bits ( to clear these fla g s ) . irq7 to irq0 flag 0 1 (n = 7 to 0) bit initial value r/w : : : [clearing conditions] ? writing 0 to flag irqnf after reading irqnf = 1 ? when interrupt exception processing is executed when set for low-level detection (irqnscb = irqnsca = 0) and, in addition, the irqn input level is high ? when irqn interrupt exception processing is executed when set for rising edge or falling edge or both rising edge and falling edge detection (irqnscb = 1 and irqnsca = 1) ? when the dtc starts due to irqn interrupt and the dtc mrb disel bit is 0 [setting conditions] ? when the irqn input level changes to low when set for low level detection (irqnscb = irqnsca = 0) ? when a falling edge occurs at the irqn input when set for falling edge detection (irqnscb = 0, irqnsca = 1) ? when a rising edge occurs at the irqn input when set for rising edge detection (irqnscb = 1, irqnsca = 0) ? when either a falling edge or rising edge occurs at the irqn input when set for both falling edge and rising edge detection (irqnscb = irqnsca = 1)
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1088 of 1220 rej09b0186-0300o dtcer?dtc enable register h'fe16 to h'fe1e dtc 7 dtce7 0 r/w 6 dtce6 0 r/w 5 dtce5 0 r/w 4 dtce4 0 r/w 3 dtce3 0 r/w 0 dtce0 0 r/w 2 dtce2 0 r/w 1 dtce1 0 r/w dtc activation by interrupt disabled [clearing conditions] when data transmission ends with the disel bit = 1 on completion of the specified number of transmissions 0 1 dtc activation enable 0 dtc activation by interrupt enabled [holding condition] when disel = 0 and the specified number of transmissions has not completed (n = 7 to 0) bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1089 of 1220 rej09b0186-0300o dtvecr?dtc vector register h'fe1f dtc 7 swdte 0 r/(w) * 1 6 dtvec6 0 r/(w) * 2 5 dtvec5 0 r/(w) * 2 4 dtvec4 0 r/(w) * 2 3 dtvec3 0 r/(w) * 2 0 dtvec0 0 r/(w) * 2 2 dtvec2 0 r/(w) * 2 1 dtvec1 0 r/(w) * 2 notes: 1. 2. only 1 can be written to the swdte bit. dtvec6 to dtvec0 can be written to when swdte = 0. dtc software startup enable dtc software startup disabled [clearing conditions] when disel = 0 and the specified number of transmissions has not completed when 0 is written after a software startup data transmit end interrupt (swdtend) request is sent to the cpu 0 1 dtc software startup vector 6 to 0 0 dtc software startup enabled [retention conditions] when disel = 1 and data transmission ends on completion of the specified number of transmissions during data transmission by software startup bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1090 of 1220 rej09b0186-0300o pcr?ppg output control register h'fe26 ppg 7 g3cms1 1 r/w 6 g3cms0 1 r/w 5 g2cms1 1 r/w 4 g2cms0 1 r/w 3 g1cms1 1 r/w 0 g0cms0 1 r/w 2 g1cms0 1 r/w 1 g0cms1 1 r/w bit initial value r/w : : : group 0 compare match select 1, 0 group 3 compare match select 1, 0 0 0 tpu channel 0 compare match g3cms0 g3cms1 1 tpu channel 1 compare match 0 1 tpu channel 2 compare match 1 tpu channel 3 compare match pulse output group 3 output trigger group 1 compare match select 1, 0 0 0 tpu channel 0 compare match g1cms0 g1cms1 1 tpu channel 1 compare match 0 1 tpu channel 2 compare match 1 tpu channel 3 compare match pulse output group 1 output trigger 0 0 tpu channel 0 compare match g0cms0 g0cms1 1 tpu channel 1 compare match 0 1 tpu channel 2 compare match 1 tpu channel 3 compare match pulse output group 0 output trigger group 2 compare match select 1, 0 0 0 tpu channel 0 compare match g2cms0 g2cms1 1 tpu channel 1 compare match 0 1 tpu channel 2 compare match 1 tpu channel 3 compare match pulse output group 2 output trigger
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1091 of 1220 rej09b0186-0300o pmr?ppg output mode register h'fe27 ppg 7 g3inv 1 r/w 6 g2inv 1 r/w 5 g1inv 1 r/w 4 g0inv 1 r/w 3 g3nov 0 r/w 0 g0nov 0 r/w 2 g2nov 0 r/w 1 g1nov 0 r/w group 3 inversion group 0 non-overlap group 2 inversion group 1 inversion group 0 inversion group 1 non-overlap group 2 non-overlap group 3 non-overlap pulse output group 0 set for inverted output (pin output level is set low when podrl = 1) 0 1 0 pulse output group 0 set for direct output (pin output level is set high when podrl = 1) pulse output group 1 set for inverted output (pin output level is set low when podrl = 1) 0 1 0 pulse output group 1 set for direct output (pin output level is set high when podrl = 1) pulse output group 2 set for inverted output (pin output level is set low when podrh = 1) 0 1 0 pulse output group 2 set for direct output (pin output level is set high when podrh = 1) pulse output group 3 set for inverted output (pin output level is set low when podrh = 1) 0 1 0 pulse output group 3 set for direct output (pin output level is set high when podrh = 1) pulse output group 3 set for normal operation (output value updated on compare match a for selected tpu) 0 1 0 pulse output group 3 set for non-overlap operation (1 output and 0 output can be output independently on compare matches a and b of selected tpu) pulse output group 2 set for normal operation (output value updated on compare match a for selected tpu) 0 1 pulse output group 2 set for non-overlap operation (1 output and 0 output can be output independently on compare matches a and b of selected tpu) pulse output group 1 set for normal operation (output value updated on compare match a for selected tpu) 0 1 pulse output group 1 set for non-overlap operation (1 output and 0 output can be output independently on compare matches a and b of selected tpu) pulse output group 0 set for normal operation (output value updated on compare match a for selected tpu) 0 1 pulse output group 0 set for non-overlap operation (1 output and 0 output can be output independently on compare matches a and b of selected tpu) bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1092 of 1220 rej09b0186-0300o nderh?next data enable register h nderl?next data enable register l h'fe28 h'fe29 ppg ppg 7 nder15 0 r/w 6 nder14 0 r/w 5 nder13 0 r/w 4 nder12 0 r/w 3 nder11 0 r/w 0 nder8 0 r/w 2 nder10 0 r/w 1 nder9 0 r/w nderh 7 nder7 0 r/w 6 nder6 0 r/w 5 nder5 0 r/w 4 nder4 0 r/w 3 nder3 0 r/w 0 nder0 0 r/w 2 nder2 0 r/w 1 nder1 0 r/w nderl next data enable 15 to 8 0 1 nder15 to nder8 description description pulse output po15 to po8 disabled (transfer from ndr15-ndr8 to pod15-pod8 disabled) pulse output po15 to po8 enabled (transfer from ndr15-ndr8 to pod15-pod8 enabled) next data enable 7 to 0 0 1 nder7 to nder0 pulse output po7 to po0 disabled (transfer from ndr7-ndr0 to pod7-pod0 disabled) pulse output po7 to po0 enabled (transfer from ndr7-ndr0 to pod7-pod0 enabled) bit initial value r/w : : : bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1093 of 1220 rej09b0186-0300o podrh?output data register h podrl?output data register l h'fe2a h'fe2b ppg ppg 7 pod15 0 r/(w) * 6 pod14 0 r/(w) * 5 pod13 0 r/(w) * 4 pod12 0 r/(w) * 3 pod11 0 r/(w) * 0 pod8 0 r/(w) * 2 pod10 0 r/(w) * 1 pod9 0 r/(w) * podrh 7 pod7 0 r/(w) * 6 pod6 0 r/(w) * 5 pod5 0 r/(w) * 4 pod4 0 r/(w) * 3 pod3 0 r/(w) * 0 pod0 0 r/(w) * 2 pod2 0 r/(w) * 1 pod1 0 r/(w) * note: * the bits set for pulse output by nder are read-only bits. podrl bit initial value r/w : : : bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1094 of 1220 rej09b0186-0300o ndrh?next data register h h'fe2c, h'fe2e ppg 7 ndr15 0 r/w 6 ndr14 0 r/w 5 ndr13 0 r/w 4 ndr12 0 r/w 3 ndr11 0 r/w 0 ndr8 0 r/w 2 ndr10 0 r/w 1 ndr9 0 r/w bit initial value r/w address: h'fe2c address: h'fe2e address: h'fe2e address: h'fe2c same trigger for pulse output groups: : : : 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 ? 1 ? 2 ? 1 ? 1 ? 1 ? bit initial value r/w : : : 7 ndr15 0 r/w 6 ndr14 0 r/w 5 ndr13 0 r/w 4 ndr12 0 r/w 3 ? 1 ? 0 ? 1 ? 2 ? 1 ? 1 ? 1 ? bit initial value r/w different triggers for pulse output groups: : : : 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ndr11 0 r/w 0 ndr8 0 r/w 2 ndr10 0 r/w 1 ndr9 0 r/w bit initial value r/w : : : note: for details see section 12.2.4, notes on ndr access.
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1095 of 1220 rej09b0186-0300o ndrl?next data register l h'fe2d, h'fe2f ppg 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 ? 1 ? 2 ? 1 ? 1 ? 1 ? bit initial value r/w : : : 7 ndr7 0 r/w 6 ndr6 0 r/w 5 ndr5 0 r/w 4 ndr4 0 r/w 3 ndr3 0 r/w 0 ndr0 0 r/w 2 ndr2 0 r/w 1 ndr1 0 r/w bit initial value r/w : : : 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ndr3 0 r/w 0 ndr0 0 r/w 2 ndr2 0 r/w 1 ndr1 0 r/w bit initial value r/w : : : 7 ndr7 0 r/w 6 ndr6 0 r/w 5 ndr5 0 r/w 4 ndr4 0 r/w 3 ? 1 ? 0 ? 1 ? 2 ? 1 ? 1 ? 1 ? bit initial value r/w different triggers for pulse output groups: note: for details see section 12.2.4, notes on ndr access. same trigger for pulse output groups: : : : address: h'fe2d address: h'fe2d address: h'fe2f address: h'fe2f
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1096 of 1220 rej09b0186-0300o p1ddr?port 1 data direction register h'fe30 port 7 p17ddr 0 w 6 p16ddr 0 w 5 p15ddr 0 w 4 p14ddr 0 w 3 p13ddr 0 w 0 p10ddr 0 w 2 p12ddr 0 w 1 p11ddr 0 w bit initial value r/w : : : p2ddr?port 2 data direction register h'fe31 port 7 p27ddr 0 w bit initial value r/w : : : 6 p26ddr 0 w 5 p25ddr 0 w 4 p24ddr 0 w 3 p23ddr 0 w 2 p22ddr 0 w 1 p21ddr 0 w 0 p20ddr 0 w p3ddr?port 3 data direction register h'fe32 port 7 p37ddr 0 w 6 p36ddr 0 w 5 p35ddr 0 w 4 p34ddr 0 w 3 p33ddr 0 w 0 p30ddr 0 w 2 p32ddr 0 w 1 p31ddr 0 w bit initial value r/w : : : p5ddr?port 5 data direction register h'fe34 port 7 ? undefined ? bit initial value r/w : : : 6 ? undefined ? 5 ? undefined ? 4 ? undefined ? 3 ? undefined ? 2 p52ddr 0 w 1 p51ddr 0 w 0 p50ddr 0 w p7ddr?port 7 data direction register h'fe36 port 7 p77ddr 0 w 6 p76ddr 0 w 5 p75ddr 0 w 4 p74ddr 0 w 3 p73ddr 0 w 0 p70ddr 0 w 2 p72ddr 0 w 1 p71ddr 0 w bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1097 of 1220 rej09b0186-0300o p8ddr?port 8 data direction register h'fe37 port 7 ? undefined ? bit initial value r/w : : : 6 p86ddr 0 w 5 p85ddr 0 w 4 p84ddr 0 w 3 p83ddr 0 w 2 p82ddr 0 w 1 p81ddr 0 w 0 p80ddr 0 w paddr?port a data direction register h'fe39 port 7 pa7ddr 0 w 6 pa6ddr 0 w 5 pa5ddr 0 w 4 pa4ddr 0 w 3 pa3ddr 0 w 0 pa0ddr 0 w 2 pa2ddr 0 w 1 pa1ddr 0 w bit initial value r/w : : : pbddr?port b data direction register h'fe3a port 7 pb7ddr 0 w 6 pb6ddr 0 w 5 pb5ddr 0 w 4 pb4ddr 0 w 3 pb3ddr 0 w 0 pb0ddr 0 w 2 pb2ddr 0 w 1 pb1ddr 0 w bit initial value r/w : : : pcddr?port c data direction register h'fe3b port 7 pc7ddr 0 w 6 pc6ddr 0 w 5 pc5ddr 0 w 4 pc4ddr 0 w 3 pc3ddr 0 w 0 pc0ddr 0 w 2 pc2ddr 0 w 1 pc1ddr 0 w bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1098 of 1220 rej09b0186-0300o pdddr?port d data direction register h'fe3c port 7 pd7ddr 0 w 6 pd6ddr 0 w 5 pd5ddr 0 w 4 pd4ddr 0 w 3 pd3ddr 0 w 0 pd0ddr 0 w 2 pd2ddr 0 w 1 pd1ddr 0 w bit initial value r/w : : : peddr?port e data direction register h'fe3d port 7 pe7ddr 0 w 6 pe6ddr 0 w 5 pe5ddr 0 w 4 pe4ddr 0 w 3 pe3ddr 0 w 0 pe0ddr 0 w 2 pe2ddr 0 w 1 pe1ddr 0 w bit initial value r/w : : : pfddr?port f data direction register h'fe3e port 7 pf7ddr 1 w 0 w 6 pf6ddr 0 w 0 w 5 pf5ddr 0 w 0 w 4 pf4ddr 0 w 0 w 3 pf3ddr 0 w 0 w 0 pf0ddr 0 w 0 w 2 pf2ddr 0 w 0 w 1 pf1ddr 0 w 0 w bit modes 4 to 6 initial value r/w mode 7 initial value r/w : : : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1099 of 1220 rej09b0186-0300o pgddr?port g data direction register h'fe3f port 7 ? undefined ? undefined ? 6 ? undefined ? undefined ? 5 ? undefined ? undefined ? 4 pg4ddr 1 w 0 w 3 pg3ddr 0 w 0 w 0 pg0ddr 0 w 0 w 2 pg2ddr 0 w 0 w 1 pg1ddr 0 w 0 w bit modes 4 and 5 initial value r/w modes 6 and 7 initial value r/w : : : : : papcr?port a pull-up mos control register h'fe40 port 7 pa7pcr 0 r/w 6 pa6pcr 0 r/w 5 pa5pcr 0 r/w 4 pa4pcr 0 r/w 3 pa3pcr 0 r/w 0 pa0pcr 0 r/w 2 pa2pcr 0 r/w 1 pa1pcr 0 r/w bit initial value r/w : : : pbpcr?port b pull-up mos control register h'fe41 port 7 pb7pcr 0 r/w 6 pb6pcr 0 r/w 5 pb5pcr 0 r/w 4 pb4pcr 0 r/w 3 pb3pcr 0 r/w 0 pb0pcr 0 r/w 2 pb2pcr 0 r/w 1 pb1pcr 0 r/w bit initial value r/w : : : pcpcr?port c pull-up mos control register h'fe42 port 7 pc7pcr 0 r/w 6 pc6pcr 0 r/w 5 pc5pcr 0 r/w 4 pc4pcr 0 r/w 3 pc3pcr 0 r/w 0 pc0pcr 0 r/w 2 pc2pcr 0 r/w 1 pc1pcr 0 r/w bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1100 of 1220 rej09b0186-0300o pdpcr?port d pull-up mos control register h'fe43 port 7 pd7pcr 0 r/w 6 pd6pcr 0 r/w 5 pd5pcr 0 r/w 4 pd4pcr 0 r/w 3 pd3pcr 0 r/w 0 pd0pcr 0 r/w 2 pd2pcr 0 r/w 1 pd1pcr 0 r/w bit initial value r/w : : : pepcr?port e pull-up mos control register h'fe44 port 7 pe7pcr 0 r/w 6 pe6pcr 0 r/w 5 pe5pcr 0 r/w 4 pe4pcr 0 r/w 3 pe3pcr 0 r/w 0 pe0pcr 0 r/w 2 pe2pcr 0 r/w 1 pe1pcr 0 r/w bit initial value r/w : : : p3odr?port 3 open-drain control register h'fe46 port 7 p37odr 0 r/w 6 p36odr 0 r/w 5 p35odr 0 r/w 4 p34odr 0 r/w 3 p33odr 0 r/w 0 p30odr 0 r/w 2 p32odr 0 r/w 1 p31odr 0 r/w bit initial value r/w : : : paodr?port a open drain control register h'fe47 port 7 pa7odr 0 r/w 6 pa6odr 0 r/w 5 pa5odr 0 r/w 4 pa4odr 0 r/w 3 pa3odr 0 r/w 0 pa0odr 0 r/w 2 pa2odr 0 r/w 1 pa1odr 0 r/w bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1101 of 1220 rej09b0186-0300o pbodr?port b open drain control register h'fe48 port 7 pb7odr 0 r/w 6 pb6odr 0 r/w 5 pb5odr 0 r/w 4 pb4odr 0 r/w 3 pb3odr 0 r/w 0 pb0odr 0 r/w 2 pb2odr 0 r/w 1 pb1odr 0 r/w bit initial value r/w : : : pcodr?port c open drain control register h'fe49 port 7 pc7odr 0 r/w 6 pc6odr 0 r/w 5 pc5odr 0 r/w 4 pc4odr 0 r/w 3 pc3odr 0 r/w 0 pc0odr 0 r/w 2 pc2odr 0 r/w 1 pc1odr 0 r/w bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1102 of 1220 rej09b0186-0300o tcr0?timer control register 0 tcr3?timer control register 3 h'ff10 h'fe80 tpu0 tpu3 7 cclr2 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w channel 0: tcr0 channel 3: tcr3 counter clear 2, 1, 0 clock edge 1, 0 0 0 tcnt clearing disabled cclr1 cclr2 tcnt cleared at tgra compare match/input capture 1 tcnt cleared at tgrb compare match/input capture 0 cclr0 1 0 0 1 tcnt clearing disabled 0 1 tcnt cleared at tgrc compare match/input capture * 2 1 tcnt cleared when other channel counters with synchronized clearing or synchronized operation are cleared * 1 1 tcnt cleared at tgrd compare match/input capture * 2 0 1 tcnt cleared when other channel counters with synchronized clearing or synchronized operation are cleared * 1 time prescaler 2, 1, 0 tcr0 tcr3 0 0 internal clock: counts on /1 internal clock: counts on /4 1 internal clock: counts on /16 0 1 0 0 1 external clock: counts on tclka pin input 0 1 internal clock: counts on /1024 1 internal clock: counts on /64 1 internal clock: counts on /256 0 1 internal clock: counts on /4096 0 0 internal clock: counts on /1 internal clock: counts on /4 1 internal clock: counts on /16 0 1 0 0 1 external clock: counts on tclka pin input 0 1 external clock: counts on tclkb pin input 1 internal clock: counts on /64 1 external clock: counts on tclkc pin input 0 1 external clock: counts on tclkd pin input 0 0 counts on rising edge ckeg0 description description ckeg1 1 counts on falling edge ? 1 counts on both edges note: internal clock edge selection is valid only when the input clock is ? /4 or slower. this setting is ignored when the input clock is ? /1 or an overflow or underflow in another channel is selected. bit initial value r/w : : : notes: 1. synchronous operation setting is performed by setting the sync bit in tsyr to 1. 2. when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur.
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1103 of 1220 rej09b0186-0300o tmdr0?timer mode register 0 tmdr3?timer mode register 3 h'ff11 h'fe81 tpu0 tpu3 7 ? 1 ? 6 ? 1 ? 5 bfb 0 r/w 4 bfa 0 r/w 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w channel 0: tmdr0 channel 3: tmdr3 normal tgrb operation buffer operation of tgrb and tgrd 0 1 normal tgra operation buffer operation of tgra and tgrc normal operation reserved pwm mode 1 pwm mode 2 phase calculation mode 1 phase calculation mode 2 phase calculation mode 3 phase calculation mode 4 0 1 buffer operation b mode 3 to 0 buffer operation a 0 1 0 md0 description md1 md2 * 2 0 0 1 1 0 0 1 ? 1 0 1 1 * * * md3 * 1 0 1 * : don't care notes: 1. 2. md3 is a reserved bit. only write 0 to this bit. phase calculation mode cannot be set for channels 0 and 3. only write 0 to md2. bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1104 of 1220 rej09b0186-0300o tior3h?timer i/o control register 3h h'fe82 tpu3 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value r/w : : : * : don't care tgr3a i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt4 count-up/ count-down tgr3a is output compare register tgr3a is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tioca3 pin capture input source is channel 4/count clock 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * * : don't care tgr3b i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt4 count-up/ count-down * 1 tgr3b is output compare register tgr3b is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocb3 pin capture input source is channel 4/count clock 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * note: 1. when bits tpsc2 to tpsc0 in tcr4 are set to b'000 and /1 is used as the tcnt4 count clock, this setting is invalid and input capture is not generated.
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1105 of 1220 rej09b0186-0300o tior4?timer i/o control register 4h'fe92 tpu4 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w * : don't care tgr4a i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at generation of tgr3a compare match/input capture tgr4a is output compare register tgr4a is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tioca4 pin capture input source is tgr3a compare match/ input capture 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * * : don't care tgr4b i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at generation of tgr3c compare match/input capture tgr4b is output compare register tgr4b is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocb4 pin capture input source is tgr3c compare match/ input capture 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1106 of 1220 rej09b0186-0300o tior5?timer i/o control register 5h'fea2 tpu5 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w * : don't care tgr5a i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges tgr5a is output compare register tgr5a is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tioca5 pin 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 * * : don't care tgr5b i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges tgr5b is output compare register tgr5b is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocb5 pin 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 * bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1107 of 1220 rej09b0186-0300o tior0h?timer i/o control register 0h h'ff12 tpu0 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w * : don't care tgr0a i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt1 count-up/ count-down tgr0a is output compare register tgr0a is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tioca0 pin capture input source is channel 1/count clock 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * * : don't care tgr0b i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt1 count-up/ count-down * 1 tgr0b is output compare register tgr0b is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocb0 pin capture input source is channel 1/count clock 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * note: 1. when bits tpsc2 to tpsc0 in tcr1 are set to b'000 and /1 is used as the tcnt1 count clock, this settin g is invalid and input capture is not g enerated. bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1108 of 1220 rej09b0186-0300o tior1?timer i/o control register 1 h'ff22 tpu1 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w * : don't care tgr1a i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at generation of channel 0/tgr0a compare match/ input capture tgr1a is output compare register tgr1a is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tioca1 pin capture input source is tgr0a compare match/ input capture 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * * : don't care tgr1b i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at generation of tgr0c compare match/input capture tgr1b is output compare register tgr1b is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocb1 pin capture input source is tgr0c compare match/ input capture 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1109 of 1220 rej09b0186-0300o tior2?timer i/o control register 2 h'ff32 tpu2 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w * : don't care tgr2a i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges tgr2a is output compare register tgr2a is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tioca2 pin 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 * * : don't care tgr2b i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges tgr2b is output compare register tgr2b is input capture register output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocb2 pin 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 * bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1110 of 1220 rej09b0186-0300o tior3l?timer i/o control register 3l h'fe83 tpu3 7 iod3 0 r/w 6 iod2 0 r/w 5 iod1 0 r/w 4 iod0 0 r/w 3 ioc3 0 r/w 0 ioc0 0 r/w 2 ioc2 0 r/w 1 ioc1 0 r/w * : don't care tgr3c i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt4 count-up/ count-down tgr3c is output compare register * 1 tgr3c is input capture register * 1 output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocc3 pin capture input source is channel 4/count clock 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * * : don't care tgr3d i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt4 count-up/ count-down * 1 tgr3d is output compare register * 2 tgr3d is input capture register * 2 output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocd3 pin capture input source is channel 4/count clock 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * notes: 1. 2. when bits tpsc2 to tpsc0 in tcr4 are set to b'000 and /1 is used as the tcnt4 count clock, this setting is invalid and input capture is not generated. when the bfb bit in tmdr3 is set to 1 and tgr3d is used as a buffer register, this setting is invalid and input capture/output compare is not generated. note: when tgrc or tgrd is designated for buffer operation, this setting is invalid and the register operates as a buffer register. note: 1. when the bfa bit in tmdr3 is set to 1 and tgr3c is used as a buffer register, this setting is invalid and input capture/output compare is not generated. bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1111 of 1220 rej09b0186-0300o tior0l?timer i/o control register 0l h'ff13 tpu0 7 iod3 0 r/w 6 iod2 0 r/w 5 iod1 0 r/w 4 iod0 0 r/w 3 ioc3 0 r/w 0 ioc0 0 r/w 2 ioc2 0 r/w 1 ioc1 0 r/w * : don't care tgr0c i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt1 count-up/ count-down tgr0c is output compare register * 1 tgr0c is input capture register * 1 output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocc0 pin capture input source is channel 1/count clock 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * * : don't care tgr0d i/o control 0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt1 count-up/ count-down * 1 tgr0d is output compare register * 2 tgr0d is input capture register * 2 output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocd0 pin capture input source is channel 1/count clock 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * notes: 1. 2. when bits tpsc2 to tpsc0 in tcr1 are set to b'000 and /1 is used as the tcnt1 count clock, this setting is invalid and input capture is not generated. when the bfb bit in tmdr0 is set to 1 and tgr0d is used as a buffer register, this setting is invalid and input capture/output compare is not generated. note: 1. when the bfa bit in tmdr0 is set to 1 and tgr0c is used as a buffer register, this setting is invalid and input capture/output compare is not generated. note: when tgrc or tgrd is designated for buffer operation, this setting is invalid and the re g ister operates as a buffer re g ister. bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1112 of 1220 rej09b0186-0300o tier0?timer interrupt enable register 0 tier3?timer interrupt enable register 3 h'ff14 h'fe84 tpu0 tpu3 7 ttge 0 r/w 6 ? 1 ? 5 ? 0 ? 4 tciev 0 r/w 3 tgied 0 r/w 0 tgiea 0 r/w 2 tgiec 0 r/w 1 tgieb 0 r/w channel 0: tier0 channel 3: tier3 a/d conversion start request enable tgfa bit interrupt request (tgia) disabled tgfa bit interrupt request (tgia) enabled 0 1 tgr interrupt enable a overflow interrupt enable tgfb bit interrupt request (tgib) disabled tgfb bit interrupt request (tgib) enabled 0 1 tgfd bit interrupt request (tgid) disabled tgfd bit interrupt request (tgid) enabled 0 1 a/d conversion start request generation disabled a/d conversion start request generation enabled 0 1 tcfv interrupt request (tciv) disabled tcfv interrupt request (tciv) enabled 0 1 tgr interrupt enable b tgfc bit interrupt request (tgic) disabled tgfc bit interrupt request (tgic) enabled 0 1 tgr interrupt enable c tgr interrupt enable d bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1113 of 1220 rej09b0186-0300o tsr0?timer status register 0 tsr3?timer status register 3 h'ff15 h'fe85 tpu0 tpu3 7 ? 1 ? 6 ? 1 ? 5 ? 0 ? 4 tcfv 0 r/(w) * 3 tgfd 0 r/(w) * 0 tgfa 0 r/(w) * 2 tgfc 0 r/(w) * 1 tgfb 0 r/(w) * note: * onl y 0 can be written to these bits ( to clear these fla g s ) . channel 0: tsr0 channel 3: tsr3 input capture/output compare flag a overflow flag input capture/output compare flag b input capture/output compare flag c input capture/output compare flag d [clearing conditions] ? when the dtc is started by a tgid interrupt and the dtc mrb disel bit is 0 ? writing 0 to tgfd after reading tgfd = 1 [setting conditions] ? when tgrd is functioning as the output compare register and tcnt = tgrd ? when tgrd is functioning as the input capture register and the value of tcnt is sent to tgrd by the input capture signal 0 1 [clearing conditions] ? when the dtc is started by a tgic interrupt and the dtc mrb disel bit is 0 ? writing 0 to tgfc after reading tgfc = 1 [setting conditions] ? when tgrc is functioning as the output compare register and tcnt = tgrc ? when tgrc is functioning as the input capture register and the value of tcnt is sent to tgrc by the input capture signal 0 1 [clearing conditions] ? when the dtc is started by a tgib interrupt and the dtc mrb disel bit is 0 ? writing 0 to tgfb after reading tgfb = 1 [setting conditions] ? when tgrb is functioning as the output compare register and tcnt = tgrb ? when tgrb is functioning as the input capture register and the value of tcnt is sent to tgrb by the input capture signal 0 1 0 1 [clearing condition] ? writing 0 to tcfv after reading tcfv = 1 [setting condition] ? when the tcnt value overflows (h?ffff h?0000) 0 1 0 bit initial value r/w : : : [clearing conditions] ? when the dtc is started by a tgia interrupt and the dtc mrb disel bit is 0 ? when the dmac is started by a tgia interrupt and the dmac dmabcr dta bit is 1 ? writing 0 to tgfa after reading tgfa = 1 [setting conditions] ? when tgra is functioning as the output compare register and tcnt = tgra ? when tgra is functioning as the input capture register and the value of tcnt is sent to tgra by the input capture signal
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1114 of 1220 rej09b0186-0300o tcnt0?timer counter 0 (up-counter) tcnt0?timer counter 1 (up/down-counter * ) tcnt0?timer counter 2 (up/down-counter * ) tcnt0?timer counter 3 (up-counter) tcnt0?timer counter 4 (up/down-counter * ) tcnt0?timer counter 5 (up/down-counter * ) h'ff16 h'ff26 h'ff36 h'fe86 h'fe96 h'fea6 tpu0 tpu1 tpu2 tpu3 tpu4 tpu5 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w note: * this register can be used as an up/down counter only in phase calculation mode (and when counting overflows and underflows in other channels in phase calculation mode) in all other cases, this register functions as an up-counter. bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1115 of 1220 rej09b0186-0300o tgr0a?timer general register 0a tgr0b?timer general register 0b tgr0c?timer general register 0c tgr0d?timer general register 0d tgr1a?timer general register 1a tgr1b?timer general register 1b tgr2a?timer general register 2a tgr2b?timer general register 2b tgr3a?timer general register 3a tgr3b?timer general register 3b tgr3c?timer general register 3c tgr3d?timer general register 3d tgr4a?timer general register 4a tgr4b?timer general register 4b tgr5a?timer general register 5a tgr5b?timer general register 5b h'ff18 h'ff1a h'ff1c h'ff1e h'ff28 h'ff2a h'ff38 h'ff3a h'fe88 h'fe8a h'fe8c h'fe8e h'fe98 h'fe9a h'fea8 h'feaa tpu0 tpu0 tpu0 tpu0 tpu1 tpu1 tpu2 tpu2 tpu3 tpu3 tpu3 tpu3 tpu4 tpu4 tpu5 tpu5 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1116 of 1220 rej09b0186-0300o tcr1?timer control register 1 tcr2?timer control register 2 tcr4?timer control register 4 tcr5?timer control register 5 h'ff20 h'ff30 h'fe90 h'fea0 tpu1 tpu2 tpu4 tpu5 7 ? 0 ? 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w channel 1: tcr1 channel 2: tcr2 channel 4: tcr4 channel 5: tcr5 clock edge 1, 0 0 0 tcnt clearing disabled cclr0 cclr1 0 reserve * 2 1 tcnt cleared at tgra compare match/input capture 0 1 tcnt cleared at tgrb compare match/input capture 1 tcnt cleared when other channel counters with synchronized clearing or synchronized operation are cleared * 1 counter clear 2, 1, 0 0 0 counts on rising edge ckeg0 description description ckeg1 1 counts on falling edge ? 1 counts on both edges note: internal clock edge selection is valid only when the input clock is /4 or slower. this setting is ignored when the input clock is /1 or an overflow or underflow in another channel is selected. notes: 1. 2. sync operation is selected by setting 1 in the tsyr sync bit. bit 7 of channels 1 , 2 , 4 , and 5 is reserved. this bit alwa y s returns 0 when read , and cannot be written to . bit initial value r/w : : : time prescaler 2, 1, 0 tcr1 tcr2 0 0 internal clock: counts on /1 internal clock: counts on /4 1 internal clock: counts on /16 0 1 0 0 1 external clock: counts on tclka pin input 0 1 external clock: counts on tclkb pin input 1 internal clock: counts on /64 1 external clock: counts on tclkc pin input 0 1 internal clock: counts on /1024 0 0 internal clock: counts on /1 internal clock: counts on /4 1 internal clock: counts on /16 0 1 0 0 1 external clock: counts on tclka pin input 0 1 external clock: counts on tclkb pin input 1 internal clock: counts on /64 1 internal clock: counts on /256 0 1 counts on tcnt2 overflow/underflow tcr4 note: this setting is ignored when channel 2 is in phase counting mode. note: this setting is ignored when channel 1 is in phase counting mode. tcr5 note: this setting is ignored when channel 4 is in phase counting mode. note: this setting is ignored when channel 5 is in phase counting mode. 0 0 internal clock: counts on /1 internal clock: counts on /4 1 internal clock: counts on /16 0 1 0 0 1 external clock: counts on tclka pin input 0 1 external clock: counts on tclkc pin input 1 internal clock: counts on /64 1 internal clock: counts on /256 0 1 external clock: counts on tclkd pin input 0 0 internal clock: counts on /1 internal clock: counts on ? /4 1 internal clock: counts on /16 0 1 0 0 1 external clock: counts on tclka pin input 0 1 external clock: counts on tclkc pin input 1 internal clock: counts on /64 1 internal clock: counts on /1024 0 1 counts on tcnt5 overflow/underflow
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1117 of 1220 rej09b0186-0300o tmdr1?timer mode register 1 tmdr2?timer mode register 2 tmdr4?timer mode register 4 tmdr5?timer mode register 5 h'ff21 h'ff31 h'fe91 h'fea1 tpu1 tpu2 tpu4 tpu5 7 ? 1 ? 6 ? 1 ? 5 ? 0 ? 4 ? 0 ? 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w channel 1: tmdr1 channel 2: tmdr2 channel 4: tmdr4 channel 5: tmdr5 normal operation reserved pwm mode 1 pwm mode 2 phase calculation mode 1 phase calculation mode 2 phase calculation mode 3 phase calculation mode 4 mode 3 to 0 0 1 0 md0 description md1 md2 * 2 0 0 1 1 0 0 1 ? 1 0 1 1 * * * md3 * 1 0 1 * : don ? t care notes: 1. 2. md3 is a reserved bit. only write 0 to this bit. phase calculation mode cannot be set for channels 0 and 3. only write 0 to md2. bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1118 of 1220 rej09b0186-0300o tier1?timer interrupt enable register 1 tier2?timer interrupt enable register 2 tier4?timer interrupt enable register 4 tier5?timer interrupt enable register 5 h'ff24 h'ff34 h'fe94 h'fea4 tpu1 tpu2 tpu4 tpu5 7 ttge 0 r/w 6 ? 1 ? 5 tcieu 0 r/w 4 tciev 0 r/w 3 ? 0 ? 0 tgiea 0 r/w 2 ? 0 ? 1 tgieb 0 r/w bit initial value r/w : : : channel 1: tier1 channel 2: tier2 channel 4: tier4 channel 5: tier5 a/d conversion start request enable tgfa bit interrupt request (tgia) disabled tgfa bit interrupt request (tgia) enabled 0 1 tgr interrupt enable a underflow interrupt enable tgfb bit interrupt request (tgib) disabled tgfb bit interrupt request (tgib) enabled 0 1 0 1 a/d conversion start request generation disabled a/d conversion start request generation enabled 0 1 tcfu interrupt request (tciu) disabled tcfu interrupt request (tciu) enabled tcfv interrupt request (tciv) disabled tcfv interrupt request (tciv) enabled 0 1 tgr interrupt enable b overflow interrupt enable
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1119 of 1220 rej09b0186-0300o tsr1?timer status register 1 tsr2?timer status register 2 tsr4?timer status register 4 tsr5?timer status register 5 h'ff25 h'ff35 h'fe95 h'fea5 tpu1 tpu2 tpu4 tpu5 7 tcfd 1 r 6 ? 1 ? 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 ? 0 ? 0 tgfa 0 r/(w) * 2 ? 0 ? 1 tgfb 0 r/(w) * note: * only 0 can be written to these bits (to clear these flags). channel 1: tsr1 channel 2: tsr2 channel 4: tsr4 channel 5: tsr5 input capture/output compare flag a input capture/output compare flag b [clearing conditions ] ? when the dtc is started by a tgib interrupt and the dtc mrb disel bit is 0 ? writing 0 to tgfb after reading tgfb = 1 [setting conditions ] ? when tgrb is functioning as the output compare register and tcnt = tgrb ? when tgrb is functioning as the input capture register and the value of tcnt is sent to tgrb by the input capture signal 0 1 0 1 count direction flag underflow flag tcnt counts down tcnt counts up 0 1 overflow flag [clearing condition ] ? writing 0 to tcfv after reading tcfv = 1 [setting condition ] ? when the tcnt value overflows (h'ffff h'0000) 0 1 0 [clearing condition ] ? writing 0 to tcfu after reading tcfu = 1 [setting condition ] ? when the tcnt value underflows (h'0000 h'ffff) 0 1 0 bit initial value r/w : : : [clearing conditions ] ? when the dtc is started by a tgia interrupt and the dtc mrb disel bit is 0 ? when the dmac is started by a tgia interrupt and the dmac dmabcr dta bit is 1 ? writing 0 to tgfa after reading tgfa = 1 [setting conditions ] ? when tgra is functioning as the output compare register and tcnt = tgra ? when tgra is functioning as the input capture register and the value of tcnt is sent to tgra by the input capture signal
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1120 of 1220 rej09b0186-0300o tstr?timer start register h'feb0 tpu common 7 ? 0 ? 6 ? 0 ? 5 cst5 0 r/w 4 cst4 0 r/w 3 cst3 0 r/w 0 cst0 0 r/w 2 cst2 0 r/w 1 cst1 0 r/w counter start 5 to 0 tcntn counting operation disabled tcntn counting operation enabled 0 1 note: when the tioc pin is operating as an output pin, writing 0 to a cst bit disables counting. the tioc pins output compare output level is maintained. when a cst bit is 0, the output level of the pin is updated to the set initial output value by writing to tior. (n = 5 to 0) bit initial value r/w : : : tsyr?timer synchro register h'feb1 tpu common 7 ? 0 ? 6 ? 0 ? 5 sync5 0 r/w 4 sync4 0 r/w 3 sync3 0 r/w 0 sync0 0 r/w 2 sync2 0 r/w 1 sync1 0 r/w bit initial value r/w : : : timer sync 5 to 0 tcntn operate independently (tcnts are preset and cleared independently of other channels) tcntn operate in sync mode. synchronized tcnt presetting and clearing enabled 0 1 (n = 5 to 0) notes: 1. 2. the sync bit of a minimum of two channels must be set to 1 in order to select sync operation. to enable sync clearing, in addition to the sync bits, the tcr cclr2 to cclr0 bits must be set for the tcnt clearin g factors.
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1121 of 1220 rej09b0186-0300o ipra?interrupt priority register a iprb?interrupt priority register b iprc?interrupt priority register c iprd?interrupt priority register d ipre?interrupt priority register e iprf?interrupt priority register f iprg?interrupt priority register g iprh?interrupt priority register h ipri?interrupt priority register i iprj?interrupt priority register j iprk?interrupt priority register k iprl?interrupt priority register l ipro?interrupt priority register o h'fec0 h'fec1 h'fec2 h'fec3 h'fec4 h'fec5 h'fec6 h'fec7 h'fec8 h'fec9 h'feca h'fecb h'fece interrupt controller 7 ? 0 ? 6 ipr6 1 r/w 5 ipr5 1 r/w 4 ipr4 1 r/w 3 ? 0 ? 0 ipr0 1 r/w 2 ipr2 1 r/w 1 ipr1 1 r/w iprb irq2 register bit irq3 iprc irq6 irq7 irq4 irq5 dtc interrupt factors vs ipr ipra irq0 irq1 iprd watchdog timer 0 refresh timer ipre pc brake adc watchdog timer 1 iprf tpu channel 0 tpu channel 1 iprg tpu channel 2 tpu channel 3 iprh tpu channel 4 itpu channel 5 ipri 8-bit timer channel 0 8-bit timer channel 1 iprj dmac sci channel 0 iprk sci channel 1 sci channel 2 iprl 8-bit timer 2, 3 iic (optional) ipro sci channel 3 sci channel 4 6 to 4 2 to 0 bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1122 of 1220 rej09b0186-0300o abwcr?bus width control register h'fed0 bus controller 7 abw7 1 r/w 0 r/w 6 abw6 1 r/w 0 r/w 5 abw5 1 r/w 0 r/w 4 abw4 1 r/w 0 r/w 3 abw3 1 r/w 0 r/w 0 abw0 1 r/w 0 r/w 2 abw2 1 r/w 0 r/w 1 abw1 1 r/w 0 r/w area 7 to 0 bus width control sets area n to 16-bit access sets area n to 8-bit access 0 1 (n = 7 to 0) bit mode 5 to 7 initial value r/w mode 4 initial value r/w : : : : : : astcr?access state control register h'fed1 bus controller 7 ast7 1 r/w 6 ast6 1 r/w 5 ast5 1 r/w 4 ast4 1 r/w 3 ast3 1 r/w 0 ast0 1 r/w 2 ast2 1 r/w 1 ast1 1 r/w area 7 to 0 access state control area n set as 2-state access area insertion of wait states in area n external area access is disabled external area access of area n set as 3-state access area insertion of wait states in area n external area access is enabled 0 1 (n = 7 to 0) bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1123 of 1220 rej09b0186-0300o wcrh?wait control register h h'fed2 bus controller 7 w71 1 r/w 6 w70 1 r/w 5 w61 1 r/w 4 w60 1 r/w 3 w51 1 r/w 0 w40 1 r/w 2 w50 1 r/w 1 w41 1 r/w area 7 wait control 1, 0 area 6 wait control 1, 0 area 4 wait control 1, 0 area 5 wait control 1, 0 0 0 no program wait inserted when accessing external area of area 7 1 program wait state inserted when accessing external area of area 7 2 program wait states inserted when accessing external area of area 7 3 program wait states inserted when accessing external area of area 7 w70 w71 1 0 1 1 0 0 no program wait inserted when accessing external area of area 5 1 program wait state inserted when accessing external area of area 5 2 program wait states inserted when accessing external area of area 5 3 program wait states inserted when accessing external area of area 5 w50 w51 1 0 1 1 0 0 no program wait inserted when accessing external area of area 4 1 program wait state inserted when accessing external area of area 4 2 program wait states inserted when accessing external area of area 4 3 program wait states inserted when accessing external area of area 4 w40 w41 1 0 1 1 0 0 no program wait inserted when accessing external area of area 6 1 program wait state inserted when accessing external area of area 6 2 program wait states inserted when accessing external area of area 6 3 program wait states inserted when accessing external area of area 6 w60 w61 1 0 1 1 bit initial value r/w : : : description description description description
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1124 of 1220 rej09b0186-0300o wcrl?wait control register h'fed3 bus controller 7 w31 1 r/w 6 w30 1 r/w 5 w21 1 r/w 4 w20 1 r/w 3 w11 1 r/w 0 w00 1 r/w 2 w10 1 r/w 1 w01 1 r/w area 3 wait control area 2 wait control area 0 wait control area 1 wait control 0 0 no program wait inserted when accessing external area of area 3 1 program wait state inserted when accessing external area of area 3 2 program wait states inserted when accessing external area of area 3 3 program wait states inserted when accessing external area of area 3 w30 w31 1 0 1 1 0 0 no program wait inserted when accessing external area of area 1 1 program wait state inserted when accessing external area of area 1 2 program wait states inserted when accessing external area of area 1 3 program wait states inserted when accessing external area of area 1 w10 w11 1 0 1 1 0 0 no program wait inserted when accessing external area of area 0 1 program wait state inserted when accessing external area of area 0 2 program wait states inserted when accessing external area of area 0 3 program wait states inserted when accessing external area of area 0 w00 w01 1 0 1 1 0 0 no program wait inserted when accessing external area of area 2 1 program wait state inserted when accessing external area of area 2 2 program wait states inserted when accessing external area of area 2 3 program wait states inserted when accessing external area of area 2 w20 w21 1 0 1 1 bit initial value r/w : : : description description description description
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1125 of 1220 rej09b0186-0300o bcrh?bus control register h h'fed4 bus controller 7 icis1 1 r/w 6 icis0 1 r/w 5 brstrm 0 r/w 4 brsts1 1 r/w 3 brsts0 0 r/w 0 rmts0 0 r/w 2 rmts2 0 r/w 1 rmts1 0 r/w no idle cycle is inserted when an external read cycle follows an external read cycle of another area an idle cycle is inserted when an external read cycle follows an external read cycle of another area 0 1 0 idle cycle insertion 1 no idle cycle is inserted when an external read cycle follows an external write cycle an idle cycle is inserted when an external read cycle follows an external write cycle 1 idle cycle insertion 0 area 0 is basic bus interface area 0 is burst rom interface 0 1 burst rom enable burst cycle = 1 state burst cycle = 2 states 0 1 burst access = 4 words max burst access = 8 words max 0 1 burst cycle select 1 ram type select burst cycle select 0 0 1 0 rmts0 area 2 rmts1 rmts2 area 3 area 4 area 5 0 0 1 1 1 1 1 normal area dram area normal area dram area normal area dram area contiguous dram area bit initial value r/w : : : note: when all areas selected in the dram area are set for 8-bit access, the pf2 pin can be used as an i/o port or breqo or wait . when set for contiguous dram the bus widths for areas 2 to 5 and the number of access states (number of programmable waits) must be set to the same values. do not attempt to set combinations other than those shown in the table.
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1126 of 1220 rej09b0186-0300o bcrl?bus control register l h'fed5 bus controller 7 brle 0 r/w 6 breqoe 0 r/w 5 ? 0 ? 4 oes 0 r/w 3 dds 1 r/w 0 waite 0 r/w 2 rcts 0 r/w 1 wdbe 0 r/w bit initial value r/w : : : release of external bus privileges disabled. breq , back , and breqo can be used as i/o ports release of external bus privileges enabled 0 1 bus release enable wait input via wait pin disabled the wait pin can be used as an i/o port wait input via wait pin enabled 0 1 wait pin enable breqo output disabled. breqo can be used as an i/o port breqo output enabled 0 1 breqo pin enable cs3 pin used as port or as cs3 signal output when only area 2 is set as dram, or when areas 2 to 5 are set as contiguous dram space, the cs3 pin is used as the oe pin 0 1 oe select do not use write data buffer function use write data buffer function 0 1 write data buffer enable cas signal output timing is the same when reading and writing when reading, the cas signal is asserted one half cycle faster than when writing 0 1 read cas timing select when performing dmac single address transmission to the dram space, always perform full access. the dack signal level changes to low from t r or t 1 cycle burst access is also available when performing dmac single address transmission to the dram space. the dack signal level changes to low from t c1 or t 2 cycle 0 1 dack timing select
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1127 of 1220 rej09b0186-0300o mcr?memory control register h'fed6 bus controller 7 tpc 0 r/w 6 be 0 r/w 5 rcdm 0 r/w 4 cw2 0 r/w 3 mxc1 0 r/w 0 rlw0 0 r/w 2 mxc0 0 r/w 1 rlw1 0 r/w bit initial value r/w : : : one precharge cycle state inserted two precharge cycle states inserted 0 1 0 tp cycle control burst access disabled (permanently full access) dram space accessed in high-speed page mode 1 burst access enable dram interface: ras up mode selected dram interface: ras down mode selected 0 1 ras down mode insert 3 wait states insert 1 wait state insert 2 wait states do not insert wait state reserved bit refresh cycle wait control 1, 0 multiplex shift count 1, 0 0 1 0 rlw0 rlw1 0 1 1 ? 0 1 0 mxc0 mxc1 0 1 1 8-bit shift (1) when set for 8-bit access space: row addresses a23 to a8 are targets of comparison (2) when set for 16-bit access space: row addresses a23 to a9 are targets of comparison 9-bit shift (1) when set for 8-bit access space: row addresses a23 to a9 are targets of comparison (2) when set for 16-bit access space: row addresses a23 to a10 are targets of comparison 10-bit shift (1) when set for 8-bit access space: row addresses a23 to a10 are targets of comparison (2) when set for 16-bit access space: row addresses a23 to a11 are targets of comparison description description
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1128 of 1220 rej09b0186-0300o dramcr?dram control register h'fed7 bus controller 7 rfshe 0 r/w 6 cbrm 0 r/w 5 rmode 0 r/w 4 cmf 0 r/w 3 cmie 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w refresh control 0 [clearing condition] ? writing 0 to cmf flag after reading cmf = 1 [setting condition] ? when rtcnt = rtcor 1 cbr refresh mode do not perform self-refresh in software standby mode perform self-refresh in software standby mode 0 1 external access enabled at cas-before-ras refresh external access disabled at cas-before-ras refresh 0 1 do not perform refresh control perform refresh control 0 1 refresh mode cmf flag interrupt request (cmi) disabled cmf flag interrupt request (cmi) enabled counting on /8 counting on /32 no counting operation counting on /2 0 1 compare match flag refresh counter clock select compare match interrupt enable 0 1 0 cks0 cks1 cks2 0 0 1 1 counting on /2048 counting on /4096 counting on /128 counting on /512 0 1 0 1 0 1 1 bit initial value r/w : : : description
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1129 of 1220 rej09b0186-0300o rtcnt?refresh timer counter h'fed8 bus controller 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : rtcor?refresh time constant register h'fed9 bus controller 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : : ramer?ram emulation register h'fedb flash 7 ? 0 r 6 ? 0 r 5 ? 0 r/w 4 ? 0 r/w 3 rams 0 r/w 0 ram0 0 r/w 2 ram2 0 r/w 1 ram1 0 r/w ram select * : don ? t care emulation not selected program/erase-protection of all flash memory blocks is disabled 0 1 flash memory area selection 0 emulation selected program/erase-protection of all flash memory blocks is enabled addresses block name h'ffd000 ? h'ffdfff ram area 4 kbytes h'000000 ? h'000fff eb0 (4 kbytes) h'001000 ? h'001fff eb1 (4 kbytes) h'002000 ? h'002fff eb2 (4 kbytes) h'003000 ? h'003fff eb3 (4 kbytes) h'004000 ? h'004fff eb4 (4 kbytes) h'005000 ? h'005fff eb5 (4 kbytes) h'006000 ? h'006fff eb6 (4 kbytes) h'007000 ? h'007fff eb7 (4 kbytes) rams ram1 ram1 ram0 0 * * * 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1130 of 1220 rej09b0186-0300o mar0ah?memory address register 0ah mar0al?memory address register 0al h'fee0 h'fee2 dmac dmac 16 * r/w 18 * r/w 17 * r/w 19 * r/w 21 * r/w 22 * r/w 23 * r/w 24 ? 0 ? 25 ? 0 ? 26 ? 0 ? 27 ? 0 ? 28 ? 0 ? 29 ? 0 ? 30 ? 0 ? 31 ? 0 ? 0 * r/w 2 * r/w 1 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 * r/w 8 * r/w 9 * r/w 10 * r/w 11 * r/w 12 * r/w 13 * r/w 14 * r/w 15 * r/w 20 * r/w * : undefined bit mar initial value r/w : : : : bit mar initial value r/w : : : : in short address mode: specifies transfer destination/transfer source address in full address mode: not used ioar0a?i/o address register 0a ioar1a?i/o address register 1a h'fee4 h'fef4 dmac dmac 0 * r/w 2 * r/w 1 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 * r/w 8 * r/w 9 * r/w 10 * r/w 11 * r/w 12 * r/w 13 * r/w 14 * r/w 15 * r/w * : undefined bit ioar initial value r/w : : : : in short address mode: specifies transfer destination/transfer source address in full address mode: not used
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1131 of 1220 rej09b0186-0300o etcr0a?transfer count register 0a h'fee6 dmac * : undefined bit etcr0a initial value r/w : : : : sequential mode, idle mode, and normal mode repeat mode block transfer mode 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w transfer counter block size counter transfer counter holds number of transfers holds block size mar0bh?memory address register 0bh mar0bl?memory address register 0bl h'fee8 h'feea dmac dmac * : undefined bit mar0bl initial value r/w 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w bit mar0bh initial value r/w : : : : : : : : 31 ? 0 ? 30 ? 0 ? 29 ? 0 ? 28 ? 0 ? 27 ? 0 ? 26 ? 0 ? 25 ? 0 ? 24 ? 0 ? 23 * r/w 22 * r/w 21 * r/w 20 * r/w 19 * r/w 18 * r/w 17 * r/w 16 * r/w in short address mode: specifies transfer destination/transfer source address in full address mode: specifies transfer destination
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1132 of 1220 rej09b0186-0300o ioar0b?i/o address register 0b ioar1b?i/o address register 1b h'feec h'fefc dmac dmac * : undefined bit ioar0b initial value r/w : : : : 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w in short address mode: specifies transfer destination/transfer source address in full address mode: not used etcr0b?transfer count register 0b h'feee dmac note: not used in normal mode. * : undefined bit etcr0b initial value r/w : : : : sequential mode and idle mode repeat mode block transfer mode 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w transfer counter transfer counter holds number of transfers block transfer counter
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1133 of 1220 rej09b0186-0300o mar1ah?memory address register 1ah mar1al?memory address register 1al h'fef0 h'fef2 dmac dmac * : undefined bit mar1al initial value r/w 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w bit mar1ah initial value r/w : : : : : : : : 31 ? 0 ? 30 ? 0 ? 29 ? 0 ? 28 ? 0 ? 27 ? 0 ? 26 ? 0 ? 25 ? 0 ? 24 ? 0 ? 23 * r/w 22 * r/w 21 * r/w 20 * r/w 19 * r/w 18 * r/w 17 * r/w 16 * r/w in short address mode: specifies transfer destination/transfer source address in full address mode: not used etcr1a?transfer count register 1a h'fef6 dmac * : undefined bit etcr1a initial value r/w : : : : sequential mode, idle mode, and normal mode repeat mode block transfer mode 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w transfer counter block size counter transfer counter holds number of transfers holds block size
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1134 of 1220 rej09b0186-0300o mar1bh?memory address register 1bh mar1bl?memory address register 1bl h'fef8 h'fefa dmac dmac * : undefined bit mar1bl initial value r/w 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w bit mar1bh initial value r/w : : : : : : : : 31 ? 0 ? 30 ? 0 ? 29 ? 0 ? 28 ? 0 ? 27 ? 0 ? 26 ? 0 ? 25 ? 0 ? 24 ? 0 ? 23 * r/w 22 * r/w 21 * r/w 20 * r/w 19 * r/w 18 * r/w 17 * r/w 16 * r/w in short address mode: specifies transfer destination/transfer source address in full address mode: not used etcr1b?transfer count register 1b h'fefe dmac note: not used in normal mode. * : undefined bit etcr1b initial value r/w : : : : sequential mode and idle mode repeat mode block transfer mode 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 10 * r/w 9 * r/w 8 * r/w 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 2 * r/w 1 * r/w 0 * r/w transfer counter transfer counter holds number of transfers block transfer counter
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1135 of 1220 rej09b0186-0300o p1dr?port 1 data register h'ff00 port 7 p17dr 0 r/w 6 p16dr 0 r/w 5 p15dr 0 r/w 4 p14dr 0 r/w 3 p13dr 0 r/w 0 p10dr 0 r/w 2 p12dr 0 r/w 1 p11dr 0 r/w bit initial value r/w : : : p2dr?port 2 data register h'ff01 port 7 p27dr 0 r/w bit initial value r/w : : : 6 p26dr 0 r/w 5 p25dr 0 r/w 4 p24dr 0 r/w 3 p23dr 0 r/w 2 p22dr 0 r/w 1 p21dr 0 r/w 0 p20dr 0 r/w p3dr?port 3 data register h'ff02 port 7 p37dr 0 r/w 6 p36dr 0 r/w 5 p35dr 0 r/w 4 p34dr 0 r/w 3 p33dr 0 r/w 0 p30dr 0 r/w 2 p32dr 0 r/w 1 p31dr 0 r/w bit initial value r/w : : : p5dr?port 5 data register h'ff04 port 7 ? undefined ? bit initial value r/w : : : 6 ? undefined ? 5 ? undefined ? 4 ? undefined ? 3 ? undefined ? 2 p52dr 0 r/w 1 p51dr 0 r/w 0 p50dr 0 r/w p7dr?port 7 data register h'ff06 port 7 p77dr 0 r/w 6 p76dr 0 r/w 5 p75dr 0 r/w 4 p74dr 0 r/w 3 p73dr 0 r/w 0 p70dr 0 r/w 2 p72dr 0 r/w 1 p71dr 0 r/w bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1136 of 1220 rej09b0186-0300o p8dr?port 8 data register h'ff07 port 7 ? undefined ? bit initial value r/w : : : 6 p86dr 0 r/w 5 p85dr 0 r/w 4 p84dr 0 r/w 3 p83dr 0 r/w 2 p82dr 0 r/w 1 p81dr 0 r/w 0 p80dr 0 r/w padr?port a data register h'ff09 port 7 pa7dr 0 r/w 6 pa6dr 0 r/w 5 pa5dr 0 r/w 4 pa4dr 0 r/w 3 pa3dr 0 r/w 0 pa0dr 0 r/w 2 pa2dr 0 r/w 1 pa1dr 0 r/w bit initial value r/w : : : pbdr?port b data register h'ff0a port 7 pb7dr 0 r/w 6 pb6dr 0 r/w 5 pb5dr 0 r/w 4 pb4dr 0 r/w 3 pb3dr 0 r/w 0 pb0dr 0 r/w 2 pb2dr 0 r/w 1 pb1dr 0 r/w bit initial value r/w : : : pcdr?port c data register h'ff0b port 7 pc7dr 0 r/w 6 pc6dr 0 r/w 5 pc5dr 0 r/w 4 pc4dr 0 r/w 3 pc3dr 0 r/w 0 pc0dr 0 r/w 2 pc2dr 0 r/w 1 pc1dr 0 r/w bit initial value r/w : : : pddr?port d data register h'ff0c port 7 pd7dr 0 r/w 6 pd6dr 0 r/w 5 pd5dr 0 r/w 4 pd4dr 0 r/w 3 pd3dr 0 r/w 0 pd0dr 0 r/w 2 pd2dr 0 r/w 1 pd1dr 0 r/w bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1137 of 1220 rej09b0186-0300o pedr?port e data register h'ff0d port 7 pe7dr 0 r/w 6 pe6dr 0 r/w 5 pe5dr 0 r/w 4 pe4dr 0 r/w 3 pe3dr 0 r/w 0 pe0dr 0 r/w 2 pe2dr 0 r/w 1 pe1dr 0 r/w bit initial value r/w : : : pfdr?port f data register h'ff0e port 7 pf7dr 0 r/w 6 pf6dr 0 r/w 5 pf5dr 0 r/w 4 pf4dr 0 r/w 3 pf3dr 0 r/w 0 pf0dr 0 r/w 2 pf2dr 0 r/w 1 pf1dr 0 r/w bit initial value r/w : : : pgdr?port g data register h'ff0f port 7 ? undefined ? 6 ? undefined ? 5 ? undefined ? 4 pg4dr 0 r/w 3 pg3dr 0 r/w 0 pg0dr 0 r/w 2 pg2dr 0 r/w 1 pg1dr 0 r/w bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1138 of 1220 rej09b0186-0300o dmawer?dma write enable register h'ff60 dmac 7 ? 0 ? 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 we1b 0 r/w 0 we0a 0 r/w 2 we1a 0 r/w 1 we0b 0 r/w write enable 1a disables writing to all dmacr1a bits, and dmabcr bits 10, 6, and 2 enables writing to all dmacr1a bits, and dmabcr bits 10, 6, and 2 0 1 disables writing to all dmacr0a bits, and dmabcr bits 8, 4, and 0 enables writing to all dmacr0a bits, and dmabcr bits 8, 4, and 0 0 1 write enable 0b disables writing to all dmacr0b bits, dmabcr bits 9, 5, and 1, and dmatcr bit 4 enables writing to all dmacr0b bits, dmabcr bits 9, 5, and 1, and dmatcr bit 4 0 1 write enable 0a disables writing to all dmacr1b bits, dmabcr bits 11, 7, and 3, and dmatcr bit 5 enables writing to all dmacr1b bits, dmabcr bits 11, 7, and 3, and dmatcr bit 5 0 1 write enable 1b bit dmawer initial value r/w : : : : dmatcr?dma terminal control register h'ff61 dmac 7 ? 0 ? 6 ? 0 ? 5 tee1 0 r/w 4 tee0 0 r/w 3 ? 0 ? 0 ? 0 ? 2 ? 0 ? 1 ? 0 ? bit dmatcr initial value r/w : : : : disables tend1 pin output enables tend1 pin output 0 1 transfer end pin enable 1 disables tend0 pin output enables tend0 pin output 0 1 transfer end pin enable 0
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1139 of 1220 rej09b0186-0300o dmacr0a?dma control register 0a dmacr0b?dma control register 0b dmacr1a?dma control register 1a dmacr1b?dma control register 1b h'ff62 h'ff63 h'ff64 h'ff65 dmac dmac dmac dmac bit dmacra initial value r/w full address mode : : : : 15 dtsz 0 r/w 14 said 0 r/w 13 saide 0 r/w 12 blkdir 0 r/w 11 blke 0 r/w 10 ? 0 r/w 9 ? 0 r/w 8 ? 0 r/w block direction/block enable 0 transfer in normal mode 1 0 1 0 1 transfer in block transfer mode, destination is block area transfer in normal mode transfer in block transfer mode, source is block area source address increment/decrement 0 mara is fixed 1 0 1 0 1 mara is incremented after a data transfer mara is fixed mara is decremented after a data transfer data transfer size 0 byte-size transfer 1 word-size transfer when dtsz = 0, mara is incremented by 1 after a transfer when dtsz = 1, mara is incremented by 2 after a transfer when dtsz = 0, mara is decremented by 1 after a transfer when dtsz = 1, mara is decremented by 2 after a transfer
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1140 of 1220 rej09b0186-0300o bit dmacrb initial value r/w full address mode : : : : 7 ? 0 r/w 6 daid 0 r/w 5 daide 0 r/w 4 ? 0 r/w 3 dtf3 0 r/w 2 dtf2 0 r/w 1 dtf1 0 r/w 0 dtf0 0 r/w data transfer factor dtf3 dtf2 dtf1 dtf0 block transfer mode normal mode ? activated by a/d converter conversion end interrupt activated by dreq pin falling edge input * activated by dreq pin low-level input activated by sci channel 0 transmit-data-empty interrupt activated by sci channel 0 reception complete interrupt 0 1 0 1 0 1 activated by sci channel 1 transmit-data-empty interrupt 0 activated by sci channel 1 reception complete interrupt ? ? activated by dreq pin falling edge input activated by dreq pin low-level input ? ? auto-request (cycle steal) auto-request (burst) 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 activated by tpu channel 0 compare match/input capture a interrupt ? activated by tpu channel 1 compare match/input capture a interrupt ? activated by tpu channel 2 compare match/input capture a interrupt ? activated by tpu channel 3 compare match/input capture a interrupt ? activated by tpu channel 4 compare match/input capture a interrupt ? activated by tpu channel 5 compare match/input capture a interrupt ? ?? ?? destination address increment/decrement note: * detected as a low level in the first transfer after transfer is enabled. 0 marb is fixed 1 0 1 0 1 marb is incremented after a data transfer when dtsz = 0, marb is incremented by 1 after a transfer when dtsz = 1, marb is incremented by 2 after a transfer marb is fixed marb is decremented after a data transfer when dtsz = 0, marb is decremented by 1 after a transfer when dtsz = 1, marb is decremented by 2 after a transfer
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1141 of 1220 rej09b0186-0300o bit dmacr initial value read/write short address mode 7 dtsz 0 r/w 6 dtid 0 r/w 5 rpe 0 r/w 4 dtdir 0 r/w 3 dtf3 0 r/w 2 dtf2 0 r/w 1 dtf1 0 r/w 0 dtf0 0 r/w data transfer factor 0 ? channel a channel b 1 0 1 activated by a/d converter conversion end interrupt ? ? activated by dreq pin falling edge input activated by dreq pin low-level input activated by sci channel 0 transmit-data- empty interrupt activated by sci channel 0 reception complete interrupt 0 1 0 1 00 1 activated by sci channel 1 transmit-data- empty interrupt 10 activated by sci channel 1 reception complete interrupt 1 0 0 1 activated by tpu channel 0 compare match/ input capture a interrupt 1 0 1 activated by tpu channel 1 compare match/ input capture a interrupt activated by tpu channel 2 compare match/ input capture a interrupt activated by tpu channel 3 compare match/ input capture a interrupt activated by tpu channel 4 compare match/ input capture a interrupt activated by tpu channel 5 compare match/ input capture a interrupt 0 1 0 1 00 1 ? 10 ? 1 data transfer direction 00 1 transfer with mar as source address and ioar as destination address transfer with ioar as source address and mar as destination address 10 1 transfer with mar as source address and dack pin as write strobe transfer with dack pin as read strobe and mar as destination address repeat enable 0 transfer in sequential mode (no transfer end interrupt) transfer in sequential mode (with transfer end interrupt) 1 transfer in repeat mode (no transfer end interrupt) transfer in idle mode (with transfer end interrupt) 0 1 0 1 data transfer increment/decrement 0 mar is incremented after a data transfer when dtsz = 0, mar is incremented by 1 after a transfer when dtsz = 1, mar is incremented by 2 after a transfer 1 mar is decremented after a data transfer when dtsz = 0, mar is decremented by 1 after a transfer when dtsz = 1, mar is decremented by 2 after a transfer data transfer size 0 byte-size transfer 1 word-size transfer
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1142 of 1220 rej09b0186-0300o dmabcr?dma band control register h'ff66 dmac short address mode 15 fae1 0 r/w 14 fae0 0 r/w 13 sae1 0 r/w 12 sae0 0 r/w 11 dta1b 0 r/w 8 dta0a 0 r/w 10 dta1a 0 r/w 9 dta0b 0 r/w full address enable 1 data transfer acknowledge 0a short address mode full address mode 0 1 transfer in dual address mode transfer in single address mode 0 1 short address mode full address mode 0 1 clearing of selected internal interrupt factor at dma transfer disabled clearing of selected internal interrupt factor at dma transfer enabled 0 1 clearing of selected internal interrupt factor at dma transfer disabled clearing of selected internal interrupt factor at dma transfer enabled 0 1 clearing of selected internal interrupt factor at dma transfer disabled clearing of selected internal interrupt factor at dma transfer enabled 0 1 clearing of selected internal interrupt factor at dma transfer disabled clearing of selected internal interrupt factor at dma transfer enabled 0 1 full address enable 0 transfer in dual address mode transfer in single address mode 0 1 single address enable 1 single address enable 0 data transfer acknowledge 0b data transfer acknowledge 1a data transfer acknowledge 1b bit dmabcrh initial value r/w : : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1143 of 1220 rej09b0186-0300o 7 dte1b 0 r/w 6 dte1a 0 r/w 5 dte0b 0 r/w 4 dte0a 0 r/w 3 dtie1b 0 r/w 0 dtie0a 0 r/w 2 dtie1a 0 r/w 1 dtie0b 0 r/w data transfer enable 1b data transfer interrupt enable 0a data transfer disabled data transfer enabled 0 1 data transfer disabled data transfer enabled 0 1 data transfer disabled data transfer enabled 0 1 transfer end interrupt disabled transfer end interrupt enabled 0 1 transfer end interrupt disabled transfer end interrupt enabled 0 1 transfer end interrupt disabled transfer end interrupt enabled 0 1 transfer end interrupt disabled transfer end interrupt enabled 0 1 data transfer enable 1a data transfer disabled data transfer enabled 0 1 data transfer enable 0b data transfer enable 0a data transfer interrupt enable 0b data transfer interrupt enable 1a data transfer interrupt enable 1b bit dmabcrl initial value r/w : : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1144 of 1220 rej09b0186-0300o 15 fae1 0 r/w 14 fae0 0 r/w 13 ? 0 r/w 12 ? 0 r/w 11 dta1 0 r/w 8 ? 0 r/w 10 ? 0 r/w 9 dta0 0 r/w bit dmabcrh initial value r/w full address mode : : : : full address enable 1 0 short address mode 1 full address mode full address enable 0 0 short address mode 1 full address mode data transfer acknowledge 1 data transfer acknowledge 0 0 clearing of selected internal interrupt source at time of dma transfer is disabled 1 clearing of selected internal interrupt source at time of dma transfer is enabled 0 clearing of selected internal interrupt source at time of dma transfer is disabled 1 clearing of selected internal interrupt source at time of dma transfer is enabled
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1145 of 1220 rej09b0186-0300o 7 dtme1 0 r/w 6 dte1 0 r/w 5 dtme0 0 r/w 4 dte0 0 r/w 3 dtie1b 0 r/w 0 dtie0a 0 r/w 2 dtie1a 0 r/w 1 dtie0b 0 r/w bit dmabcrl initial value r/w : : : : data transfer end interrupt enable 0a 0 transfer end interrupt disabled 1 transfer end interrupt enabled data transfer end interrupt enable 1a 0 transfer end interrupt disabled 1 transfer end interrupt enabled data transfer interrupt enable 0b 0 transfer break interrupt disabled 1 transfer break interrupt enabled data transfer interrupt enable 1b 0 transfer break interrupt disabled 1 transfer break interrupt enabled data transfer enable 0 0 data transfer disabled 1 data transfer enabled data transfer enable 1 0 data transfer disabled 1 data transfer enabled data transfer master enable 0 0 data transfer disabled in normal mode, cleared to 0 by an nmi interrupt 1 data transfer enabled data transfer master enable 1 0 data transfer disabled in burst mode, cleared to 0 by an nmi interrupt 1 data transfer enabled
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1146 of 1220 rej09b0186-0300o tcsr0?timer control/status register 0 h'ff74 (w), h'ff74 (r) wdt0 7 ovf 0 r/(w) * 6 wt/ it 0 r/w 5 tme 0 r/w 4 ? 1 ? 3 ? 1 ? 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w notes: tcsr is write-protected by a password to prevent accidental overwriting. for details see section 15.2.5, notes on register access. * only 0 can be written to these bits (to clear these fla g s). overflow flag 0 [clearing condition] ? when 0 is written to ovf bit after reading tcsr when ovf = 1 1 [setting conditions] ? when tcnt overflows (changes from h'ff to h'00) ? when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset timer enable 0 initializes tcnt to h ' 00 and disables the counting operation 1 tcnt performs counting operation timer mode select 0 interval timer mode: interval timer interrupt (wovi) request sent to cpu when overflow occurs at tcnt 1 watchdog timer mode: wdtovf signal output externally when overflow occurs at tcnt * note: * see section 15.2.3, reset control/status register (rstcsr) for details of when tcnt overflows in watchdog timer mode. clock select 2 to 0 wdt0 input clock select cks2 cks1 cks0 clock overflow cycle * (when = 25 mhz) 0 0 0 /2 20.4 s 1 /64 652.8 s 1 0 /128 1.3 ms 1 /512 5.2 ms 1 0 0 /2048 20.9 ms 1 /8192 83.6 ms 1 0 /32768 334.2 ms 1 /131072 1.34 s note: * the overflow cycle starts when tcnt starts counting from h ' 00 and ends when an overflow occurs. bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1147 of 1220 rej09b0186-0300o tcnt0?timer counter 0 tcnt1?timer counter 1 h'ff74 (w), h'ff75 (r) h'ffa2 (w), h'ffa3 (r) wdt0 wdt1 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : note: tcnt is write-protected by a password to prevent accidental overwriting. for details see section 15.2.5, notes on register access. rstcsr?reset control/status register h'ff76 (w), h'ff77 (r) wdt0 7 wovf 0 r/(w) * 6 rste 0 r/w 5 rsts 0 r/w 4 ? 1 ? 3 ? 1 ? 0 ? 1 ? 2 ? 1 ? 1 ? 1 ? notes: rstcsr is write-protected by a password to prevent accidental overwriting. for details see section 15.2.5, notes on register access. * only 0 can be written to these bits (to clear these flags). watchdog timer overflow flag 0 [clearing condition] ? writing 0 to wovf after reading tcsr when wovf = 1 1 [setting condition] ? when, in watchdog timer mode, tcnt overflows (h'ff h'00) reset select 0 power-on reset 1 manual reset reset enable 0 no internal reset on tcnt overflow * 1 internal reset performed on tcnt overflow note: * the lsi is not internally reset, but tcnt and tcsr in wdt are reset. bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1148 of 1220 rej09b0186-0300o iccr0?i 2 c bus control register iccr1?i 2 c bus control register h'ff78 h'ff80 iic0 iic1 7 ice 0 r/w 6 ieic 0 r/w 5 mst 0 r/w 4 trs 0 r/w 3 acke 0 r/w 0 scp 0 r/w 2 bbsy 0 r/w 1 iric 0 r/(w) * bus busy 0 bus is free [clearing condition] ? when a stop condition is detected 1 bus is free [clearing condition] ? when a stop condition is detected i 2 c bus interface interrupt request flag 0 waiting for transfer, or transfer in progress 1 interrupt requested i 2 c bus interface interrupt enable 0 interrupts disabled 1 interrupts enabled i 2 c bus interface enable 0 i 2 c bus interface module disabled, with scl and sda signal pins set to port function i 2 c bus interface module internal states initialized sar and sarx can be accessed 1 i 2 c bus interface module enabled for transfer operations (pins scl and sda are driving the bus) icmr and icdr can be accessed acknowledge bit judgement selection 0 the value of the acknowledge bit is ignored, and continuous transfer is performed 1 if the acknowledge bit is 1, continuous transfer is interrupted start condition/stop condition prohibit 0 writing 0 issues a start or stop condition, in combination with the bbsy flag 1 reading always returns a value of 1 writing is ignored master/slave select, transmit/receive select 0 0 slave receive mode 1 slave transmit mode 1 0 master receive mode 1 master transmit mode note: for details see section 18.2.5, i 2 c bus control register. note: for details see section 18.2.5, i 2 c bus control register. note: * only 0 can be written, for flag clearing. bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1149 of 1220 rej09b0186-0300o icsr0?i 2 c bus status register icsr1?i 2 c bus status register h'ff79 h'ff81 iic0 iic1 7 estp 0 r/(w) * 6 stop 0 r/(w) * 5 irtr 0 r/(w) * 4 aasx 0 r/(w) * 3 al 0 r/(w) * 0 ackb 0 r/w 2 aas 0 r/(w) * 1 adz 0 r/(w) * note: * only 0 can be written to these bits (to clear these flags). error stop condition detection flag 0 no error stop condition [clearing conditions] when 0 written after reading estp = 1 when iric flag is cleared to 0 1 error stop condition detected in slave mode in i 2 c bus format [setting conditions] on detection of stop condition while sending frame no meaning when in other than slave mode in i 2 c bus format normal end condition detection flag 0 no normal end condition [clearing conditions] when 0 is written after reading stop = 1 when iric flag is cleared to 0 1 normal end condition detected in slave mode in i 2 c bus format [setting conditions] on detection of stop condition on completion of sending frame no meaning when in other than slave mode in i 2 c bus format i 2 c bus interface continuous transmit and receive interrupt request flag 0 transmit wait state, or transmitting [clearing conditions] whe conditionsn 0 written after reading irtr = 1 when iric flag is cleared to 0 1 continuous transmit state [setting conditions] in i 2 c bus interface slave mode when 1 is set in tdre or rdrf flag when aasx = 1 in other than i 2 c bus interface slave mode when tdre or rdrf flag is set to 1 2nd slave address confirmation flag 0 2nd slave address not confirmed [clearing conditions] when 0 is written after reading aasx = 1 when start conditions are detected in master mode 1 2nd slave address confirmed [setting condition] when 2nd slave address is detected in slave receive mode and fsx = 0 arbitration lost flag 0 secure bus [clearing conditions] when data is written to icdr (when sending), or when data is read (when receiving) when 0 is written after reading al = 1 1 bus arbitration lost [setting conditions] when there is a mismatch between internal sda and sda pin at rise in scl in master transmit mode when the internal scl level is high at the fall in scl in master transmit mode slave address confirmation flag 0 slave address or general call address not confirmed [clearing conditions] when data is written to icdr (when sending), or when data is read from icdr (when receiving) when 0 is written after reading aas = 1 in master mode 1 slave address or general call address confirmed [setting condition] when slave address or general call address is detected in slave receive mode and fs = 0 general call address confirmation flag 0 general call address not confirmed [clearing conditions] when data is written to icdr (when sending), or when data is read from icdr (when receiving) when 0 is written after reading adz = 1 in master mode 1 general call address confirmation [setting condition] when general call address is detected is in slave receive mode and fsx = 0 or fs = 0) acknowledge bit 0 when receiving, 0 is output at acknowledge output timing when transmitting, this bit shows that an acknowledge (0) has not been sent from the receiving device 1 when receiving, 1 is output at acknowledge output timing when transmitting, this bit shows that an acknowledge (1) has been sent from the receiving device bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1150 of 1220 rej09b0186-0300o icdr0?i 2 c bus data register icdr1?i 2 c bus data register h'ff7e h'ff86 iic0 iic1 bit : initial value : r/w : icdrr icdrs icdrt tdre, rdrf (internal flag) 7 icdr7 ? r/w 6 icdr6 ? r/w 5 icdr5 ? r/w 4 icdr4 ? r/w 3 icdr3 ? r/w 0 icdr0 ? r/w 2 icdr2 ? r/w 1 icdr1 ? r/w bit : initial value : r/w : 7 icdrr7 ? r 6 icdrr6 ? r 5 icdrr5 ? r 4 icdrr4 ? r 3 icdrr3 ? r 0 icdrr0 ? r 2 icdrr2 ? r 1 icdrr1 ? r bit : initial value : r/w : 7 icdrs7 ? ? 6 icdrs6 ? ? 5 icdrr5 ? ? 4 icdrs4 ? ? 3 icdrs3 ? ? 0 icdrs0 ? ? 2 icdrs2 ? ? 1 icdrs1 ? ? bit : initial value : r/w : 7 icdrt7 ? w 6 icdrt6 ? w 5 icdrt5 ? w 4 icdrt4 ? w 3 icdrt3 ? w 0 icdrt0 ? w 2 icdrt2 ? w 1 icdrt1 ? w bit : initial value : r/w : ? rdrf 0 ? ? tdre 0 ? sarx0?2nd slave address register sarx1?2nd slave address register h'ff7e h'ff86 iic0 iic1 7 svax6 0 r/w 6 svax5 0 r/w 5 svax4 0 r/w 4 svax3 0 r/w 3 svax2 0 r/w 0 fsx 1 r/w 2 svax1 0 r/w 1 svax0 0 r/w 2nd slave address format select x bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1151 of 1220 rej09b0186-0300o icmr0?i 2 c bus mode register icmr1?i 2 c bus mode register h'ff7f h'ff87 iic0 iic1 7 mls 0 r/w 6 wait 0 r/w 5 cks2 0 r/w 4 cks1 0 r/w 3 cks0 0 r/w 0 bc0 0 r/w 2 bc2 0 r/w 1 bc1 0 r/w msb-first/lsb-first select 0 msb first 1 lsb first wait insert bit 0 send data followed by acknowledge bit 1 insert wait between data and acknowledge bit transmit clock select scrx bit 5 bit 4 bit 3 clock transfer rate bits 5, 6 iicx cks2 cks1 cks0 = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz = 25 mhz 0 0 0 0 /28 179 khz 286 khz 357 khz 571 khz 714 khz 893 khz 1 /40 125 khz 200 khz 250 khz 400 khz 500 khz 625 khz 1 0 /48 104 khz 167 khz 208 khz 333 khz 417 khz 521 khz 1 /64 78.1 khz 125 khz 156 khz 250 khz 313 khz 391 khz 1 0 0 /80 62.5 khz 100 khz 125 khz 200 khz 250 khz 313 khz 1 /100 50.0 khz 80.0 khz 100 khz 160 khz 200 khz 250 khz 1 0 /112 44.6 khz 71.4 khz 89.3 khz 143 khz 179 khz 223 khz 1 /128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 195 khz 1 0 0 0 /56 89.3 khz 143 khz 179 khz 286 khz 357 khz 446 khz 1 /80 62.5 khz 100 khz 125 khz 200 khz 250 khz 313 khz 1 0 /96 52.1 khz 83.3 khz 104 khz 167 khz 208 khz 260 khz 1 /128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 195 khz 1 0 0 /160 31.3 khz 50.0 khz 62.5 khz 100 khz 125 khz 156 khz 1 /200 25.0 khz 40.0 khz 50.0 khz 80.0 khz 100 khz 125 khz 1 0 /224 22.3 khz 35.7 khz 44.6 khz 71.4 khz 89.3 khz 112 khz 1 /256 19.5 khz 31.3 khz 39.1 khz 62.5 khz 78.1 khz 97.7 khz bit counter bit 2 bit 1 bit 0 bit/frame bc2 bc1 bc0 clock sync i 2 c bus format serial format 0 0 0 8 9 1 1 2 1 0 2 3 1 3 4 1 0 0 4 5 1 5 6 1 0 6 7 1 7 8 bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1152 of 1220 rej09b0186-0300o sar0?slave address register sar1?slave address register h'ff7f h'ff87 iic0 iic1 7 sva6 0 r/w 6 sva5 0 r/w 5 sva4 0 r/w 4 sva3 0 r/w 3 sva2 0 r/w 0 fs 0 r/w 2 sva1 0 r/w 1 sva0 0 r/w slave address format select ddcswr sar sarx bit 6 bit 0 bit 0 operating mode sw fs fsx 0 0 0 i 2 c bus format sar and sarx slave addresses recognized 1 i 2 c bus format (initial value) sar slave address recognized sarx slave address ignored 1 0 i 2 c bus format sar slave address ignored sarx slave address recognized 1 synchronous serial format sar and sarx slave addresses ignored 1 ? ? must not be set bit initial value r/w : : : addrah?a/d data register ah addral?a/d data register al addrbh?a/d data register bh addrbl?a/d data register bl addrch?a/d data register ch addrcl?a/d data register cl addrdh?a/d data register dh addrdl?a/d data register dl h'ff90 h'ff91 h'ff92 h'ff93 h'ff94 h'ff95 h'ff96 h'ff97 a/d a/d a/d a/d a/d a/d a/d a/d 14 ad8 0 r 12 ad6 0 r 10 ad4 0 r 8 ad2 0 r 6 ad0 0 r 0 ? 0 r 4 ? 0 r 2 ? 0 r 15 ad9 0 r 13 ad7 0 r 11 ad5 0 r 9 ad3 0 r 7 ad1 0 r 1 ? 0 r 5 ? 0 r 3 ? 0 r bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1153 of 1220 rej09b0186-0300o adcsr?a/d control/status register h'ff98 a/d 7 adf 0 r/(w) * 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 ch3 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w note: * only 0 can be written to these bits (to clear these flags). a/d end flag 0 [clearing conditions] ? writing 0 to the adf flag after reading adf = 1 ? when dtc is started by an adi interrupt and addr is read 1 [setting conditions] ? single mode: on completion of a/d conversion ? scan mode: on completion of conversion of all specified channels a/d start 0 a/d conversion disabled 1 (1) single mode: a/d conversion starts. automatically cleared to 0 on completion of conversion on specified channel (2) scan mode: a/d conversion starts. the selected channel continues to be sequentially converted until this bit is cleared to 0 by a software, reset, or standby mode is selected, or module stop mode is selected a/d interrupt enable 0 a/d conversion end interrupt (adi) requests disabled 1 a/d conversion end interrupt (adi) requests enabled scan mode 0 single mode 1 scan mode channel select 3 channel select 2 to 0 ch3 ch2 ch1 ch0 single mode scan mode (scan = 0) (scan = 1) 0 0 0 0 an0 an0 1 an1 an0, an1 1 0 an2 an0 to an2 1 an3 an0 to an3 1 0 0 an4 an4 1 an5 an4, an5 1 0 an6 an4 to an6 1 an7 an4 to an7 1 0 0 0 an8 an8 1 an9 an8, an9 1 0 an10 an8 to an10 1 an11 an8 to an11 1 0 0 an12 an12 1 an13 an12, an13 1 0 an14 an12 to an14 1 an15 an12 to an15 bit initial value r/w : : : 0 an8 to an11 set as group 0 analog input pins, and an12 to an15 as group 1 analog input pins 1 an0 to an3 set as group 0 analog input pins, and an4 to an7 set as group 1 analog input pins
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1154 of 1220 rej09b0186-0300o adcr?a/d control register h'ff99 a/d 7 trgs1 0 r/w 6 trgs0 0 r/w 5 ? 1 ? 4 ? 1 ? 3 cks1 0 r/w 0 ? 1 ? 2 cks0 0 r/w 1 ? 1 ? time trigger select 1, 0 clock select 1, 0 trgs1 trgs0 description 0 0 enables starting of a/d conversion by software 1 enables starting of a/d conversion by tpu conversion start trigger 1 0 enables starting of a/d conversion by 8-bit timer conversion start trigger 1 enables starting of a/d conversion by external trigger pin (adtrg) cks1 cks0 description 0 0 conversion time = 530 states (max.) 1 conversion time = 266 states (max.) 1 0 conversion time = 134 states (max.) 1 conversion time = 68 states (max.) bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1155 of 1220 rej09b0186-0300o tcsr1?timer control/status register 1 h'ffa2 (w), h'ffa2 (r) wdt1 7 ovf 0 r/(w) * 6 wt/it 0 r/w 5 tme 0 r/w 4 pss 0 r/w 3 rst/nmi 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w notes: tcsr is write-protected by a password to prevent accidental overwriting. for details see section 15.2.5, notes on register access. * only 0 can be written to these bits (to clear these flags). overflow flag 0 [clearing conditions] ? when 0 is written to tme bit ? when 0 is written to ovf bit after reading tcsr when ovf = 1 1 [setting conditions] ? when tcnt overflows (h ? ff h ? 00) ? when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset timer enable 0 initializes tcnt to h ? 00 and disables the counting operation 1 tcnt performs counting operation prescaler select 0 tcnt counts the divided clock output by the -based prescaler (psm) 1 tcnt counts the divided clock output by the sub-based prescaler (pss) reset or nmi 0 nmi interrupt request 1 internal reset request timer mode select 0 interval timer mode: interval timer interrupt (wovi) request sent to cpu when overflow occurs at tcnt 1 watchdog timer mode: reset or nmi interrupt request sent to cpu when overflow occurs at tcnt clock select 2 to 0 pss csk2 csk1 csk0 clock overflow cycle * (when = 25 mhz) (when sub = 32.768 khz) 0 0 0 0 /2 20.4 s 1 /64 652.8 s 1 0 /128 1.3 ms 1 /512 5.2 ms 1 0 0 /2048 20.9 ms 1 /8192 83.6 ms 1 0 /32768 334.2 ms 1 /131072 1.34 s 1 0 0 0 sub/2 15.6 ms 1 sub/4 31.3 ms 1 0 sub/8 62.5 ms 1 sub/16 125 ms 1 0 0 sub/32 250 ms 1 sub/64 500 ms 1 0 sub/128 1 s 1 sub/256 2 s note: * the overflow cycle starts when tcnt starts counting from h ? 00 and ends when an overflow occurs. bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1156 of 1220 rej09b0186-0300o flmcr1?flash memory control register 1 h'ffa8 flash 7 fwe ?* r 6 swe1 0 r/w 5 esu1 0 r/w 4 psu1 0 r/w 3 ev1 0 r/w 0 p1 0 r/w 2 pv1 0 r/w 1 e1 0 r/w flash write enable bit note: * determined b y the state of the fwe pin. 0 when low level signal input to fwe pin (hardware protect status) 1 when high level signal input to fwe pin software write enable bit 1 0 writing disabled 1 writing enabled [setting condition] ? when fwe = 1 erase setup bit 1 0 exits erase setup 1 erase setup [setting condition] ? when fwe = 1 and swe1 = 1 program setup bit 1 0 exits program setup 1 program setup [setting condition] ? when fwe = 1 and swe1 = 1 erase verify 1 0 exits erase verify mode 1 enters erase verify mode [setting condition] ? when fwe = 1 and swe1 = 1 program verify 1 0 exits program verify mode 1 enters program verify mode [setting condition] ? when fwe = 1 and swe1 = 1 erase 1 0 exits erase mode. 1 enters erase mode [setting condition] ? when fwe = 1, swe1 = 1, and esu1 = 1 program 1 0 exits program mode 1 enters program mode [setting condition] ? when fwe = 1, swe1 = 1, and psu1 = 1 bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1157 of 1220 rej09b0186-0300o flmcr2?flash memory control register 2 h'ffa9 flash 7 fler 0 r 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 ? 0 ? 0 ? 0 ? 2 ? 0 ? 1 ? 0 ? flash memory error 0 flash memory operating normally flash memory protection against writing and erasing (error protection) is ignored [clearing condition] ? at a power-on reset and in hardware standby mode 1 shows that an error has occurred when writing to or erasing flash memory flash memory protection against writing and erasing (error protection) is enabled [setting condition] ? see section 22.8.3, error protection bit initial value r/w : : : ebr1?erase block register 1 h'ffaa flash 7 eb7 0 r/w 6 eb6 0 r/w 5 eb5 0 r/w 4 eb4 0 r/w 3 eb3 0 r/w 0 eb0 0 r/w 2 eb2 0 r/w 1 eb1 0 r/w bit initial value r/w : : : ebr2?erase block register 2 h'ffab flash 7 ? 0 r/w 6 ? 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 eb11 0 r/w 0 eb8 0 r/w 2 eb10 0 r/w 1 eb9 0 r/w bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1158 of 1220 rej09b0186-0300o flpwcr?flash memory power control register h'ffac flash 7 pdwnd 0 r/w 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 0 ? 0 r 2 ? 0 r 1 ? 0 r power-down disable 0 transition to flash memory power-down mode enabled 1 transition to flash memory power-down mode disabled bit initial value r/w : : : port1?port 1 register h'ffb0 port 7 p17 ? * r 6 p16 ? * r 5 p15 ? * r 4 p14 ? * r 3 p13 ? * r 0 p10 ? * r 2 p12 ? * r 1 p11 ? * r bit initial value r/w note: * determined by status of pins p17 to p10. : : : port2?port 2 register h'ffb1 port 7 p27 ? * r bit initial value r/w note: * determined b y status of pins p27 to p20. : : : 6 p26 ? * r 5 p25 ? * r 4 p24 ? * r 3 p23 ? * r 2 p22 ? * r 1 p21 ? * r 0 p20 ? * r
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1159 of 1220 rej09b0186-0300o port3?port 3 register h'ffb2 port 7 p37 ? * r 6 p36 ? * r 5 p35 ? * r 4 p34 ? * r 3 p33 ? * r 0 p30 ? * r 2 p32 ? * r 1 p31 ? * r bit initial value r/w note: * determined by status of pins p37 to p30. : : : port4?port 4 register h'ffb3 port 7 p47 ? * r 6 p46 ? * r 5 p45 ? * r 4 p44 ? * r 3 p43 ? * r 0 p40 ? * r 2 p42 ? * r 1 p41 ? * r note: * determined b y status of pins p47 to p40. bit initial value r/w : : : port5?port 5 register h'ffb4 port 7 ? undefined ? 6 ? undefined ? 5 ? undefined ? 4 ? undefined ? 3 ? undefined ? 0 p50 ? * r 2 p52 ? * r 1 p51 ? * r note: * determined b y status of pins p52 to p50. bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1160 of 1220 rej09b0186-0300o port7?port 7 register h'ffb6 port 7 p77 ? * r 6 p76 ? * r 5 p75 ? * r 4 p74 ? * r 3 p73 ? * r 0 p70 ? * r 2 p72 ? * r 1 p71 ? * r note: * determined b y status of pins p77 to p70. bit initial value r/w : : : port8?port 8 register h'ffb7 port 7 ? undefined ? bit initial value r/w note: * determined b y status of pins p86 to p80. : : : 6 p86 ? * r 5 p85 ? * r 4 p84 ? * r 3 p83 ? * r 2 p82 ? * r 1 p81 ? * r 0 p80 ? * r port9?port 9 register h'ffb8 port 7 p97 ? * r 6 p96 ? * r 5 p95 ? * r 4 p94 ? * r 3 p93 ? * r 0 p90 ? * r 2 p92 ? * r 1 p91 ? * r note: * determined b y status of pins p97 to p90. bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1161 of 1220 rej09b0186-0300o porta?port a register h'ffb9 port 7 ? undefined ? 6 ? undefined ? 5 ? undefined ? 4 ? undefined ? 3 pa3 ? * r 0 pa0 ? * r 2 pa2 ? * r 1 pa1 ? * r note: * determined b y status of pins pa3 to pa0. bit initial value r/w : : : portb?port b register h'ffba port 7 pb7 ? * r 6 pb6 ? * r 5 pb5 ? * r 4 pb4 ? * r 3 pb3 ? * r 0 pb0 ? * r 2 pb2 ? * r 1 pb1 ? * r note: * determined b y status of pins pb7 to pb0. bit initial value r/w : : : portc?port c register h'ffbb port 7 pc7 ? * r 6 pc6 ? * r 5 pc5 ? * r 4 pc4 ? * r 3 pc3 ? * r 0 pc0 ? * r 2 pc2 ? * r 1 pc1 ? * r note: * determined b y status of pins pc7 to pc0. bit initial value r/w : : : portd?port d register h'ffbc port 7 pd7 ? * r 6 pd6 ? * r 5 pd5 ? * r 4 pd4 ? * r 3 pd3 ? * r 0 pd0 ? * r 2 pd2 ? * r 1 pd1 ? * r note: * determined b y status of pins pd7 to pd0. bit initial value r/w : : :
appendix b internal i/o register rev. 3.00 jan 11, 2005 page 1162 of 1220 rej09b0186-0300o porte?port e register h'ffbd port 7 pe7 ? * r 6 pe6 ? * r 5 pe5 ? * r 4 pe4 ? * r 3 pe3 ? * r 0 pe0 ? * r 2 pe2 ? * r 1 pe1 ? * r note: * determined b y status of pins pe7 to pe0. bit initial value r/w : : : portf?port f register h'ffbe port 7 pf7 ? * r 6 pf6 ? * r 5 pf5 ? * r 4 pf4 ? * r 3 pf3 ? * r 0 pf0 ? * r 2 pf2 ? * r 1 pf1 ? * r note: * determined b y status of pins pf7 to pf0. bit initial value r/w : : : portg?port g register h'ffbf port 7 ? undefined ? 6 ? undefined ? 5 ? undefined ? 4 pg4 ? * r 3 pg3 ? * r 0 pg0 ? * r 2 pg2 ? * r 1 pg1 ? * r note: * determined b y status of pins pg4 to pg0. bit initial value r/w : : :
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1163 of 1220 rej09b0186-0300o appendix c i/o port block diagrams c.1 port 1 block diagrams r p1nddr c qd reset internal data bus internal address bus wddr1 reset wdr1 r p1ndr c qd p1n * rdr1 rpor1 ppg module tpu module pulse output enable pulse output output compare output/pwm output enable output compare output/ pwm output input capture input wddr1: wdr1: rdr1: rpor1: n = 0 or 1 note: * write to p1ddr write to p1dr read p1dr read port 1 legend: priority order: address output > output compare output > pwm output > dma transfer acknowledge output > pulse output > dr output figure c.1 (a) port 1 block diagram (pins p10 and p11)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1164 of 1220 rej09b0186-0300o r p1nddr c qd reset wddr1 reset wdr1 r p1ndr c qd p1n rdr1 rpor1 ppg module tpu module pulse output enable output compare output / pwm output enable output compare output / pwm output pulse output external clock input input capture input * legend: wddr1: write to p1ddr wdr1: write to p1dr rdr1: read p1dr rpor1: read port 1 n = 2 or 3 note: * priorit y order: address output > output compare output/pwm output > pulse output > dr output internal data bus internal address bus figure c.1 (b) port 1 block diagram (pins p12 and p13)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1165 of 1220 rej09b0186-0300o r p14ddr c qd reset wddr1 reset wdr1 r p14dr c qd p14 rdr1 rpor1 ppg module tpu module pulse output enable interrupt controller irq0 interrupt input output compare output / pwm output enable output compare output / pwm output pulse output input capture input * legend: wddr1: write to p1ddr wdr1: write to p1dr rdr1: read p1dr rpor1: read port 1 note: * priorit y order: output compare output/pwm output > pulse output > dr output internal data bus figure c.1 (c) port 1 block diagram (pin p14)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1166 of 1220 rej09b0186-0300o r p15ddr c qd reset wddr1 reset wdr1 r p15dr c qd p15 rdr1 rpor1 ppg module tpu module pulse output enable output compare output / pwm output enable output compare output / pwm output pulse output input capture input external clock input * legend: wddr1: write to p1ddr wdr1: write to p1dr rdr1: read p1dr rpor1: read port 1 note: * priorit y order: output compare output/pwm output > pulse output > dr output internal data bus figure c.1 (d) port 1 block diagram (pin p15)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1167 of 1220 rej09b0186-0300o r p16ddr c qd reset wddr1 reset internal data bus wdr1 r p16dr c qd p16 rdr1 rpor1 ppg module tpu module pulse output enable output compare output/pwm output enable output compare output/ pwm output pulse output pwm module pwm2 output enable pwm2 output input capture input input controller irq1 interrupt input * legend: wddr1: wdr1: rdr1: rpor1: write to p1ddr write to p1dr read p1dr read port 1 note: * priorit y order: output compare output/pwm output > pwm2 output > pulse output > dr output figure c.1 (e) port 1 block diagram (pin p16)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1168 of 1220 rej09b0186-0300o r p17ddr c qd reset wddr1 reset internal data bus wdr1 r p17dr c qd p17 rdr1 rpor1 ppg module tpu module pulse output enable output compare output/pwm output enable output compare output/ pwm output pulse output pwm module pwm3 output enable pwm3 output input capture input external clock input * legend: wddr1: wdr1: rdr1: rpor1: write to p1ddr write to p1dr read p1dr read port 1 note: * priorit y order: output compare output/pwm output > pwm3 output > pulse output > dr output figure c.1 (f) port 1 block diagram (pin p17)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1169 of 1220 rej09b0186-0300o c.2 port 2 block diagram r p2nddr c qd reset wddr2 reset wdr2 r p2ndr c qd p2n rdr2 rpor2 ppg module tpu module pulse output enable output compare output / pwm output enable output compare output / pwm output pulse output input capture input external clock input * note: * priority order: output compare output/pwm output > pwm output > pulse output > dr output legend: wddr2: wdr2: rdr2: rpor2: write to p2ddr write to p2dr read p2dr read port 2 internal data bus figure c.2 port 2 block diagram (pins p20 to p27)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1170 of 1220 rej09b0186-0300o c.3 port 3 block diagrams r p30ddr c qd reset internal data bus wddr3 reset wdr3 r c qd p30 rdr3 rodr3 rpor3 txd0/irtxd sci module serial transmit enable serial transmit data notes: 1. output enable signal 2. open drain control signal p30dr reset wodr3 r c qd p30odr * 1 * 2 legend: wddr3: wdr3: wodr3: rdr3: rpor3: rodr3: write to p3ddr write to p3dr write to p3odr read p3dr read port 3 read p3odr figure c.3 (a) port 3 block diagram (pin p30)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1171 of 1220 rej09b0186-0300o r p31ddr c qd reset internal data bus wddr3 reset wdr3 r c qd p31 rdr3 rodr3 rpor3 sci module serial receive data enable serial receive data rxd0/irrxd p31dr reset wodr3 r c qd p31odr * 1 * 2 notes: 1. output enable signal 2. open drain control signal legend: wddr3: wdr3: wodr3: rdr3: rpor3: rodr3: write to p3ddr write to p3dr write to p3odr read p3dr read port 3 read p3odr figure c.3 (b) port 3 block diagram (pin p31)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1172 of 1220 rej09b0186-0300o r p32ddr c qd reset internal data bus wddr3 reset wdr3 r c qd p32 rdr3 rodr3 rpor3 sci module serial clock output enable serial clock input enable serial clock output iic1 module sda1 output iic1 output enable sda1 input interrupt controller irq4 interrupt input p32dr reset wodr3 r c qd p32odr * 2 * 3 * 1 serial clock input notes: 1. priority order: iic output > serial clock output > dr outpu t 2. output enable signal 3. open drain control signal legend: wddr3: wdr3: wodr3: rdr3: rpor3: rodr3: write to p3ddr write to p3dr write to p3odr read p3dr read port 3 read p3odr figure c.3 (c) port 3 block diagram (pin p32)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1173 of 1220 rej09b0186-0300o r p33ddr c qd reset internal data bus wddr3 reset wdr3 r c qd p33 rdr3 rodr3 rpor3 sci module serial transmit enable serial transmit data p33dr reset wodr3 r c qd p33odr * 1 * 2 txd1 iic1 module scl1 output iic1 output enable scl1 input notes: 1. output enable signal 2. open drain control signal legend: wddr3: wdr3: wodr3: rdr3: rpor3: rodr3: write to p3ddr write to p3dr write to p3odr read p3dr read port 3 read p3odr figure c.3 (d) port 3 block diagram (pin p33)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1174 of 1220 rej09b0186-0300o r p34ddr c qd reset internal data bus wddr3 reset wdr3 r c qd p34 rdr3 rodr3 rpor3 sci module iic0 module sda0 output sda0 input iic0 output enable serial receive data enable serial receive data rxd1 p34dr reset wodr3 r c qd p34odr * 1 * 2 * 3 notes: 1. output enable signal 2. open drain control signal 3. priority order: iic output > dr output legend: wddr3: wdr3: wodr3: rdr3: rpor3: rodr3: write to p3ddr write to p3dr write to p3odr read p3dr read port 3 read p3odr figure c.3 (e) port 3 block diagram (pin p34)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1175 of 1220 rej09b0186-0300o r p35ddr c qd reset internal data bus wddr3 reset wdr3 r c qd p3 5 rdr3 rodr3 rpor3 sci module iic0 module scl0 output scl0 input iic0 output enable irq5 interrupt input interrupt controller serial clock output enable serial clock output serial clock input enable p35dr reset wodr3 r c qd p35odr * 2 * 3 * 1 serial clock input notes: 1. priority order: iic output > serial clock output > dr outpu t 2. output enable signal 3. open drain control signal legend: wddr3: wdr3: wodr3: rdr3: rpor3: rodr3: write to p3ddr write to p3dr write to p3odr read p3dr read port 3 read p3odr figure c.3 (f) port 3 block diagram (pin p35)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1176 of 1220 rej09b0186-0300o r p36ddr c qd reset internal data bus wddr3 reset wdr3 r c qd p36 rdr3 rodr3 rpor3 sci module serial receive data enable serial receive data rxd4 p36dr reset wodr3 r c qd p36odr * 1 * 2 notes: 1. output enable signal 2. open drain control signal legend: wddr3: wdr3: wodr3: rdr3: rpor3: rodr3: write to p3ddr write to p3dr write to p3odr read p3dr read port 3 read p3odr figure c.3 (g) port 3 block diagram (pin p36)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1177 of 1220 rej09b0186-0300o r p37ddr c qd reset internal data bus wddr3 reset wdr3 r c qd p37 rdr3 rodr3 rpor3 sci module serial transmit enable serial transmit data p37dr reset wodr3 r c qd p37odr txd4 * 1 * 2 notes: 1. output enable signal 2. open drain control signal legend: wddr3: wdr3: wodr3: rdr3: rpor3: rodr3: write to p3ddr write to p3dr write to p3odr read p3dr read port 3 read p3odr figure c.3 (h) port 3 block diagram (pin p37)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1178 of 1220 rej09b0186-0300o c.4 port 4 block diagrams p4n rpor4 internal data bus a/d converter module analog input legend: rpor4: read port 4 n = 0 to 5 figure c.4 (a) port 4 block diagram (pins p40 to p45) p4n rpor4 internal data bus a/d converter module analog input d/a converter module output enable analog output legend: rpor4: read port 4 n = 6 or 7 figure c.4 (b) port 4 block diagram (pins p46 and p47)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1179 of 1220 rej09b0186-0300o c.5 port 5 block diagrams r p50ddr c qd reset wddr5 reset wdr5 r c qd p50 rdr5 rpor5 sci module serial transmit enable serial transmit data txd2 p50dr legend: wddr5: wdr5: rdr5: rpor5: write to p5ddr write to p5dr read p5dr read port 5 internal data bus figure c.5 (a) port 5 block diagram (pin p50)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1180 of 1220 rej09b0186-0300o r p51ddr c qd wddr5 wdr5 r c qd p51 rdr5 rpor5 serial receive data enable serial receive data rxd2 p51dr reset reset sci module legend: wddr5: wdr5: rdr5: rpor5: write to p5ddr write to p5dr read p5dr read port 5 internal data bus figure c.5 (b) port 5 block diagram (pin p51)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1181 of 1220 rej09b0186-0300o r p52ddr c qd wddr5 wdr5 r p52dr c qd p52 rdr5 rpor5 serial clock output enable serial clock output serial clock input serial clock input enable reset reset sci module legend: wddr5: wdr5: rdr5: rpor5: write to p5ddr write to p5dr read p5dr read port 5 internal data bus figure c.5 (c) port 5 block diagram (pin p52)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1182 of 1220 rej09b0186-0300o c.6 port 7 block diagrams r p7nddr c qd reset internal data bus wddr7 mode 7 modes 4 to 6 reset wdr7 r p7ndr c qd p7n rdr7 rpor7 bus controller chip select 8-bit timer reset/count inpu t wddr7: wdr7: rdr7: rpor7: n = 0 or 1 write to p7ddr write to p7dr read p7dr read port 7 legend: figure c.6 (a) port 7 block diagram (pins p70 and p71)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1183 of 1220 rej09b0186-0300o r p72ddr c qd reset internal data bus wddr7 mode 7 modes 4 to 6 reset wdr7 r p72dr c qd p72 rdr7 rpor7 bus controller chip select 8-bit timer timer output tmo0 timer output enable * wddr7: wdr7: rdr7: rpor7: write to p7ddr write to p7dr read p7dr read port 7 legend: note: * priority order: (mode 7) 8-bit timer output > dr output (modes 4 to 6) chip select output > 8-bit timer output > dr output figure c.6 (b) port 7 block diagram (pin p72)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1184 of 1220 rej09b0186-0300o r p73ddr c qd reset internal data bus wddr7 mode 7 modes 4 to 6 reset wdr7 r p73dr c qd p73 rdr7 rpor7 bus controller chip select 8-bit timer timer output tmo1 timer output enable * wddr7: wdr7: rdr7: rpor7: write to p7ddr write to p7dr read p7dr read port 7 legend: note: * priority order: (mode 7) 8-bit timer output > dr output (modes 4 to 6) chip select output > 8-bit timer output > dr output figure c.6 (c) port 7 block diagram (pin p73)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1185 of 1220 rej09b0186-0300o r p74ddr c qd reset internal data bus wddr7 reset wdr7 r c qd p74 rdr7 rpor7 8-bit timer 8-bit timer output enabl e 8-bit timer output system controller manual reset input enable manual reset input p74dr wddr7: wdr7: rdr7: rpor7: write to p7ddr write to p7dr read p7dr read port 7 legend : figure c.6 (d) port 7 block diagram (pin p74)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1186 of 1220 rej09b0186-0300o r p75ddr c qd reset internal data bus wddr7 reset wdr7 r p75dr c qd p75 rdr7 rpor7 8-bit timer sci module timer output enable serial clock output enable serial clock input enable serial clock timer output serial clock input * wddr7: wdr7: rdr7: rpor7: write to p7ddr write to p7dr read p7dr read port 7 legend: note: * priorit y order: serial clock output > 8-bit timer output > dr output figure c.6 (e) port 7 block diagram (pin p75)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1187 of 1220 rej09b0186-0300o r p76ddr c qd reset internal data bus wddr7 reset wdr7 r c qd p76 rdr7 rpor7 sci module serial receive data enable serial receive data rxd3 p76dr wddr7: wdr7: rdr7: rpor7: write to p7ddr write to p7dr read p7dr read port 7 legend: figure c.6 (f) port 7 block diagram (pin p76)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1188 of 1220 rej09b0186-0300o r p77ddr c qd reset internal data bus wddr7 reset wdr7 r c qd p77 rdr7 rpor7 sci module serial transmit enable data serial transmit data txd3 p77dr wddr7: wdr7: rdr7: rpor7: write to p7ddr write to p7dr read p7dr read port 7 legend: figure c.6 (g) port 7 block diagram (pin p77)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1189 of 1220 rej09b0186-0300o c.7 port 8 block diagrams d wddr8 wdr8 r p8ndr c qd p8n rdr8 rpor8 r c qd p8nddr dma request reset reset dma controller legend: wddr8: wdr8: rdr8: rpor8: write to p8ddr write to p8dr read p8dr read port 8 internal data bus figure c.7 (a) port 8 block diagram (pins p80 and p81)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1190 of 1220 rej09b0186-0300o r p8nddr c qd wddr8 wdr8 r c qd p8n rdr8 rpor8 dma transfer end enable dma transfer end p8ndr note: * priority order: dma transfer end output > dr output * reset reset dma controller legend: wddr8: wdr8: rdr8: rpor8: write to p8ddr write to p8dr read p8dr read port 8 internal data bus figure c.7 (b) port 8 block diagram (pins p82 and p83)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1191 of 1220 rej09b0186-0300o r p8nddr c qd wddr8 wdr8 r c qd p8n rdr8 rpor8 dma transfer acknowledge p8ndr * dma transfer acknowledge enable reset reset dma controller legend: wddr8: wdr8: rdr8: rpor8: write to p8ddr write to p8dr read p8dr read port 8 internal data bus note: * priorit y order: dma transfer acknowled g e output > dr output figure c.7 (c) port 8 block diagram (pins p84 and p85)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1192 of 1220 rej09b0186-0300o d wddr8 wdr8 r p86dr c qd p86 rdr8 rpor8 r c qd p86ddr reset reset legend: wddr8: wdr8: rdr8: rpor8: write to p8ddr write to p8dr read p8dr read port 8 internal data bus figure c.7 (d) port 8 block diagram (pin p86)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1193 of 1220 rej09b0186-0300o c.8 port 9 block diagrams p9n rpor9 internal data bus a/d converter module analog input rpor9: n = 0 to 5 read port 9 legend: figure c.8 (a) port 9 block diagram (pins p90 to p95) p9n rpor9 internal data bus a/d converter module analog input d/a converter module output enable analog output rpor9: n = 6 or 7 read port 9 legend: figure c.8 (b) port 9 block diagram (pins p96 and p97)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1194 of 1220 rej09b0186-0300o c.9 port a block diagrams r panpcr c qd reset internal data bus internal address bus wpcra reset wdra r c qd pan rdra rodra rpora pandr reset wddra r c qd panddr reset wodra rpcra r c qd panodr * 1 * 2 modes 4 to 6 address enable notes: 1. output enable signal 2. open drain control signal wddra: wdra: wodra: wpcra: rdra: rpora: rodra: rpcra: n = 0 to 7 write to paddr write to padr write to paodr write to papcr read padr read port a read paodr read papcr legend: figure c.9 port a block diagram (pins pa0 to pa7)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1195 of 1220 rej09b0186-0300o c.10 port b block diagram r pbnpcr c qd reset internal address bus internal data bus wpcrb reset wdrb r c qd pb1 rdrb rodrb rporb pbndr reset wddrb r c qd pbnddr reset wodrb rpcrb r c qd pbnodr * 1 * 2 modes 4 to 6 address enable notes: 1. output enable signal 2. open drain control signal wddrb: wdrb: wodrb: wpcrb: rdrb: rporb: rodrb: rpcrb: n = 0 to 7 write to pbddr write to pbdr write to pbodr write to pbpcr read pbdr read port b read pbodr read pbpcr legend: figure c.10 port b block diagram (pins pb0 to pb7)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1196 of 1220 rej09b0186-0300o c.11 port c block diagrams r pcnpcr c qd reset internal address bus internal data bus wpcrc reset wdra r c qd pcn rdrc rodrc rporc pcndr reset wddra r c qd pcnddr reset wodrc rpcrc r c qd pcnodr * 1 * 2 modes 4 and 5 mode 6 notes: 1. output enable signal 2. open drain control signal wddra: wdra: wodra: wpcra: rdra: rpora: rodra: rpcra: n = 0 to 5 write to pcddr write to pcdr write to pcodr write to pcpcr read pcdr read port a read pcodr read pcpcr legend: figure c.11 (a) port c block diagram (pins pc0 to pc5)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1197 of 1220 rej09b0186-0300o r pcnpcr c qd reset internal address bus internal data bus wpcrc reset wdra r c qd pcn rdrc rodrc rporc pcndr reset wddra r c qd pcnddr reset wodrc rpcrc r c qd pcnodr * 1 * 2 modes 4 and 5 mode 6 pwm output pwm output enable notes: 1. output enable signal 2. open drain control signal wddra: wdra: wodra: wpcra: rdra: rpora: rodra: rpcra: n = 6 or 7 write to pcddr write to pcdr write to pcodr write to pcpcr read pcdr read port a read pcodr read pcpcr legend: figure c.11 (b) port c block diagram (pins pc6 and pc7)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1198 of 1220 rej09b0186-0300o c.12 port d block diagram r pdnpcr c qd reset internal upper data bus wpcrd reset wdrd external address upper write r c qd pdn rdrd rpord pdndr wddrd c qd pdnddr rpcrd mode 7 modes 4 to 6 external address write reset r external address upper read wddrd: wdrd: wpcrd: rdrd: rpord: rpcrd: n = 1 to 7 write to pdddr write to pddr write to pdpcr read pddr read port d read pdpcr legend: figure c.12 port d block diagram (pins pd1 to pd7)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1199 of 1220 rej09b0186-0300o c.13 port e block diagram r penpcr c qd reset internal upper data bus internal lower data bus wpcre reset wdre r c qd pen rdre rpore pendr wddre c qd penddr rpcre mode 7 modes 4 to 6 external address write reset r external addres lower read wddre: wdre: wpcre: rdre: rpore: rpcre: n = 1 to 7 write to peddr write to pedr write to pepcr read pedr read port e read pepcr legend: figure c.13 port e block diagram (pins pe1 to pe7)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1200 of 1220 rej09b0186-0300o c.14 port f block diagrams r pf0ddr c qd reset internal data bus wddrf reset wdrf r c qd pf0 rdrf rporf bus request input irq interrupt input pf0dr bus controller brle bit modes 4 to 6 wddrf: wdrf: rdrf: rporf: write to pfddr write to pfdr read pfdr read port f legend: figure c.14 (a) port f block diagram (pin pf0)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1201 of 1220 rej09b0186-0300o r pf1ddr c qd reset internal data bus wddrf modes 4 to 6 buzz output buzz output enable reset wdrf r pf1dr c qd pf1 rdrf rporf bus controller brle output bus request acknowledge output wddrf: wdrf: rdrf: rporf: write to pfddr write to pfdr read pfdr read port f legend: figure c.14 (b) port f block diagram (pin pf1)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1202 of 1220 rej09b0186-0300o r pf2ddr c qd reset internal data bus wddrf reset wdrf r pf2dr c qd pf2 rdrf rporf bus request output enable bus request output wait input lcas output enable lcass bit lcas output bus controller wait enable modes 4 to 6 modes 4 to 6 modes 4 to 6 wddrf: wdrf: rdrf: rporf: write to pfddr write to pfdr read pfdr read port f legend: figure c.14 (c) port f block diagram (pin pf2)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1203 of 1220 rej09b0186-0300o r pf3ddr c qd reset internal data bus wddrf reset wdrf r pf3dr c qd pf3 rdrf rporf bus controller adtrg input irq interrupt inpu t lwr output modes 4 to 6 wddrf: wdrf: rdrf: rporf: write to pfddr write to pfdr read pfdr read port f legend: figure c.14 (d) port f block diagram (pin pf3)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1204 of 1220 rej09b0186-0300o r pf4ddr c qd reset internal data bus modes 4 to 6 wddrf reset wdrf r pf4dr c qd pf4 rdrf rporf bus controlle r hwr output wddrf: wdrf: rdrf: rporf: write to pfddr write to pfdr read pfdr read port f legend: figure c.14 (e) port f block diagram (pin pf4)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1205 of 1220 rej09b0186-0300o r pf5ddr c qd reset internal data bus wddrf reset modes 4 to 6 wdrf r pf5dr c qd pf5 rdrf rporf bus controlle r rd output wddrf: wdrf: rdrf: rporf: write to pfddr write to pfdr read pfdr read port f legend: figure c.14 (f) port f block diagram (pin pf5)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1206 of 1220 rej09b0186-0300o r pf6ddr c qd reset internal data bus wddrf reset modes 4 to 6 wdrf r pf6dr c qd pf6 rdrf rporf bus controller lcas output lcas output enable lcass as output wddrf: wdrf: rdrf: rporf: write to pfddr write to pfdr read pfdr read port f legend: figure c.14 (g) port f block diagram (pin pf6)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1207 of 1220 rej09b0186-0300o d wddrf reset wdrf r pf7dr c qd pf7 rdrf rporf * set priority * wddrf: wdrf: rdrf: rporf: write to pfddr write to pfdr read pfdr read port f legend: figure c.14 (h) port f block diagram (pin pf7)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1208 of 1220 rej09b0186-0300o c.15 port g block diagrams r pg0ddr c qd reset internal data bus wddrg modes 4 to 6 reset wdrg r pg0dr c qd pg0 rdrg rporg bus controller irq interrupt input cas enable cas output wddrg: wdrg: rdrg: rporg: write to pgddr write to pgdr read pgdr read port g legend: figure c.15 (a) port g block diagram (pin pg0)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1209 of 1220 rej09b0186-0300o r pg1ddr c qd reset internal data bus wddrg reset modes 4 to 6 wdrg r pg1dr c qd pg1 rdrg rporg bus controller oe output oe output enable chip select wddrg: wdrg: rdrg: rporg: write to pgddr write to pgdr read pgdr read port g legend: figure c.15 (b) port g block diagram (pin pg1)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1210 of 1220 rej09b0186-0300o r pgnddr c qd reset wddrg reset wdrg r pgndr c qd pgn rdrg rporg bus controlle r chip select modes 4 to 6 internal data bus wddrg: wdrg: rdrg: rporg: n = 2 or 3 write to pgddr write to pgdr read pgdr read port g legend: figure c.15 (c) port g block diagram (pins pg2 and pg3)
appendix c i/o port block diagrams rev. 3.00 jan 11, 2005 page 1211 of 1220 rej09b0186-0300o qd wddrg reset wdrg r pg4dr c qd pg4 rdrg rporg bus controlle r chip select modes 4 to 6 d reset r modes 4 and 5 modes 6 and 7 internal data bus s c qd pg4ddr wddrg: wdrg: rdrg: rporg: write to pgddr write to pgdr read pgdr read port g legend: figure c.15 (d) port g block diagram (pin pg4)
appendix d pin states rev. 3.00 jan 11, 2005 page 1212 of 1220 rej09b0186-0300o appendix d pin states d.1 port states in each mode table d.1 i/o port states in each processing state port name pin name mcu operating mode power- on reset manual reset hardware standby mode software standby mode bus release state program execution state sleep mode port 1 4 to 7 t kept t kept kept i/o port port 2 4 to 7 t kept t kept kept i/o port port 3 4 to 7 t kept t kept kept i/o port port 4 4 to 7 t t t t t input port port 5 4 to 7 t kept t kept kept i/o port p73/ cs7 p72/ cs6 p71/ cs5 p70/ cs4 7 4 to 6 t t kept kept t t kept [ddr ope = 0] t [ddr ope = 1] h kept t i/o port [ddr = 0] input port [ddr = 1] cs7 to cs4 port 8 4 to 7 t kept t kept kept i/o port port 9 4 to 7 t t t t t input port port a 4, 5 6 l t kept kept t t [address output, ope = 0] t [address output, ope = 1] kept [otherwise] kept [address output] t [otherwise] kept [address output] a23 to a16 [otherwise] i/o port 7 t kept t kept kept i/o port port b 4, 5 6 l t kept kept t t [address output, ope = 0] t [address output, ope = 1] kept [otherwise] kept [address output] t [otherwise] kept [address output] a15 to a8 [otherwise] i/o port 7 t kept t kept kept i/o port
appendix d pin states rev. 3.00 jan 11, 2005 page 1213 of 1220 rej09b0186-0300o port name pin name mcu operating mode power- on reset manual reset hardware standby mode software standby mode bus release state program execution state sleep mode port c 4, 5 l kept t [ope = 0] t [ope = 1] kept ta7 to a0 6 t kept t [ddr = 1, ope = 0] t [ddr = 1, ope = 1] kept [ddr = 0] kept t [ddr = 1] a7 to a0 [ddr = 0] i/o port 7 t kept t kept kept i/o port port d 4 to 6 t t * t t t data bus 7 t kept t kept kept i/o port port e 4 to 6 8 bit bus t kept t kept kept i/o port 16 bit bus tt * t t t data bus 7 t kept t kept kept i/o port pf7/ 4 to 6 clock output kept t [ddr = 0] t [ddr = 1] h kept [ddr = 0] t [ddr = 1] clock output 7 t kept t [ddr = 0] t [ddr = 1] h kept [ddr = 0] t [ddr = 1] clock output pf6/ as lcas 4 to 6 h h t [ope = 0] t [lcas output, ope = 1] lcas [as output, ope = 1] h t [lcas output] lcas [otherwise] as 7 t kept t kept kept i/o port
appendix d pin states rev. 3.00 jan 11, 2005 page 1214 of 1220 rej09b0186-0300o port name pin name mcu operating mode power- on reset manual reset hardware standby mode software standby mode bus release state program execution state sleep mode pf5/ rd pf4/ hwr pf3/ lwr / adtrg / 4 to 6 h h t [ope = 0] t [ope = 1] h t rd , hwr , lwr irq3 7 t kept t kept kept i/o port pf2/ lcas / wait / breqo 4 to 6 t [cas output] h [otherwise] kept t [lcas output, ope = 0] t [lcas output, ope = 1] lcas [otherwise] kept [lcas output] t [breqoe = 1] breqo [waite = 1] t [lcas output] lcas [breqoe = 1] breqo [waite = 1] wait 7 t kept t kept kept i/o port pf1/ back buzz 4 to 6 t kept t [brle = 0, buzze = 0] i/o port [brle = 0, buzze = 1] h [brle = 1] h [brle = 0, buzze = 0] i/o port [brle = 0, buzze = 1] h [brle = 1] l [brle = 0, buzze = 0] i/o port [brle = 0, buzze = 1] buzz [brle = 1] back 7 t kept t kept kept i/o port pf0/ breq / irq2 4 to 6 t kept t [brle = 0] kept [brle = 1] t t[brle = 0] i/o port [brle = 1] breq 7 t kept t kept kept i/o port pg4/ cs0 4, 5 6 h t kept t [ddr = 1, ope = 0] t [ddr = 1, ope = 1] h [ddr = 0] t t [ddr = 0] input port [ddr = 1] cs0 7 t kept t kept kept i/o port
appendix d pin states rev. 3.00 jan 11, 2005 page 1215 of 1220 rej09b0186-0300o port name pin name mcu operating mode power- on reset manual reset hardware standby mode software standby mode bus release state program execution state sleep mode pg3/ cs1 pg2/ cs2 4 to 6 t kept t [ddr = 1, ope = 0] t [ddr = 1, ope = 1] h [ddr = 0] t t [ddr = 0] input port [ddr = 1] cs2 to cs1 7 t kept t kept kept i/o port pg1/ cs3 / oe / irq7 4 to 6 t kept t [ddr = 1, ope = 0] t [ddr = 1, ope = 1] h [ddr = 0] t t [ddr = 0] input port [oe = 0, ddr = 1] cs3 [oe = 1, ddr = 1] oe 7 t kept t kept kept i/o port pg0/ cas / irq6 4 to 6 t kept t [drame = 0] kept [drame = 1, ope = 1] cas [drame = 1, ope = 1] t t [drame = 0] i/o port [drame = 1] cas 7 t kept t kept kept i/o port legend: h: high level l: low level t: high impedance kept: input port becomes high-impedance, output port retains state ddr: data direction register ope: output port enable waite: wait input enable brle: bus release enable breqoe: breqo pin enable drame: dram space setting lcase: dram space setting, cw2 = lcass = 0 note: * indicates the state after completion of the executing bus cycle.
appendix e timing of transition to and recovery from hardware standby mode rev. 3.00 jan 11, 2005 page 1216 of 1220 rej09b0186-0300o appendix e timing of transition to and recovery from hardware standby mode timing of transition to hardware standby mode (1) to retain ram contents with the rame bit set to 1 in syscr, drive the res signal low at least 10 states before the stby signal goes low, as shown below. res must remain low until stby signal goes low (delay from stby low to res high: 0 ns or more). stby res t 2 0 ns t 1 10 t cyc figure e.1 timing of transition to hardware standby mode (2) to retain ram contents with the rame bit cleared to 0 in syscr, or when ram contents do not need to be retained, res does not have to be driven low as in (1). timing of recovery from hardware standby mode drive the res signal low and the nmi signal high approximately 100 ns or more before stby goes high to execute a power-on reset. t osc t nmirh t 100 ns nmi stby res figure e.2 timing of recovery from hardware standby mode
appendix f product code lineup rev. 3.00 jan 11, 2005 page 1217 of 1220 rej09b0186-0300o appendix f product code lineup table f.1 h8s/2643 group product code lineup product type product code mark code package (package code) h8s/2643 f-ztat hd64f2643 hd64f2643fc 144-pin qfp (fp-144j) hd64f2643tf 144-pin tqfp (tfp-144) masked rom HD6432643 HD6432643fc 144-pin qfp (fp-144j) HD6432643tf 144-pin tqfp (tfp-144) h8s/2642 hd6432642 hd6432642fc 144-pin qfp (fp-144j) hd6432642tf 144-pin tqfp (tfp-144) h8s/2641 hd6432641 hd6432641fc 144-pin qfp (fp-144j) hd6432641tf 144-pin tqfp (tfp-144)
appendix g package dimensions rev. 3.00 jan 11, 2005 page 1218 of 1220 rej09b0186-0300o appendix g package dimensions figures g.1 and g.2 show the fp-144j and tfp-144 package dimensions of the h8s/2643 group. package code jedec jeita mass (reference value) fp-144j ? conforms 2.4 g * dimension including the plating thickness base material dimension 0.10 m 20 22.0 0.2 73 36 144 0.5 0.10 3.05 max 0? ? 8? 22.0 0.2 108 72 37 109 1 0.17 0.05 2.70 0.22 0.05 0.5 0.1 1.0 0.10 +0.15 ?0.10 1.25 0.20 0.04 0.15 0.04 * * unit: mm figure g.1 fp-144j package dimensions
appendix g package dimensions rev. 3.00 jan 11, 2005 page 1219 of 1220 rej09b0186-0300o package code jedec jeita mass (reference value) tfp-144 ? conforms 0.6 g * dimension including the plating thickness base material dimension 108 73 136 0 ? ? 8 ? 0.08 0.07 m 18.0 0.2 72 144 109 37 18.0 0.2 * 0.18 0.05 0.4 1.20 max 1.0 0.5 0.1 16 1.00 0.10 0.05 * 0.17 0.05 0.16 0.04 0.15 0.04 1.0 unit: mm figure g.2 fp-144 package dimensions
appendix g package dimensions rev. 3.00 jan 11, 2005 page 1220 of 1220 rej09b0186-0300o
renesas 16-bit single-chip microcomputer hardware manual h8s/2643 group, h8s/2643f-ztat ? publication date: 1st edition, may, 2000 rev.3.00, january 11, 2005 published by: sales strategic planning div. renesas technology corp. edited by: technical documentation & information department renesas kodaira semiconductor co., ltd. ? 2005. renesas technology corp. all rights reserved. printed in japan.
sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. unit2607 ruijing building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices colophon 2.0
h8s/2643 group, h8s/2643f-ztat tm rej09b0186-0300o hardware manual 1753, shimonumabe, nakahara-ku, kawasaki-shi, kanagawa 211-8668 japan

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